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High Quality Test Pattern Generation and Boolean Satisfiability

Stephan Eggersglüß,
Rolf Drechsler

ISBN 1441999752


This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT). A fast and highly fault efficient SAT-based ATPG framework is presented which is also to generate high-quality delay tests such as robust path delay tests, as well as tests with long propagation paths to detect small delay defects.
The aim of the techniques and methodologies presented in this book is to improve SAT-based ATPG, in order to make it applicable in industrial practice. Readers will learn to improve the performance and robustness of the overall test generation process, so that the ATPG algorithm reliably will generate test patterns for most targeted faults in acceptable run time to meet the high fault coverage demands of the industry.

The techniques and improvements presented in this book provide the following advantages:
  • Provides a comprehensive introduction to test generation and Boolean Satisfiability;
  • Describes a highly fault efficient SAT-based ATPG framework;
  • Introduces circuit-oriented SAT solving techniques, which make use of structural information and are able to accelerate the search process significantly;
  • Provides SAT formulations for the prevalent delay fault models, in addition to the classical stuck-at fault model;
  • Includes an industrial perspective on the state-of-the-art in the testing, along with SAT; two topics typically distinguished from each other;


Prof. Dr. Rolf Drechsler Rolf Drechsler received his diploma and Dr. phil. nat. degree in computer science from the J.W. Goethe-University in Frankfurt am Main, Germany, in 1992 and 1995, respectively. He was with the Institute of Computer Science at the Albert-Ludwigs-University of Freiburg im Breisgau, Germany from 1995 to 2000. He joined the Corporate Technology Department of Siemens AG, Munich in 2000, where he worked as a Senior Engineer in the formal verification group. Since October 2001 he has been with the University of Bremen, Germany, where he is now a full professor for computer architecture. His research interests include data structures logic synthesis, test, and verification.

Dipl.Inf. Stephan Eggersglüß Stephan Eggersglüß received his diploma in Computer Science from the University of Bremen, Bremen, Germany in 2006. In this year, he also was with the Design-for-Test group of Philips Semiconductors, Hamburg, Germany. Since then he has been with the computer architecture group at the University of Bremen, Bremen, Germany, where he received his doctor degree in 2010. Since 2010, he is also with the German Research Center for Artificial Intelligence (DFKI). Stephan Eggersglüß is recipient of the IEEE TTTC's E.J. McCluskey Best Doctoral Thesis Award 2010 and EDAA Outstanding Dissertation Award 2011. His research interests include the satisfiability problem, test in general, and delay test generation in particular.

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