True-PolyTronik: Securing Circuits Against Laser Logic State Imaging Attack Using RFET
Author: Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, and Rolf Drechsler
Conference:
International Conference on VLSI Design 2025
Pdf | Reference: Bangalore, India, 2025
Exploring the Potential of Dynamic Quantum Circuit for Improving Device Scalability
Author: Abhoy Kole, Kamalika Datta, Rolf Drechsler
Conference:
IEEE International System-on-Chip Conference
Reference: Dresden, Germany, 2024
Let’s Brainstorm: Personalized Chatbot Prototype as Creativity Partner in Idea Crowdsourcing Platforms
Author: Sana Hassan Imam, Rolf Drechsler
Conference:
Diginomics Summer Conference
Pdf | Reference: Bremen, Germany, 2024
From Bugs to Fixes: HDL Bug Identification and Patching using LLMs and RAG
Author: Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler
Conference:
LLM-Aided Design, 2024 (LAD)
Pdf | Reference: San Jose, CA, USA, 2024
EvoAl — Codeless Domain-Optimisation
Author: Bernhard J. Berger, Christina Plump, Lauren Paul, Rolf Drechsler
Conference:
GECCO Companion
Pdf | Reference: Melbourne, Australia, 2024
Finding the perfect MRI sequence for your patient --- Towards an optimisation workflow for MRI-sequences
Author: Christina Plump, Daniel C. Hoinkiss, Jörn Huber, Bernhard J. Berger, Matthias Günther, Christoph Lüth, Rolf Drechsler
Conference:
CEC 2024, at IEEE WCCI 2024
Pdf | Reference: Yokohama, Japan, 2024
Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification
Author: Khushboo Qayyum, Abhoy Kole, Kamalika Datta, Muhammad Hassan, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: Tempa Bay Area, Florida, USA , 2024
Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification
Author: Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2024
Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent
Author: Kemal Çağlar Coşkun, Muhammad Hassan, Lars Hedrich, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2024
Polynomial Formal Verification of Approximate Adders with Constant Cutwidth
Author: Mohamed Nadeem, Chandan Kumar Jha, Rolf Drechsler
Conference:
IEEE European Test Symposium (ETS)
Pdf | Reference: The Hague, Netherlands, 2024
A Multi-Objective Evolutionary Approach for Test Network Design.
Author: Payam Habiby, Fatemeh Shirinzadeh, Sebastian Huhn, Rolf Drechsler
Conference:
IEEE European Test Symposium (ETS)
Reference: The Hague, Netherlands, 2024
In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures
Author: Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta and Rolf Drechsler
Conference:
International Conference on VLSI Design (VLSID)
Pdf | Reference: Kolkata, India, 2024
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array
Author: Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana
Conference:
International Conference on VLSI Design (VLSID)
Pdf | Reference: Kolkata, India, 2024
A Dynamic Programming Based Graph Traversal Approach for Efficient Implementation of Nearest Neighbor Architecture in 2D
Author: Sneha Lahiri, Megha Kesh, Rupsa Mandal, Sovan Bhattacharya, Anirban Bhattacharjee, Dola Sinha, Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler, Robert Wille
Conference:
International Conference on VLSI Design (VLSID)
Reference: Kolkata, India, 2024
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory
Author: Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin Patkar, Rolf Drechsler, Farhad Merchant
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference: Incheon Songdo Convensia, South Korea, 2024
Aktuelle Entwicklungen und Perspektiven (an Hochschulen) im Bereich Data Science
Author: Lena Steinmann, Dirk Nowotka, Lea Oberländer , Helen Pfuhl, Heiner Stuckenschmidt, Rolf Drechsler
Conference:
INFORMATIK 2023
Reference: Berlin, Deutschland, 2023
Das Data Science Center an der Universität Bremen: Interdisziplinärer Knotenpunkt und Service-Infrastruktur für die datenintensive Forschung
Author: Lena Steinmann, Heike Thöricht, Sandra Zänkert, Rolf Drechsler
Conference:
E-Science-Tage 2023
Pdf | Reference: Heidelberg, Deutschland, 2023
Hidden in Plain Sight: A Detailed Investigation of Selectively Increasing Local Density to Camouflage and Robustify Against Optical Probing Attacks
Author: Sajjad Parvin, Chandan Kumar Jha, Sallar Ahmadi-Pour, Frank Sill Torres, and Rolf Drechsler
Conference:
IEEE International Test Conference India (ITC India)
Pdf | Reference: Bengaluru, India, 2023
Hybrid PTX Analysis for GPU accelerated CNN inferencing aiding Computer Architecture Design
Author: Christopher Metz, Christina Plump, Bernhard J. Berger, Rolf Drechsler
Conference:
Forum on Specification & Design Languages (FDL)
Pdf | Reference: Turin, Italy, 2023
Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models
Author: Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler
Conference:
Forum on Specification & Design Languages (FDL)
Pdf | Reference: Turin, Italy, 2023
Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification
Author: Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Conference:
Forum on Specification & Design Languages (FDL)
Pdf | Reference: Turin, Italy, 2023
LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing
Author: Sajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Iguazu Falls, Brazil, 2023
Verification of In-Memory Logic Design Using ReRAM Crossbars
Author: Kamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler
Conference:
IEEE Interregional NEWCAS Conference (NEWCAS)
Pdf | Reference: Edinburgh, Scotland, 2023
Finite State Automata Design using 1T1R ReRAM Crossbar
Author: Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad Shafik, Alex Yakovlev, Sachin Patkar, Farhad Merchant
Conference:
IEEE Interregional NEWCAS Conference (NEWCAS)
Pdf | Reference: Edinburgh, Scotland, 2023
Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures
Author: Abhoy Kole, Kamalika Datta, Philipp Niemann, Indranil Sengupta and Rolf Drechsler
Conference:
International Conference on Reversible Computation (RC)
Pdf | Reference: Giessen, Germany, 2023
Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture
Author: Kamalika Datta, Abhoy Kole, Indranil Sengupta and Rolf Drechsler
Conference:
International Conference on Reversible Computation (RC)
Pdf | Reference: Giessen, Germany, 2023
Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips
Author: Payam Habiby, Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich, Sebastian Huhn, Rolf Drechsler
Conference:
IEEE European Test Symposium (ETS)
Pdf | Reference: Venice, Italy, 2023
Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods
Author: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference:
IEEE European Test Symposium (ETS)
Pdf | Reference: Venice, Italy, 2023
A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin
Author: Daniel Tille, Leon Klimasch, Sebastian Huhn
Conference:
41st IEEE VLSI Test Symposium (VTS)
Pdf | Reference: San Diego, USA, 2023
Design Enablement Flow for Circuits with Inherent
Obfuscation based on Reconfigurable Transistors
Author: Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed E. Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, Violetta Sessi, Maximilian Drescher, Sabine Kolodinski and Maciej Wiatr
Conference:
Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2023
Divider Verification Using Symbolic Computer Algebra and Delayed Don’t Care Optimization
Author: Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler
Conference:
Formal Methods in Computer-Aided Design (FMCAD)
Pdf | Reference: Trento, Italy, 2022
Next Generation Design For Testability, Debug and
Reliability Using Formal Techniques
Author: Sebastian Huhn and Rolf Drechsler
Conference:
International Test Conference (ITC)
Pdf | Reference: Anaheim, CA, USA, 2022
Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device
Author: Alexander Fratzer, Vladimir Herdt, Christoph Lüth, Rolf Drechsler
Conference:
Forum on Specification & Design Languages (FDL)
Pdf | Reference: Linz, Austria, 2022
Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification
Author: Niklas Bruns, Vladimir Herdt, Rolf Drechsler
Conference:
Forum on Specification & Design Languages (FDL)
Pdf | Reference: Linz, Austria, 2022
Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study
Author: Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler and Klaus McDonald-Maier
Conference:
Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Gran Canaria, Spain, 2022
SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library
Author: Abhoy Kole, Kamalika Datta, Indranil Sengupta and Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Gran Canaria, Spain, 2022
Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles
Author: Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta and Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Gran Canaria, Spain, 2022
Using density of training data to improve evolutionary algorithms with approximative fitness functions
Author: Christina Plump, Bernhard J. Berger, Rolf Drechsler
Conference:
Congress of Evolutionary Computation (CEC)
Pdf | Reference: Padua, Italien, 2022
Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype
Author: Pascal Pieper, Vladimir Herdt, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Reference: Irvine, CA, USA, 2022
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
Author: Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: Irvine, CA, USA, 2022
Formal Verification of Modular Multipliers using Symbolic Computer Algebra and Boolean Satisfiability
Author: Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2022
Verifying SystemC TLM Peripherals using Modern C++ Symbolic Execution Tools
Author: Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2022
Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods
Author: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference:
IEEE European Test Symposium (ETS)
Pdf | Reference: Barcelona, Spain, 2022
Choosing the right technique for the right restriction - a domain-specific approach for enforcing search-space restrictions in evolutionary algorithms
Author: Christina Plump, Bernhard Berger, Rolf Drechsler
Conference:
LDIC-2022
Pdf | Reference: Bremen, Germany
A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection
Author: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference:
40th IEEE VLSI Test Symposium (VTS)
Pdf | Reference: San Diego, USA, 2022
The Scale4Edge RISC-V Ecosystem
Author: Wolfgang Ecker, Milos Krstic, Andreas Mauderer, Eyck Jentzsch, Mihaela Damian, Julian Oppermann, Andreas Koch, Peer Adelt, Wolfgang Müller, Vladimir Herdt, Rolf Drechsler, Rafael Stahl, Karsten Emrich, Daniel Müller-Gritschneder, Jan Schlamelcher, Kim Grüttner, Jörg Bormann, Wolfgang Kunz, Reinhold Heckmann, Gerhard Angst, Ralf Wimmer, Bernd Becker, Philipp Scholl, Paul Palomero Bernardo, Oliver Bringmann, Johannes Partzsch, Christian Mayr
Conference:
Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2022
Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
Author: Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler
Conference:
Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2022
Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and
Circuit Design Techniques
Author: Sajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres and Rolf Drechsler
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Taipei, Taiwan, 2022
Polynomial Formal Verification of Prefix Adders
Author: Alireza Mahzoon, Rolf Drechsler
Conference:
Asian Test Symposium (ATS)
Pdf | Reference: Virtual Conference, Japan, 2021
In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Conference:
Forum on Specification & Design Languages (FDL)
Pdf | Reference: Antibes, France, 2021
Finding Optimal Implementations of Non-native CNOT Gates using SAT
Author: Philipp Niemann, Luca Müller, Rolf Drechsler
Conference:
Reversible Computation (RC)
Pdf | Reference: Nagoya, Japan, 2021
Domain-driven correlation-aware recombination and mutation operators for complex real-world applications
Author: Christina Plump, Bernhard J. Berger, Rolf Drechsler
Conference:
IEEE Congress on Evolutionary Computation (CEC)
Pdf | Reference: Kraków, Poland, 2021
Improving evolutionary algorithms by enhancing an approximative fitness function through prediction intervals
Author: Christina Plump, Bernhard J. Berger, Rolf Drechsler
Conference:
IEEE Congress on Evolutionary Computation (CEC)
Pdf | Reference: Krakow, Poland, 2021
Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2021
Late Breaking Results: Polynomial Formal Verification of Fast Adders
Author: Alireza Mahzoon, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2021
Vertical IP Protection of the Next-Generation Devices: Quo Vadis?
Author: Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar
Conference:
Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Grenoble, France, 2021
Nano Security: From Nano-Electronics to Secure Systems
Author: Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz,
Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer
Conference:
Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Grenoble, France, 2021
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
Author: Vladimir Herdt, Daniel Große, Eyck Jentzsch, Rolf Drechsler
Conference:
Forum on Specification & Design Languages (FDL)
Pdf | Reference: Kiel, Germany, 2020
Best Paper Award
ToPoliNano and fiction: Design Tools for Field-coupled Nanocomputing
Author: Umberto Garlando, Marcel Walter, Robert Wille, Fabrizio Riente, Frank Sill Torres, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Portorož, Slowenien, 2020
Design Space Exploration in the Mapping of Reversible Circuits to IBM Quantum Computers
Author: Philipp Niemann, Alexandre A. A. de Almeida, Gerhard Dueck, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Portorož, Slowenien, 2020
Combining Machine Learning and Formal Techniques for Small Data Applications - A Framework to Explore New Structural Materials
Author: Rolf Drechsler, Sebastian Huhn, Christina Plump
Conference:
Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Portorož, Slowenien, 2020
Bail on Balancing: An Alternative Approach to the Physical Design of Field-coupled Nanocomputing Circuits
Author: Marcel Walter, Robert Wille, Frank Sill Torres, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Limassol, Cyprus, 2020
Best Paper Candidate
Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes
Author: Vladimir Herdt, Daniel Große, Jonas Wloka, Tim Güneysu, Rolf Drechsler
Conference:
30th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: Beijing, China, 2020
Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side
Author: Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2020
Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes
Author: Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2020
Verification for Field-coupled Nanocomputing Circuits
Author: Marcel Walter,
Robert Wille,
Frank Sill Torres,
Daniel Große,
Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2020
Efficient Implementation of Nearest Neighbor Quantum Circuits Using Clustering with Genetic Algorithm
Author: Anirban Bhattacharjee, Chandan Bandyopadhyay, Angshu Mukherjee, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
50th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Miyazaki, Japan, 2020
Towards Formal Verification of Optimized and Industrial Multipliers
Author: Alireza Mahzoon, Daniel Große, Christoph Scholl, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Grenoble, France, 2020
Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems
Author: Rolf Drechsler, Daniel Große
Conference:
Asian Test Symposium (ATS)
Pdf | Reference: Kolkata, India, 2019
A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems
Author: Sebastian Huhn, Daniel Tille, Rolf Drechsler
Conference:
International Test Conference in Asia (ITC-Asia)
Pdf | Reference: Tokyo, Japan, 2019
Functional Coverage-Driven Characterization of RF Amplifiers
Author: Muhammad Hassan, Daniel Große, Thilo Vörtler, Karsten Einwich and Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Pdf | Reference: Southampton, United Kingdom, 2019
Best Paper Candidate
Systematic RISC-V based Firmware Design
Author: Vladimir Herdt, Daniel Große, Rolf Drechsler, Christoph Gerum, Alexander Jung, Joscha-Joel Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz
Conference:
Forum on specification & Design Languages (FDL)
Pdf | Reference: Southampton, United Kingdom, 2019
Towards Formal Verification of Plans for Cognition-enabled Autonomous Robotic Agents
Author: Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
EUROMICRO Digital System Design Conference (DSD)
Pdf | Reference: Kallithea - Chalkidiki, Greece, 2019
Temporal Tracing of On-Chip Signals using Timeprints
Author: Rehab Massoud, Hoang M. Le, Peter Chini, Prakash Saivasan, Roland Meyer and Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: Las Vegas, USA, 2019
RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers
Author: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: Las Vegas, USA, 2019
Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study
Author: Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: Las Vegas, USA, 2019
ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing
Author: Steffen Frerix,
Saeideh Shirinzadeh,
Saman Fröhlich,
Rolf Drechsler
Conference: International Symposium on Nanoscale Architectures (NanoArch 2019)
Pdf | Reference: Qingdao, China, 2019
Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-coupled Nanotechnologies
Author: Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Miami, Florida, USA, 2019
Improved Look-ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits
Author: Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler and Hafizur Rahaman
Conference:
International Conference on VLSI Design (VLSI Design)
Pdf | Reference: Florida, USA, 2019
Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns
Author: Sebastian Huhn, Daniel Tille, Rolf Drechsler
Conference:
IEEE European Test Symposium (ETS)
Pdf | Reference: Baden Baden, Germany, 2019
Machine Learning-based Prediction of Test Power
Author: Harshad Dhotre, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
Conference:
IEEE European Test Symposium (ETS)
Pdf | Reference: Baden Baden, Germany, 2019
Accuracy and Compactness in Decision Diagrams for Quantum Computation
Author: Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Florence, Italy, 2019
One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing
Author: Saman Fröhlich, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Florence, Italy, 2019
Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing
Author: Hoang M. Le, Daniel Große, Niklas Bruns, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Florence, Italy, 2019
Better Late Than Never: Verification of Embedded Systems After Deployment
Author: Martin Ring, Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Florence, Italy, 2019
Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements
Author: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Conference:
20th IEEE Latin American Test Symposium (LATS)
Pdf | Reference: Santiago, Chile, 2019
Multi-Objective Synthesis of Quantum Circuits Using Genetic Programming
Author: Moein Sarvaghad-Moghaddam, Philipp Niemann, Rolf Drechsler
Conference:
Reversible Computation
Pdf | Reference: pp. 220-227, Leicester, UK, 2018
Design criteria of a thermal mass flow sensor for aircraft air data applications
Author: Lucas C. Ribeiro, Rubens A. Souza, Michael Lopes Oliveira, S.P.L. Vieira, W.O. Avelino, Clarice F.R. Oliveira, Davies Wiliiam de Lima Monteiro, Frank Sill Torres, Roana M.O. Hansen
Conference:
31st Congress of the International Council of the Aeronautical Sciences (ICAS 2018)
Pdf | Reference: Belo Horizonte, Brazil, 2018
Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata
Author: Frank Sill Torres, Pedro A. Silva, Geraldo Fontes, José Augusto M. Nacif, Ricardo Santos Ferreira,
Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Prague, Czech Republic, 2018
Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata
Author: Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Große, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: pp. 649-656, Prague, Czech Republic, 2018
On overcoming photodetector saturation due to background illumination while maintaining high sensitivity by means of a tailored CMOS pixel
Author: Pablo Nunes Agra Belmonte, Lucas Chaves, Frank Sill Torres, Davies William de Lima Monteiro
Conference:
Global LiFi Congress
Pdf | Reference: Paris, France, 2018
Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers
Author: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: pp. 351-356, Hong Kong SAR, China, 2018
Towards Dynamic Execution Environment for System Security Protection against Hardware Flaws
Author: Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: pp. 557-562, Hong Kong SAR, China, 2018
SAT-Lancer: A Hardware SAT-Solver for Self-Verification
Author: Buse Ustaoglu, Sebastian Huhn, Daniel Große, Rolf Drechsler
Conference:
28th ACM Great Lakes Symposium on VLSI (GLVLSI)
Pdf | Reference: pp. 479-482, Chicago, Illinois, USA, 2018
Received Best Poster Award
Confident Leakage Assessment - A Side-Channel
Evaluation Framework based on Confidence Intervals
Author: Florian Bache, Christina Plump, Tim Güneysu
Conference:
Design, Automation and Test in Europe (DATE)
Reference: Dresden, Germany, 2018
Resiliency Evaluation via Symbolic Fault Injection on Intermediate Code
Author: Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 845-850, Dresden, Germany, 2018
Testbench Qualification for SystemC-AMS Timed
Data Flow Models
Author: Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 857-860, Dresden, Germany, 2018
Approximate Hardware Generation using Symbolic Computer Algebra employing Gröbner Basis
Author: Saman Fröhlich, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 889-892, Dresden, Germany, 2018
An Exact Method for Design Exploration of Quantum-dot Cellular Automata
Author: Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 503-508, Dresden, Germany, 2018
Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips
Author: Oliver Keszöcze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Conference:
International Conference on VLSI Design (VLSID)
Pdf | Reference: Pune, Indien, 2018
Identification of Efficient Clustering Techniques for Test Power Activity on the Layout
Author: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Conference:
26th IEEE Asian Test Symposium (ATS)
Pdf | Reference: Taipei, Taiwan, 2017
Towards Early Validation of Firmware-Based Power
Management using Virtual Prototypes:
A Constrained Random Approach
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Pdf | Reference: pp. 1-8, Verona, Italy, 2017
Best Paper Candidate
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects
Author: Tino Flenker, Jan Malburg, Goerschwin Fey, Serhiy Avramenko, Massimo Violante and Matteo Sonza Reorda
Conference:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Bochum, Germany, 2017
Towards VHDL-based Design of Reversible Circuits
Author: Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Pdf | Reference: Kolkata, India, 2017
Efficient Construction of QMDDs for Irreversible, Reversible and Quantum Functions
Author: Philipp Niemann, Alwin Zulehner, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Pdf | Reference: pp. 214-231, Kolkata, India, 2017
Hiding Higher-Order Side-Channel Leakage - Randomizing Cryptographic Implementations in Reconfigurable Hardware
Author: Pascal Sasdrich, Amir Moradi, Tim Güneysu
Conference:
RSA Conference Cryptographers’ Track (CT-RSA)
Pdf | Reference: San Francisco, US, 2017.
Effects of Cell Shapes on the Routability of Digital Microfluidic Biochips
Author: Kevin Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Lausanne, Switzerland, 2017
Automatic Equivalence Checking for SystemC-TLM 2.0 Models
Against their Formal Specifications
Author: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Lausanne, Switzerland, 2017
Data Flow Testing for Virtual Prototypes
Author: Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Lausanne, Switzerland, 2017
Endurance Management for Resistive Logic-In-Memory Computing Architectures
Author: Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Lausanne, Switzerland, 2017
Optimization of Retargeting for IEEE 1149.1 TAP Controllers with Embedded Compression
Author: Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Lausanne, Schweiz, 2017
White-Box Cryptography in the Gray Box - A Hardware Implementation and its Side Channels
Author: Pascal Sasdrich, Amir Moradi, Tim Güneysu
Conference: FSE 2016: 185-203
Reference: http://dx.doi.org/10.1007/978-3-662-52993-5_10
Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test
Author: Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen
Conference:
IEEE Asian Test Symposium (ATS)
Pdf | Reference: Hiroshima, Japan, 2016
Automated Optimization of Scan Chain Structure for Test Compression-Based Designs
Author: Harshad Dhotre, Mehdi Dehbashi, Ulrike Pfannkuchen, Klaus Hofmann
Conference:
IEEE Asian Test Symposium (ATS)
Reference: Hiroshima, Japan, 2016
On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-based Error Effect Simulation - A Case Study
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Pdf | Reference: Bremen, Germany, 2016
Best Paper Candidate
Designing Reliable Cyber-Physical Systems
Author: Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon Ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Conference:
Forum on specification & Design Languages (FDL)
Pdf | Reference: Bremen, Germany, 2016
Strong 8-bit Sboxes with Efficient Masking in Hardware
Author: Erik Boss, Vincent Grosso, Tim Güneysu, Gregor Leander, Amir Moradi, Tobias Schneider
Conference: CHES 2016: 171-193
Reference: http://dx.doi.org/10.1007/978-3-662-53140-2_9
ParTI - Towards Combined Hardware Countermeasures Against Side-Channel and Fault-Injection Attacks
Author: Tobias Schneider, Amir Moradi, Tim Güneysu
Conference: CRYPTO (2), Santa Barbara, USA, 2016: 302-332
Reference: http://dx.doi.org/10.1007/978-3-662-53008-5_11
On the problems of realizing reliable and efficient ring oscillator PUFs on FPGAs.
Author: Alexander Wild, Georg T. Becker, Tim Güneysu
Conference: Hardware-Oriented Security and Trust (HOST) 2016: 103-108
Reference: http://dx.doi.org/10.1109/HST.2016.7495565
Secure and Private, yet Lightweight, Authentication for the IoT via PUF and CBKA
Author: Christopher Huth, Aydin Aysu, Jorge Guajardo, Paul Duplys, Tim Güneysu
Conference: ICISC 2016: 28-48
Reference: http://dx.doi.org/10.1007/978-3-319-53177-9_2
Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs
Author: Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Conference:
Reversible Computation
Reference: Bologna, Italy, 2016
Enumeration of reversible functions and its application to circuit complexity
Author: Mathias Soeken, Nabila Abdessaied, Giovanni De Micheli
Conference:
Reversible Computation
Pdf | Reference: Bologna, Italy, 2016
High-Performance and Lightweight Lattice-Based Public-Key Encryption
Author: Johannes A. Buchmann, Florian Göpfert, Tim Güneysu, Tobias Oder, Thomas Pöppelmann
Conference: IoTPTS@AsiaCCS 2016: 2-9
Reference: http://doi.acm.org/10.1145/2899007.2899011
IND-CCA Secure Hybrid Encryption from QC-MDPC Niederreiter
Author: Ingo von Maurich, Lukas Heberle, Tim Güneysu
Conference:
Post-Quantum Cryptography (PQCrypto 2016)
Reference: pages 1-17, LNCS Vol. 9606, Fukuoka, Japan
Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables
Author: Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Goerschwin Fey
Conference:
IEEE Latin-American Test Symposium (LATS2016)
Pdf | Reference: Foz do Iguaçu, Brazil, 2016
Robust and One-Pass Parallel Computation of Correlation-Based Attacks at Arbitrary Order
Author: Tobias Schneider, Amir Moradi, Tim Güneysu
Conference: COSADE 2016, Graz, p. 199-217
Reference: http://dx.doi.org/10.1007/978-3-319-43283-0_12
Standard lattices in hardware
Author: James Howe, Ciara Moore, Máire O'Neill, Francesco Regazzoni, Tim Güneysu, K. Beeden
Conference: Design Automation Conference (DAC), Austin, USA, 2016, 162:1-162:6
Reference: http://doi.acm.org/10.1145/2903150.2907756
An MIG-based Compiler for Programmable Logic-in-Memory Architectures
Author: Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli
Conference:
Design Automation Conference (DAC)
Pdf | Reference: Austin, USA, 2016
Precise Error Determination of Approximated Components in Sequential Circuits with Model Checking
Author: Arun Chandrasekharan,
Mathias Soeken,
Daniel Große,
Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: Austin, USA, 2016
A grain in the silicon: SCA-protected AES in less than 30 slices
Author: Pascal Sasdrich, Tim Güneysu
Conference: IEEE International Conference on
Application-specific Systems, Architectures and Processors (ASAP) 2016: 25-32
Reference: http://dx.doi.org/10.1109/ASAP.2016.7760769
On the Energy Cost of Channel Based Key Agreement
Author: Christopher Huth, René Guillaume, Paul Duplys, Kumaragurubaran Velmurugan, Tim Güneysu
Conference: TrustED@CCS 2016: 31-41
Reference: http://doi.acm.org/10.1145/2995289.2995291
Secure architectures of future emerging cryptography SAFEcrypto
Author: Máire O'Neill, Elizabeth O'Sullivan, Gavin McWilliams, Markku-Juhani Saarinen, Ciara Moore, Ayesha Khalid, James Howe, Rafaël Del Pino, Michel Abdalla, Francesco Regazzoni, Felipe Valencia, Tim Güneysu, Tobias Oder, Adrian Waller, Glyn Jones, Anthony Barnett, Robert Griffin, Andrew Byrne, Bassem Ammar, David Lund
Conference: Conf. Computing Frontiers 2016: 315-322
Reference: http://doi.acm.org/10.1145/2903150.2907756
VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers
Author: Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler
Conference:
IEEE European Test Symposium (ETS)
Pdf | Reference: Amsterdam, Niederlande, 2016
SAT-Based Post-Processing for Regional Capture Power Reduction in At-Speed Scan Test Generation
Author: Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen
Conference:
IEEE European Test Symposium (ETS)
Pdf | Reference: Amsterdam, Niederlande, 2016
A Hybrid Algorithm to Conservatively Check the Robustness of Circuits
Author: Niels Thole, Lorena Anghel, Görschwin Fey
Conference:
IEEE European Test Symposium (ETS)
Pdf | Reference: Amsterdam, Niederlande, 2016
Towards a Catalog of Structural and Behavioral
Verification Tasks for UML/OCL Models
Author: Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Conference:
Modellierung
Pdf | Reference: pp. 117-124, Karlsruhe, Germany, 2016
Quantitative Timing Analysis of UML Activity Diagrams Using Statistical Model Checking
Author: Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große,
Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 780-785, Dresden, Germany, 2016
Towards Formal Verification of Real-World SystemC TLM Peripheral Models - A Case Study
Author: Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1160-1163, Dresden, Germany, 2016
Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction
Author: Amr Sayed Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1048-1053, Dresden, Germany, 2016
Best Paper Candidate
Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs
Author: Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Dresden, Germany, 2016
Optimizing Majority-Inverter Graphs With Functional Hashing
Author: Mathias Soeken, Pierre-Emmanuel Gaillardon, Luca Amaru, Giovanni De Micheli
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Dresden, Germany, 2016
Synthesis of Approximate Coders
for On-chip Interconnects Using Reversible Logic
Author: Robert Wille, Oliver Keszöcze, Stefan Hillmich, Marcel Walter, Alberto Garcia-Ortiz
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Dresden, Germany, 2016
Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking
Author: Luca Amaru, Pierre-Emmanuel Gaillardon, Robert Wille, Giovanni De Micheli
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Dresden, 2016
Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library
Author: Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference:
International Conference on VLSI Design (VLSI Design)
Reference: Kolkata, India, 2016
Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation
Author: Tino Flenker, André Sülflow, Görschwin Fey
Conference:
24th IEEE Asian Test Symposium (ATS)
Pdf | Reference: Mumbai, India, 2015
Ricercar: A Language for Describing and Rewriting Reversible Circuits with Ancillae and its Permutation Semantics
Author: Michael Kirkedal Thomsen, Mathias Soeken, Robin Kaarsgaard
Conference:
Reversible Computation
Pdf | Reference: Grenoble, France, 2015
Towards Line-aware Realizations of Expressions for HDL-based Synthesis of Reversible Circuits
Author: Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Pdf | Reference: Grenoble, France, 2015
Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions
Author: Philipp Niemann, Saikat Basu, Amlan Chakrabarti, Niraj K. Jha, Robert Wille
Conference:
Reversible Computation
Pdf | Reference: pp. 248-264, Grenoble, France, 2015
Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits
Author: Abhoy Kole, Kamalika Datta, Indranil Sengupta, Robert Wille
Conference:
Reversible Computation
Pdf | Reference: Grenoble, France, 2015
Technology mapping for quantum circuits using Boolean functional decomposition
Author: Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Pdf | Reference: Grenoble, France, 2015
A Generic Representation of CCSL Time Constraints for UML/MARTE Models
Author: Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: San Francisco, 2015
Verifying SystemC using Stateful Symbolic Simulation
Author: Vladimir Herdt, Hoang M. Le, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: San Francisco, 2015
BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits
Author: Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference:
International Conference on VLSI Design (VLSI Design)
Pdf | Reference: Bengaluru, India, 2015
Automating the Translation of Assertions Using Natural Language Processing Techniques
Author: Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris and Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Pdf | Reference: Munich, Germany, 2014
Verifying Consistency between Activity Diagrams and Their Corresponding OCL Contracts
Author: Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Pdf | Reference: Munich, Germany, 2014
Filmstripping and Unrolling: A Comparison of Verification Approaches for UML and OCL Behavioral Models
Author: Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Conference:
8th International Conference on Tests & Proofs (TAP)
Pdf | Reference: pp. 99-116, York, 2014
Exact One-pass Synthesis of Digital Microfluidic Biochips
Author: Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: San Francisco, 2014
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State-of-the-Art and Research Challenges
Author: Jan-Hendrik Oetjens,
Nico Bannow,
Markus Becker,
Oliver Bringmann,
Andreas Burger,
Moomen Chaari,
Samarjit Chakraborty,
Rolf Drechsler,
Wolfgang Ecker,
Kim Gruettner,
Thomas Kruse,
Christoph Kuznik,
Hoang M. Le,
Andreas Mauderer,
Wolfgang Mueller,
Daniel Mueller-Gritschneder,
Frank Poppen,
Hendrik Post,
Sebastian Reiter,
Wolfgang Rosenstiel,
Simon Roth,
Ulf Schlichtmann,
Andreas von Schwerin,
Bogdan-Andrei Tabacaru,
Alexander Viehl
Conference:
Design Automation Conference (DAC)
Reference: pp. 113:1-6, San Francisco, 2014
Mapping NCV Circuits to Optimized Clifford+T Circuits
Author: D. Michael Miller, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Pdf | Reference: Kyoto, Japan, 2014
Equivalence Checking in Multi-level Quantum Systems
Author: Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Pdf | Reference: pp. 201-215, Kyoto, Japan, 2014
RevVis: Visualization of Structures and Properties in Reversible Circuits
Author: Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler
Conference:
Reversible Computation
Pdf | Reference: Kyoto, Japan, 2014
Quantum Circuit Optimization by Hadamard Gate Reduction
Author: Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Pdf | Reference: Kyoto, Japan, 2014
Verification of the Decimal Floating-Point Square Root Operation,
Author: Amr Sayed Ahmed, Hossam Fahmy, Ulrich Kühne
Conference:
19th IEEE European Test Symposium,
Pdf | Reference: Paderborn, Germany, 2014.
Optimization-based Multiple Target Test Generation for Highly Compacted Test Sets
Author: Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Conference:
19th IEEE European Test Symposium (ETS)
Pdf | Reference: Paderborn, Germany, 2014
Future SoC Verification Methodology: UVM
Evolution or Revolution?
Author: Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev
Conference:
Design, Automation and Test in Europe (DATE'14)
Pdf | Reference: Dresden, Germany, 2014
Constraint-based Platform Variants Specification for Early System Verification
Author: Andreas Burger, Alexander Viehl, Andreas Braun, Finn Haedicke, Daniel Große, Oliver Bringmann, Wolgang Rosenstiel
Conference:
Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: pp. 800-805, Singapore, 2014
Task-Driven Software Summarization
Author: Dave Binkley,
Dawn Lawrie,
Emily Hill,
Janet Burge,
Ian Harris,
Regina Hebig,
Oliver Keszöcze,
Karl Reed,
John Slankas
Conference:
29th IEEE International Conference on Software Maintenance (ICSM)
Reference: Eindhoven, The Netherlands, 2013
Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill
Author: Stephan Eggersglüß
Conference:
22nd IEEE Asian Test Symposium (ATS)
Pdf | Reference: pp. 31-16, Yilan, Taiwan, 2013
A Compact and Efficient SAT Encoding for Quantum Circuits
Author: Robert Wille, Nils Przigoda, Rolf Drechsler
Conference:
IEEE Africon
Pdf | Reference: Mauritius, 2013
Exploiting Reversibility in the Complete Simulation of Reversible Circuits
Author: Robert Wille, Simon Stelter, Rolf Drechsler
Conference:
IEEE Africon
Pdf | Reference: Mauritius, 2013
On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure
Author: Philipp Niemann, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Pdf | Reference: pp. 125-140, Victoria, Canada, 2013
Exploiting Negative Control Lines in the Optimization of Reversible Circuits
Author: Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference:
Reversible Computation
Pdf | Reference: pp. 209-220, Victoria, Canada, 2013
Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure
Author: Arighna Deb, Debesh Kumar Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler
Conference:
Reversible Computation
Pdf | Reference: pp. 182-195, Victoria, Canada, 2013
White Dots do Matter: Rewriting Reversible Logic Circuits
Author: Mathias Soeken, Michael Kirkedal Thomsen
Conference:
Reversible Computation
Pdf | Reference: pp. 196-208, Victoria, Canada, 2013
Reducing the Depth of Quantum Circuits Using Additional Lines
Author: Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Reversible Computation
Pdf | Reference: pp. 221-233, Victoria, Canada, 2013
Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation
Author: Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: pp. 116:1-6 Austin, Texas, 2013
Synchronized Debugging across Different Abstraction Levels in System Design
Author: Rolf Drechsler, Daniel Große, Hoang M. Le, André Sülflow
Conference:
embedded world Conference 2013
Pdf | Reference: Nürnberg, 2013
Reliability Analysis Reloaded: How Will We Survive?
Author: Robert Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda
Conference:
Design, Automation and Test in Europe (DATE'13)
Pdf | Reference: Grenoble, France, 2013
Determining Relevant Model Elements for the Verification of UML/OCL Specifications
Author: Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1189-1192, Grenoble, France, 2013
Towards a Generic Verification Methodology for System Models
Author: Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1193-1196, Grenoble, France, 2013
An Evolutionary Approach to Reversible Logic Synthesis using Output Permutation
Author: Kamalika Datta, Indranil Sen Gupta, Hafizur Rahaman, Rolf Drechsler
Conference:
IEEE Design and Test Symposium 2012 (IDT)
Pdf | Reference: Doha, 2012
Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems
Author: Rolf Drechsler, Mathias Soeken, Robert Wille
Conference:
IEEE Design and Test Symposium 2012 (IDT)
Pdf | Reference: Doha, 2012
SyDe - a New Graduate School for
System Design in an Excellent Setting
Author: Ulrich Kühne, Rolf Drechsler
Conference:
Informatics Europe (ECSS)
Reference: Barcelona, 2012
FoREnSiC - An Automatic Debugging Environment for C Programs
Author: Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
Conference:
Haifa Verification Conference (HVC)
Pdf | Reference: Haifa, 2012
Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization
Author: Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty
Conference:
21st IEEE Asian Test Symposium (ATS)
Pdf | Reference: pp. 290-295, Niigata, Japan, 2012
The System Verification Methodology for
Advanced TLM Verification
Author: Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, Volkan Esen
Conference:
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
Pdf | Reference: pp. 313-322, Tampere, 2012
Completeness-Driven Development
Author: Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille
Conference:
International Conference on Graph Transformation
Pdf | Reference: pp. 38-50, Bremen, 2012
Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing
Author: Rolf Drechsler, Mathias Soeken, Robert Wille
Conference:
Forum on specification & Design Languages (FDL)
Pdf | Reference: pp. 53-58, Vienna, Austria, 2012
IMITATOR 2.5: A Tool for Analyzing Robustness in Scheduling Problems (Tool Paper)
Author: Étienne André, Laurent Fribourg, Ulrich Kühne, Romain Soulat
Conference:
International Symposium on Formal Methods (FM)
Reference: Paris, France, 2012
Automated Feature Localization for Hardware Designs
using Coverage Metrics
Author: Jan Malburg, Alexander Finder, Görschwin Fey
Conference:
Design Automation Conference (DAC)
Pdf | Reference: pp. 941-946, San Francisco, 2012
Realizing Reversible Circuits Using a New Class of Quantum Gates
Author: Zahra Sasanian, Robert Wille, Michael Miller
Conference:
Design Automation Conference (DAC)
Pdf | Reference: San Francisco, 2012
Functional Analysis of Circuits Under Timing
Variations
Author: Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Conference:
17th IEEE European Test Symposium (ETS)
Pdf | Reference: pp. 177, Annecy, France, 2012
Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis
Author: Robert Wille, Rolf Drechsler, Christof Oswald, Alberto Garcia-Ortiz
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: Dresden, 2012
Improved Fault Diagnosis for Reversible Circuits
Author: Hongyan Zhang, Robert Wille, Rolf Drechsler
Conference:
Asian Test Symposium (ATS)
Pdf | Reference: New Delhi, 2011
Determining Minimal Testsets for Reversible Circuits Using Boolean Satisfiability
Author: Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
10th IEEE Africon
Pdf | Reference: Livingstone, 2011
Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction
Author: Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: pp. 223-228, Lausanne, 2011
As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
Author: Stephan Eggersglüß, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1291-1296, Grenoble, 2011
Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability
Author: Stephan Eggersglüß, Rolf Drechsler
Conference:
International Test Conference (ITC)
Pdf | Reference: pp. 1-10, Austin, 2010
SyReC: A Programming Language for Synthesis of Reversible Circuits
Author: Robert Wille, Sebastian Offermann, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Pdf | Reference: pp. 184-189, Southampton, 2010
Received Best Paper Award
Reducing the Number of Lines in Reversible Circuits
Author: Robert Wille, Mathias Soeken, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: pp. 647-652, Anaheim, 2010
Enhancing Debugging of Multiple Missing Control Errors in Reversible Logic
Author: Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: pp. 465-470, Rhode Island, 2010
Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs
Author: Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler
Conference:
15th IEEE European Test Symposium (ETS)
Pdf | Reference: pp. 176-181, Prag, 2010
Verifying UML/OCL Models Using Boolean Satisfiability
Author: Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1341-1344, Dresden, 2010, 2010
Speeding up SAT-based ATPG using Dynamic Clause Activation
Author: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Conference:
18th Asian Test Symposium (ATS'09)
Pdf | Reference: pp. 177-182, Taichung, 2009
SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults
Author: Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada
Conference: European Conference on Circuit Theory and Design
Reference: Antalya, 2009
BDD-based Synthesis of Reversible Logic for Large Functions
Author: Robert Wille, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: pp. 270-275, San Francisco, 2009
Computing Bounds for Fault Tolerance using Formal Techniques
Author: Görschwin Fey, Andre Sülflow, Rolf Drechsler
Conference:
Design Automation Conference (DAC)
Pdf | Reference: pp. 190-195, San Francisco, USA, 2009
Increasing Robustness of SAT-based Delay Test Generation using Efficient Dynamic Learning Techniques
Author: Stephan Eggersglüß, Rolf Drechsler
Conference:
14th IEEE European Test Symposium (ETS)
Pdf | Reference: pp. 81-86, Sevilla, 2009
Contradictory Antecedent Debugging in Bounded Model Checking
Author: Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: pp. 173-176, Boston, 2009
Targeting Leakage Constraints during ATPG
Author: Görschwin Fey, Sathoshi Komatsu, Yasuo Furukawa, Masahiro Fujita
Conference:
Asian Test Symposium (ATS)
Pdf | Reference: pp. 225-230, 2008
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking
Author: Robert Wille, Görschwin Fey, Marc Messing, Gerhard
Angst, Lothar Linhard, Rolf Drechsler
Conference:
Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: pp. 542-549, Parma, 2008
Improving Test Pattern Compactness in SAT-based ATPG
Author: Stephan Eggersglüß, Rolf Drechsler
Conference:
16th Asian Test Symposium (ATS’07)
Pdf | Reference: pp. 445-450, Beijing, 2007
Measuring the Quality of a SystemC Testbench by using Code Coverage Technqiues
Author: Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
Conference:
Forum on specification & Design Languages (FDL)
Pdf | Reference: pp. 146-151, Barcelona
Received Best Paper Award, 2007
Improvements for Constraint Solving in the SystemC Verification Library
Author: Daniel Große, Rüdiger Ebendt, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: pp. 493-496, Stresa, 2007
Ein formaler Ansatz zum Robustheitsnachweis
Author: Görschwin Fey, Rolf Drechsler
Conference:
Zuverlässigkeit und Entwurf
Pdf | Reference: München, 2007
Automatic Fault Localization for Property Checking
Author: Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Conference:
Haifa Verification Conference
Pdf | Reference: Haifa, 2006
HW/SW Co-Verification of Embedded Systems using Bounded Model Checking
Author: Daniel Große, Ulrich Kühne, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: pp. 43-48, Philadelphia, 2006
On the Relation Between Simulation-based and SAT-based Diagnosis
Author: Görschwin Fey, Sean Safarpour, Andreas Veneris, Rolf Drechsler
Conference:
Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1139-1144, Munich, 2006
Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits
Author: Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
Conference:
International Conference on ASIC (ASICON 2005)
Pdf | Reference: pp. 967-970, Shanghai, 2005
PASSAT: Efficient SAT-based Test Pattern Generation
Author: Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Conference:
IEEE Annual Symposium on VLSI (ISVLSI '05)
Reference: pp.212-217, Tampa, Florida, 2005
Utilizing Don't Care States in SAT-based Bounded Sequential Problems
Author: Sean Safarpour, Görschwin Fey, Andreas Veneris, Rolf Drechsler
Conference:
Great Lakes Symposium on VLSI (GLSVLSI'05)
Pdf | Reference: Chicago, 2005
Cost-Efficient Block Verification for a UMTS Up-Link
Chip-Rate Coprocessor
Author: Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey
Conference:
IEEE Design, Automation and Test in Europe
Pdf | Reference: Vol. I, pp. 162-167, Paris, 2004
BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
Author: Junhao Shi, Görschwin Fey, Rolf Drechsler
Conference:
Twelfth Asian Test Symposium (ATS03)
Reference: pp. 290-293,
Xi'an, 2003
MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits
Author: Rolf Drechsler, Junhao Shi and Görschwin Fey
Conference:
IEEE Great Lakes Symposium on VLSI (GLSV'03)
Pdf | Reference: p. 80-83, Washington, 2003
Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques
Author: Görschwin Fey, Sebastian Kinder and Rolf Drechsler
Conference: IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Reference: pp. 361-366, Tokyo, 2003
Formal Verification of LTL Formulas for SystemC Designs
Author: Daniel Große, Rolf Drechsler
Conference: IEEE International Symposium on Circuits and Systems (ISCAS'03)
Pdf | Reference: pp. V:245-V:248, Bangkok, 2003
Reducing the Number of Variable Movements in Exact BDD Minimization
Author: Rüdiger Ebendt
Conference: IEEE International Symposium on Circuits and Systems (ISCAS'03)
Pdf | Reference: pp. V:605-V:608, Bangkok, 2003
Synthesizing Checkers for On-line Verification of System-on-Chip Designs
Author: Rolf Drechsler
Conference: IEEE International Symposium on Circuits and Systems (ISCAS'03)
Pdf | Reference: pp. IV:748-IV:751, Bangkok, 2003
SPIHT implemented in a XC4000 device
Author: Jörg Ritter, Görschwin Fey and Paul Molitor
Conference: IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002)
Pdf | Reference: volume I, pp. 239-242, Tulsa, 2002
Utilizing BDDs for disjoint SOP minimization
Author: Görschwin Fey and Rolf Drechsler
Conference: IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002)
Reference: volume II, pp. 306-309, Tulsa, 2002
Crossing Reduction by Windows Optimization
Author: Thomas Eschbach, Wolfgang Günther, Rolf Drechsler and Bernd Becker
Conference: 10th International Symposium on Graph Drawing (GD'2002)
Pdf | Reference: LNCS 2528, pp. 285-294, Irvine, 2002
Computing Walsh, Arithmetic and Reed-Muller Spectral Decision Diagrams Using Graph Transformations
Author: Whitney Townsend, Mitch Thornton, Rolf Drechsler and Michael Miller
Conference: IEEE Great Lakes Symposium on VLSI (GLSV'02)
Pdf | Reference: pp. 178-183, New York, 2002
