Logo Universtity of Bremen
LOGO AGRA | AG Rechnerarchitektur

Group of Computer Architecture / AGRA | Computer Science | Faculty 03 | University of Bremen

PhD Thesis

Supporting doctoral candidates is of great importance for the working group.

The following list gives a chronological overview of the graduates as well as their titles of the respective PhD thesis, which were developed in close cooperation with research and/or industry partners.

Portrait: Pascal Pieper
Dr. Pascal Pieper
Formal and Practical Techniques for the Complex System Design Process using Virtual Prototypes

Portrait: Niklas Bruns
Dr. Niklas Bruns
Virtual Prototype Centric Verification for Embedded System Development

Portrait: Tim Meywerk
Dr. Tim Meywerk
Modelling, Verification and Test of High-level Robotic Plans

Portrait: Alireza Mahzoon
Dr. Alireza Mahzoon
Formal Verification of Structurally Complex Multipliers

Portrait: Buse Ustaoglu
Dr. Buse Ustaoglu
Hardware Packages for Self-Verification and Secure Partial Reconfiguration

Portrait: Saman Fröhlich
Dr. Saman Fröhlich
A Fully Fledged HDL Design Flow for In-Memory Computing with Approximation Support

Portrait: Rehab Massoud
Dr. Rehab Massoud
Evidence-Oriented Tracing and Verification The Declaration of Timeprints

Portrait: David Lemma
Dr. David Lemma
Specification Analysis for System-Level Power-Aware ASIC Design

Portrait: Muhammad Hassan
Dr. Muhammad Hassan
Enhanced Modern Virtual Prototype based Verification Flow for Heterogeneous Systems

Portrait: Fritjof Bornebusch
Dr. Fritjof Bornebusch
COQ meets CλaSH - Proposing a Hardware Design Synthesis Flow that Combines Proof Assistants with Functional Hardware Description Languages

Portrait: Marcel Walter
Dr. Marcel Walter
Design Automation for Field-Coupled Nanotechnologies

Portrait: Mazyar Seraj
Dr. Mazyar Seraj
Impacts of Block-based Programming on Young Learners’ Programming Skills and Attitude in the Context of Smart Environments

Portrait: Sebastian Huhn
Dr. Sebastian Huhn
Next Generation Design For Testability, Debug and Reliability Using Formal Techniques

also presented in PhD-Forum: ASP-DAC 2021 und DATE 2021

Portrait: Vladimir Herdt
Dr. Vladimir Herdt
Efficient Modeling, Verification and Analysis Techniques to Enhance the Virtual Prototype based Design Flow for Embedded Systems

Portrait: Harshad Dhotre
Dr. Harshad Dhotre
Pattern Analysis for Power Safe Testing and Prediction Using Machine Learning

Portrait: Mehran Goli
Dr. Mehran Goli
Automated Analysis of Virtual Prototypes at the Electronic System Level -Design Understanding and Applications-

Portrait: Kenneth Schmitz
Dr. Kenneth Schmitz
Trust is good, Control is better: A Container based System Design Scheme

Portrait: Arighna Deb
Dr. Arighna Deb
Logic Synthesis Techniques for Optical Circuits

Portrait: Saeideh Shirinzadeh
Dr. Saeideh Shirinzadeh
Synthesis and Optimization for Logic-in-Memory Computing using Memristive Devices

Portrait: Zaid Saleem Ali Al-Wardi
Dr. Zaid Saleem Ali Al-Wardi
HDL-based Synthesis of Reversible Circuits|A Scalable Design Approach

Portrait: Arun Chandrasekharan
Dr. Arun Chandrasekharan
Design Automation Techniques for Approximation Circuits - Synthesis, Verification and Test -

Portrait: Oliver Keszöcze
Dr. Oliver Keszöcze
Exact Design of Digital Microfluidic Biochips

Portrait: Nils Przigoda
Dr. Nils Przigoda
SMT-based Validation & Verification of UML/OCL Models

Portrait: Amr Sayed-Ahmed
Dr. Amr Sayed-Ahmed
Highly Automated Formal Verification of Arithmetic Circuits

Portrait: Jannis Stoppe
Dr. Jannis Stoppe
Non-Intrusive Analysis of Electronic System Level Designs in SystemC

Portrait: Niels Thole
Dr. Niels Thole
Formal Verification throughout the Development of Robust Systems

Portrait: Ngouo´goum Tague Laura Sandrine
Dr. Ngouo´goum Tague Laura Sandrine
Using Decision Diagrams in the Design of Reversible Circuit

Portrait: Philipp Niemann
Dr. Philipp Niemann
Towards Computer-Aided Design of Quantum Logic: Compact Representations and Efficient Synthesis Methods for an Emerging Technology

Portrait: Eleonora Schönborn
Dr. Eleonora Schönborn
Scalable Design and Synthesis of Reversible Circuits

Portrait: Finn Haedicke
Dr. Finn Haedicke
High-Quality Hardware Design and Verification using Word-Level Satisfiability Techniques

Portrait: Judith Peters
Dr. Judith Peters
Exploiting MARTE/CCSL in Modern Design Flows

Portrait: Nabila Abdessaied
Dr. Nabila Abdessaied
Reversible and Quantum Circuits | Optimization and Complexity Analysis

Portrait: Jan Malburg
Dr. Jan Malburg
Feature Localization and Design Understanding for Hardware Designs

Portrait: Melanie Diepenbeck
Dr. Melanie Diepenbeck
Completing Behaviour Driven Development for Testing and Verification

Portrait: Julia Seiter
Dr. Julia Seiter
Formal Model Refinement

Portrait: Hoang M. Le
Dr. Hoang M. Le
Automated Techniques for Functional Verification at the Electronic System Level

ausgezeichnet mit dem Sonderpreis des Rotary Clubs Bremen im Rahmen des Bremer Studienpreises 2016
also presented in PhD-Forum: DATE 2013 (Best Poster Award)

Portrait: Shuo Yang
Dr. Shuo Yang
Improving Coverage in Simulation-based Verification

Portrait: Marc Michael
Dr. Marc Michael
Methoden zum Erfassen und Entwickeln von SystemC Modellen

Portrait: Elsa Andrea Kirchner
Dr. Elsa Andrea Kirchner
Embedded Brain Reading

Portrait: Mathias Soeken
Dr. Mathias Soeken
Formal Specification Level Concepts, Methods, and Algorithms

Portrait: Mehdi Dehbashi
Dr. Mehdi Dehbashi
Debug Automation from Pre-Silicon to Post-Silicon

Portrait: Stefan Frehse
Dr. Stefan Frehse
Quality and Quantity in Robustness Checking Using Formal Techniques

Portrait: Hongyan Zhang
Dr. Hongyan Zhang
Testing of Reversible Circuits

Portrait: Beate Kapturek
Dr. Beate Kapturek
Vorgehensmodelle für die Technische Dokumentation Eingebetteter Systeme

Portrait: Daniel Tille
Dr. Daniel Tille
Advanced Utilization of Formal Methods in Automatic Test Pattern Generation for Industrial Designs

also presented in Student-Forum: ETS 2009

Portrait: Stephan Eggersglüß
Dr. Stephan Eggersglüß
Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability

auszeichnet mit
dem EDAA Outstanding Dissertation Award 2011
dem IEEE TTTC's E.J. McCluskey 2010 Best Doctoral Thesis Award
dem Sonderpreis der Bruker Daltonik GmbH im Rahmen des Bremer Studienpreises 2011

also presented in PhD-Forum: DATE 2009

Portrait: André Sülflow
Dr. André Sülflow
WoLFram – A Word Level Framework for Formal Verification and its Application

also presented in PhD-Forum: DATE 2011

Portrait: Robert Wille
Dr. Robert Wille
Towards a Design Flow for Reversible Logic

ausgezeichnet mit dem Sonderpreis des Rotary Clubs Bremen im Rahmen des Bremer Studienpreises 2010
also presented in PhD-Forum: DAC 2009

Portrait: Ulrich Kühne
Dr. Ulrich Kühne
Advanced Automation in Formal Verification of Processors

also presented in PhD-Forum: DATE 2010

Portrait: Frank Rogin
Dr. Frank Rogin
An Integrated Approach to Utilize Designer´s Debug Capacity in System-on-a-Chip Designs

also presented in PhD-Forum: DATE 2009

Portrait: Daniel Große
Dr. Daniel Große
Quality-Driven Design and Verification Flow for Digital Systems

ausgezeichnet mit dem Sonderpreis der Bruker Daltonik GmbH im Rahmen des Bremer Studienpreises 2009
also presented in PhD-Forum: DATE 2008

Portrait: Sebastian Kinder
Dr. Sebastian Kinder
Automated Validation and Verification of Railway Specific Components and Systems

Portrait: Junhao Shi
Dr. Junhao Shi
Boolean Techniques in Testing of Digital Circuits

Portrait: Görschwin Fey
Dr. Görschwin Fey
Increasing Robustness and Usability of Circuit Design Tools by Using Formal Techniques

also presented in PhD-Forum: DATE 2007

Statistic | since the year 2006 Statistic since the year 2006

Earning a doctoral degree represents a significant milestone in the scientific career. Thus, it is definitely a reason to celebrate this day accordingly. On their special day, the graduates not only have to face specific technical questions during the colloquium, but also complete various quiz rounds on topics from everyday life and leisure. These impressions usually remain unforgettable and should not be withheld from public.

©2023 | Group of Computer Architecture | Contact | Legal & Data Privacy