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Group of Computer Architecture / AGRA | Computer Science | Faculty 03 | University of Bremen

Workshops


MicroRV32, A RISC-V Platform for Education and Research
Author: Sallar Ahmadi-Pour, Rolf Drechsler
Workshop: Soft RISC-V Systems Workshop (SRvS Workshop)
Reference: Online Event, 2024
Extend and Reduce Methodology to Enable Formal Verification of Truncated Adders
Author: Chandan Kumar Jha, Khushboo Qayyum, Muhammad Hassan, Rolf Drechsler
Workshop: 16th International Workshop on Boolean Problems (IWSBP)
Reference: Bremen, Germany, 2024
SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited Cutwidth
Author: Luca Mueller, Rolf Drechsler
Workshop: 16th International Workshop on Boolean Problems (IWSBP)
Reference: Bremen, Germany, 2024
Why less is sometimes more -- Using Boolean literals to solve 2048
Author: Bernhard J. Berger, Christina Plump and Rolf Drechsler
Workshop: 16th International Workshop on Boolean Problems (IWSBP)
Reference: Bremen, Germany, 2024
Symbolic Execution of Binary Code based on Formal ISA Semantics
Author: Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler
Workshop: International KLEE Workshop on Symbolic Execution
Reference: Lisbon, Portugal, 2024
Design Automation Challenges and Benefits of Dynamic Quantum Circuit in Present NISQ Era and Beyond
Author: Abhoy Kole, Kamalika Datta, Rolf Drechsler
Workshop: International Workshop on Quantum Computing: Circuits Systems Automation and Applications, Co-located with ISVLSI 2024
Pdf | Reference: Knoxville, Tennessee, USA, 2024
RISC-V Opt-VP: An Application Analysis Platform Using Bounded Execution Trees
Author: Jan Zielasko, Rune Krauss, Marcel Merten, Rolf Drechsler
Workshop: RISC-V Summit Europe
Pdf | Reference: Munich, Germany, 2024
Cross-Level Verification of Hardware Peripherals
Author: Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Workshop: RISC-V Summit Europe
Pdf | Reference: Munich, Germany, 2024
How Can Generative AI Curate the User Creativity on an Idea Crowdsourcing Platform?
Author: Sana Hassan Imam, Christopher Alexander Metz, Rolf Drechsler
Workshop: ACM CHI 24 workshop on Generative AI in User-Generated Content
Reference: Hawaii & Virtual, 2024
Enhancing Resilience against Sequential Attacks on Logic Locking using Evolutionary Strategies
Author: Marcel Merten, Mohammed E. Djeridane, Muhammad Hassan, Niladri Bhattacharjee, Jens Trommer, Thomas Mikolajick, Rolf Drechsler
Workshop: GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Darmstadt, Germany, 2024
An Evolutionary Approach to Reconfigurable Scan Network Design
Author: Payam Habiby, Fatemeh Shirinzadeh und Rolf Drechsler
Workshop: GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Darmstadt, Germany, 2024
LLM-Assisted High Quality Invariants Generation for Formal Verification
Author: Khushboo Qayyum, Sallar Ahmadi-Pour, Muhammad Hassan, Chandan Kumar Jha, Rolf Drechsler
Workshop: University Fair at Design, Automation and Test in Europe (DATE)
Reference: Valencia, Spain, 2024
Towards Completeness: Security Coverage for System Level IFT
Author: Ece Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Landau, Germany, 2024
Towards ML-based Performance Estimation of Embedded Software: A RISC-V Case Study
Author: Weiyan Zhang, Muhammad Hassan, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Landau, Germany, 2024
Workshop: „Aktuelle Entwicklungen und Perspektiven (an Hochschulen) im Bereich Data Science“
Author: Lena Steinmann, Dirk Nowotka, Lea Oberländer, Helen Pfuhl, Heiner Stuckenschmidt und Rolf Drechsler
Workshop: INFORMATIK 2023
Pdf | Reference: Berlin, Deutschland, 2023
Data Train – The Cross-disciplinary Training in Research Data Management and Data Science
Author: Tanja Hörner, Maya Dalby, Frank Oliver Glöckner, Rolf Drechsler, Iris Pigeot
Workshop: Aktuelle Entwicklungen und Perspektiven auf INFORMATIK 2023
Reference: Berlin, Deutschland, 2023
Establishing discipline-specific Data Stewardship at the Data Science Center of the University of Bremen – One Year Review
Author: Sandra Zänkert, Heike Thöricht, Lena Steinmann, Rolf Drechsler
Workshop: Data Stewardship goes Germany
Reference: Dresden, Germany, 2023
Automated Testing of Stateful Network Protocol Implementations in the IoT
Author: Sören Tempel, Rolf Drechsler
Workshop: RIOT Summit
Video | Reference: Frankfurt, Germany, 2023
Polynomial Formal Verification exploiting Constant Cutwidth
Author: Mohamed Nadeem, Jan Kleinekathöfer, Rolf Drechsler
Workshop: International Workshop on Rapid System Prototyping (RSP)
Pdf | Reference: Hamburg, Germany, 2023
Classifying Crowdsouring Platform Users’ Engagement Behaviour using Machine Learning and XAI
Author: Sana Hassan Imam, Christopher Metz, Lars Hornuf, Rolf Drechsler
Workshop: MCI-WS16 - UCAI 2023: Workshop on User-Centered Artificial Intelligence
Pdf | Reference: DOI:10.18420/muc2023-mci-ws16-385, Rapperswil, Switzerland, 2023
Automated Formal Verification Methodology for MAGIC Design Style Based In-Memory Computing
Author: Chandan Kumar Jha, Khushboo Qayyum, Kemal Çağlar Coşkun, Simranjeet Singh, Muhammad Hassan, Rainer Leupers, Farhad Merchant, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: EPFL, Lausanne, Switzerland, 2023
Expanding RISC-V Horizons: Streamlining Heterogeneous Systems Evaluation with Open Source RISC-V AMS VP Framework
Author: Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Workshop: RISC-V Summit Europe
Pdf | Reference: Barcelona, Spain, 2023
Scale4Edge – Scaling RISC-V for Edge Applications
Author: Wolfgang Ecker, Milos Krstic, Markus Ulbricht, Andreas Mauderer, Eyck Jentzsch, Andreas Koch, Bastian Koppelmann, Wolfgang Mueller, Babak Sadiye, Niklas Bruns, Rolf Drechsler, Daniel Mueller-Gritschneder, Jan Schlamelcher, Kim Grüttner, Jörg Bormann, Wolfgang Kunz, Reinhold Heckmann, Gerhard Angst, Ralf Wimmer, Bernd Becker, Tobias Faller, Paul Palomero Bernardo, Oliver Bringmann, Johannes Partzsch, Christian Mayr
Workshop: RISC-V Summit Europe
Pdf | Reference: Barcelona, Spain, 2023
Polynomial Formal Verification of KFDD Circuits
Author: Martha Schnieber, Rolf Drechsler
Workshop: 2023 Reed-Muller Workshop (RM2023)
Reference: Matsue, Shimane, Japan, 2023
Polynomial Formal Verification of Adder Circuits Using Answer Set Programming
Author: Mohamed Nadeem, Jan Kleinekathöfer and Rolf Drechsler
Workshop: 2023 Reed-Muller Workshop (RM2023)
Pdf | Reference: Matsue, Shimane, Japan, 2023
Fast and Accurate: Machine Learning Techniques for Performance Estimation of CNNs for GPGPUs
Author: Christopher Metz, Mehran Goli, and Rolf Drechsler
Workshop: 5th Workshop on Parallel AI and Systems for the Edge (PAISE)
Pdf | Reference: St. Petersburg, USA, 2023
Security Validation of VP-based Heterogeneous Systems: A Completeness-driven Perspective
Author: Ece Nur Demirhan Coskun, Muhammad Hassan, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Freiburg, Germany, 2023
Equivalence Checking of Majority-based Function Mapping on ReRAM Crossbars
Author: Arighna Deb, Kamalika Datta, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Freiburg, Germany, 2023
Towards Comprehensive Verification of Hardware and Software for RISC-V based Embedded Systems
Author: Niklas Bruns, Sallar Ahmadi-Pour, Sören Tempel, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Freiburg, Germany, 2023
Divider Verification Using Symbolic Computer Algebra and Delayed Don’t Care Optimization
Author: Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: Freiburg, Germany, 2023
Remote Configuration Methodology for IEEE 1687 Scan Networks
Author: Payam Habiby, Sebastian Huhn and Rolf Drechsler
Workshop: 35. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Erfurt, Germany, 2023
New Directions for Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits
Author: Kemal Çağlar Coşkun, Muhammad Hassan and Rolf Drechsler
Workshop: 35. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Erfurt, Germany, 2023
How Secure Is A Circuit Against Optical Probing? Developed Countermeasures, In Progress Countermeasures Development, and the Future Works
Author: Sajjad Parvin, Frank Sill Torres and Rolf Drechsler
Workshop: 11th International Workshop on Cryptography, Robustness, and Provably Secure Schemes for Female Young Researchers (CrossFyre)
Reference: Passau, Germany, 2022
OPTI-RISK: Design of an Optical Probing Attack Hardened RISC-V Core with an Industrially Compatible CMOS Gate Library
Author: Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, and Rolf Drechsler
Workshop: 5th RISC-V Activity Workshop
Reference: Berlin, Germany, 2022
ANN-based Performance Estimation of Embedded Software for RISC-V Processors
Author: Weiyan Zhang, Mehran Goli, Alireza Mahzoon, Rolf Drechsler
Workshop: International Workshop on Rapid System Prototyping (RSP)
Pdf | Reference: Hamburg, Germany, 2022
HLS-ing Up RISC-V: Streamlining Design and Optimization
Author: Deepak Ravibabu, Muhammad Hassan and Rolf Drechsler
Workshop: University Fair at Design, Automation and Test in Europe (DATE)
Reference: Antwerpen, Belgien, 2023
Symbolic Execution for RISC-V Embedded Software Using SystemC Peripheral Models
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Workshop: 3rd International KLEE Workshop on Symbolic Execution
Video | Reference: London, 2022
Automated Testing of RIOT modules using SymEx-VP
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Workshop: RIOT Summit
Video | Reference: Hamburg, Germany, 2022
One is not Enough: Using Hybrid Proof Engines for Polynomial Formal Verification
Author: Rolf Drechsler, Alireza Mahzoon
Workshop: 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)
Reference: Hirosaki, Japan, 2022
Mapping Quantum Circuits to 2-D Quantum Architectures
Author: Kamalika Datta, Abhoy Kole, Indranil Sengupta and Rolf Drechsler
Workshop: GI Quantum Computing Workshop 2022 (GI QC 22)
Pdf | Reference: Hamburg, Germany, 2022
SAT-based Key Determination Attack for Improving the Quality Assessment of Logic Locking Mechanisms
Author: Marcel Merten, Mohammed E. Djeridane, Sebastian Huhn, Rolf Drechsler
Workshop: 15th International Workshop on Boolean Problems (IWSBP)
Pdf | Reference: Bremen, Germany, 2022
Towards System-level Assertions for Heterogeneous Systems
Author: Muhammad Hassan, Thilo Voertler, Karsten Einwich, Rolf Drechsler,Daniel Grosse
Workshop: 15th International Workshop on Boolean Problems (IWSBP)
Pdf | Reference: Bremen, Germany, 2022
Feature Importance and Extensibility for Predicting Loan Defaults in Marketplace Lending using BiLSTM
Author: Sana Hassan Imam, Sebastian Huhn, Lars Hornuf, Rolf Drechsler
Workshop: Frontiers of Factor Investing Conference (FoFi)
Reference: Lancaster, UK, 2022
Polynomial Formal Verification of Approximate Adders
Author: Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: Virtual Conference , 2022
Polynomial Formal Verification of Complex Multipliers
Author: Alireza Mahzoon, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: Virtual, 2022
Self-Explanation in Systems of Systems
Author: Goerschwin Fey, Martin Fränzle and Rolf Drechsler
Workshop: Second International Workshop on Requirements Engineering for Explainable Systems (RE4ES)
Reference: Melbourne, Victoria, Australia (virtual event with a local hub), 2022
Simulation-based Verification of SystemC-based VPs at the ESL
Author: Mehran Goli, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Virtual, 2022
RISC-V Processor Verification with Coverage-guided Aging
Author: Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Virtual, 2022
System Level Verification of Analog/Mixed-Signal Systems using Metamorphic Relations
Author: Muhammad Hassan and Rolf Drechsler
Workshop: 34. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Bremerhaven, Germany, 2022
Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods
Author: Marcel Merten, Sebastian Huhn and Rolf Drechsler
Workshop: 34. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Bremerhaven, Germany, 2022
An ILP-based Global Optimum Test Scheduler for IEEE 1687 Multi-Power Domain Networks
Author: Payam Habiby, Sebastian Huhn and Rolf Drechsler
Workshop: 34. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Bremerhaven, Germany, 2022
Verification of RISC-V Embedded Software by Integrating Concolic Testing with SystemC-based Virtual Prototypes
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Workshop: 4th Workshop on RISC-V Activities
Reference: Virtual Conference, 2021
Polynomial Formal Verification of Prefix Adders
Author: Alireza Mahzoon, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: Virtual Conference, 2021
Polynomial Formal Verification of Area-efficient and Fast Adders
Author: Alireza Mahzoon, Rolf Drechsler
Workshop: 2021 Reed-Muller Workshop (RM2021)
Pdf | Video | Reference: Nursultan, Kazakhstan, 2021
MicroRV32: An Open Source RISC-V Cross-Level Platform for Education and Research
Author: Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Workshop: Design Automation for CPS and IoT (DESTION)
Pdf | Reference: Nashville, USA, 2021
GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools
Author: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: München, Germany, 2021
Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
Author: Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: München, Germany, 2021
VP-based DIFT for Embedded Binaries: A RISC-V Case Study
Author: Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: München, Germany, 2021
MicroRV32: A SpinalHDL based RISC-V Implementation for FPGAs
Author: Sallar Ahmadi-Pour, Vladimir Herdt and Rolf Drechsler
Workshop: University Booth at Design, Automation and Test in Europe (DATE)
Pdf | Reference: Grenoble, France, 2021
Efficient Techniques to Boost RISC-V Compliance Testing
Author: Vladimir Herdt and Rolf Drechsler
Workshop: Workshop on Interdependent Challenges of Reliability, Security and Quality (RESCUE)
Reference: Grenoble, France, 2021
A Memory-Upscaled Boolean Satisfiability Solver for Complex On-Chip Self-Verification Tasks
Author: Buse Ustaoglu, Sebastian Huhn and Rolf Drechsler
Workshop: Workshop on Interdependent Challenges of Reliability, Security and Quality (RESCUE)
Pdf | Reference: Grenoble, France, 2021
Pick the Right Edge Device: Towards Power and Performance Estimation of CUDA-based CNNs on GPGPUs
Author: Christopher Metz, Mehran Goli, Rolf Drechsler
Workshop: System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA)
Pdf | Reference: Grenoble, France, 2021
Test Scheduling Optimization Model for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability
Author: Payam Habiby, Sebastian Huhn and Rolf Drechsler
Workshop: 33. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Nordhausen, Germany, 2021
SAT-based Exact Physical Design for Field-coupled Nanocomputing Technologies
Author: Marcel Walter, Winston Haaswijk, Robert Wille, Frank Sill Torres, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: San Francisco, USA, 2020
Fuzz-Testing RISC-V Simulators
Author: Vladimir Herdt, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: Stuttgart, Germany, 2020
Coverage-Directed Stimuli Generation for Characterization of RF Amplifiers
Author: Muhammad Hassan, Daniel Große, Ahmad Asghar, Rolf Drechsler
Workshop: 32. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2020)
Pdf | Reference: Stuttgart, Germany, 2020
Power-Layout-Aware Test Pattern Re-scheduling
Author: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Workshop: 32. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2020)
Reference: Stuttgart, Germany, 2020
Integrating Hybrid Analysis with Machine Learning Techniques for Portion Resilience Evaluation in Approximating SystemC-based Designs
Author: Mehran Goli, Rolf Drechsler
Workshop: Workshop on Machine Learning for CAD (MLCAD)
Reference: Canmore (Banff Area), Alberta, Canada, 2019
GenMul: Generating architecturally complex multipliers to challenge formal verification tools
Author: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: Lausanne, Switzerland, 2019
fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits
Author: Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: Lausanne, Switzerland, 2019
Self-Explaining Digital Systems – Some Technical Steps
Author: Goerschwin Fey and Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Kaiserslautern, Germany, 2019
Towards Gate-Level Design of QCA Circuits
Author: Philipp Niemann, Igor Kazhdan, Frank Sill Torres, Rolf Drechsler
Workshop: 6th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Florence, Italy, 2019
Enhanced Embedded Test Compression Technique For Processing Incompressible Test Patterns
Author: Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler
Workshop: 31. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Prien am Chiemsee, Germany, 2019
IR-drop Prediction of Test Patterns Using Parasitic Elements
Author: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Workshop: 31. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2019)
Reference: Prien am Chiemsee, Germany, 2019
Optimizing Ts in the Synthesis of Clifford+T Quantum Circuits
Author: Philipp Niemann, Robert Wille, Rolf Drechsler
Workshop: 2nd International Workshop on Quantum Compilation (IWQC, co-located with ICCAD)
Reference: San Diego, CA, USA, 2018
Improving SAT solving using Monte Carlo Tree Search-based Clause Learning
Author: Oliver Keszöcze, Kenneth Schmitz, Jens Schloeter, Rolf Drechsler
Workshop: 13th International Workshop on Boolean Problems (IWSBP)
Reference: Bremen, Germany, 2018
ConfidenceSat: A Parallel SAT Solver with Conflict Clause Handling
Author: Kenneth Schmitz, Oliver Keszöcze, Jil Tietjen and Rolf Drechsler
Workshop: 13th International Workshop on Boolean Problems (IWSBP)
Reference: Bremen, Germany, 2018
A Document-oriented, Heterogeneous Database Model for Large Experimental Data Sets
Author: Timo Kohorst and Sebastian Huhn and Rolf Drechsler
Workshop: MAPEX Symposium
Pdf | Reference: Bremen, Germany, 2018
Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation
Author: Rolf Drechsler, Christoph Lüth, Goerschwin Fey, Tim Güneysu
Workshop: 3nd International Verification and Security Workshop (IVSW)
Pdf | Reference: Costa Brava, Spain, 2018
Evaluation of Power State Cross Coverage in Firmware-Based Power Management
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: Embedded Software for Industrial IoTs (ESIIT)
Reference: Dresden, Germany, 2018
Time-stamps for Hardware Simulation Models Accurate Time-back Annotation
Author: Rehab Massoud, Jannis Stoppe, Karthik Maddikunta, Rolf Drechsler
Workshop: 5th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Dresden, Germany, 2018
Execution Environment for Dynamic Software Runtime Examination
Author: Kenneth Schmitz, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Workshop: 5th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Dresden, Germany, 2018
A Codeword-based Compaction Technique for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks
Author: Sebastian Huhn, Marcel Merten, Stephan Eggersglüß and Rolf Drechsler
Workshop: 30. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Freiburg (Breisgau), Germany, 2018
ATPG Constraint Analysis for Reducing Regional Power Activity
Author: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen
Workshop: 30. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2018)
Reference: Freiburg (Breisgau), Germany, 2018
Towards Automated Refinement of TLM Properties to RTL
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: Tübingen, Germany, 2018
Revisiting Symbolic Software-implemented Fault Injection
Author: Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Workshop: 2nd International Workshop on Resiliency in Embedded Electronic Systems (REES)
Reference: Lausanne, Switzerland, 2017
Making Waveforms Great Again
Author: Jannis Stoppe and Rolf Drechsler
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Lausanne, Switzerland, 2017
A Human-Centered Approach to Routing for Digital Microfluidic Biochips
Author: Oliver Keszöcze, Andre Pols and Rolf Drechsler
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Lausanne, Switzerland, 2017
Verilog2GEXF - Dynamic Large Scale Circuit Visualization
Author: Kenneth Schmitz, Jannis Stoppe, Rolf Drechsler
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Lausanne, Switzerland, 2017
Computing Exact Fault Candidates Incrementally
Author: Heinz Riener, Görschwin Fey
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Lausanne, Switzerland, 2017
Mining Latency Guarantees for RT-level Designs
Author: Jan Malburg, Heinz Riener, Görschwin Fey
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Lausanne, Switzerland, 2017
Der Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips
Author: Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: Bremen, Germany, 2017
Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing
Author: Saman Fröhlich, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: pp. 27-38, Bremen, Germany, 2017
Counterexample-Guided EF Synthesis of Boolean Functions
Author: Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: Bremen, Germany, 2017
A Lightweight Method for Transient Test Power Pattern Analysis for Pattern Selection
Author: Harshad Dhotre, Stephan Eggersglüß
Workshop: 29. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2017)
Reference: Lübeck, Germany, 2017
Using Lightweight Containers in Hardware/Software Co-Design for Security
Author: Daniel Große, Kenneth Schmitz, Rolf Drechsler
Workshop: Workshop on Computer-Aided Design and Implementation for Cryptography and Security (CADICS)
Reference: Austin, USA, 2016
Integrating an SMT-based Model Finder into USE
Author: Nils Przigoda, Frank Hilken, Judith Peters, Robert Wille, Martin Gogolla, Rolf Drechsler
Workshop: Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Reference: Saint-Malo, France, 2016
On the computational complexity of error metrics in approximate computing
Author: Oliver Keszöcze, Mathias Soeken, Rolf Drechsler
Workshop: International Workshop on Boolean Problems
Reference: Freiberg, Germany, 2016
Counterexample-Guided Diagnosis
Author: Heinz Riener, Görschwin Fey
Workshop: International Verification and Security Workshop (IVSW'16)
Pdf | Reference: Sant Feliu de Guixols, Catalunya, Spain, 2016
Generating good properties from a small number of use cases
Author: Jan Malburg, Tino Flenker, Görschwin Fey
Workshop: International Verification and Security Workshop (IVSW'16)
Reference: Sant Feliu de Guixols, Catalunya, Spain, 2016
SystemCDG - AI Based Coverage Driven Stimuli Generation for SystemC
Author: Jannis Stoppe, Arved Friedemann, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: Austin, TX, USA, 2016
SMT-Based CPS Parameter Synthesis
Author: Heinz Riener, Robert Könighofer, Görschwin Fey, Roderick Bloem
Workshop: Applied Verification for Continuous and Hybrid Systems (ARCH@CPSWeek'16)
Pdf | Reference: pp. 126-133, Vienna, Austria, 2016
Synthesis of Optical Circuits with Contradictory Optimization Objectives
Author: Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler
Workshop: The 2nd International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop)
Reference: Dresden, Germany, 2016
Change Management for Hardware Designers
Author: Martin Ring, Jannis Stoppe, Christoph Lüth, Rolf Drechsler
Workshop: Workshop on Design Automation for Understanding Hardware Designs (DUHDE)
Reference: Dresden, Germany, 2016
Visualizing Microfluidic Biochips Interactively
Author: Jannis Stoppe, Oliver Keszöcze, Robert Wille, Rolf Drechsler
Workshop: Workshop on Design Automation for Understanding Hardware Designs (DUHDE)
Reference: Dresden, Germany, 2016
Matching Abstract and Concrete Hardware Models for Design Understanding
Author: Tino Flenker, Görschwin Fey
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDE)
Pdf | Reference: Dresden, Germany, 2016
Leichtgewichtige Datenkompressions-Architektur für IEEE 1149.1-kompatible Testschnittstellen
Author: Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler
Workshop: 28. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Siegen, Germany, 2016
Eliminierung von energieunsicheren Tests in kompakten Testmengen
Author: Stephan Eggersglüß
Workshop: 28. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference: Siegen, Germany, 2016
A Hybrid Algorithm to Conservatively Check the Robustness of Circuits
Author: Niels Thole, Lorena Anghel, Görschwin Fey
Workshop: 28. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Siegen, Germany, 2016
Symbolic Error Metric Determination for Approximate Computing
Author: Arun Chandrasekharan, Daniel Große, Mathias Soeken, Rolf Drechsler
Workshop: 19. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'16)
Reference: Freiburg, Germany, 2016
Extraktion von Frame Conditions aus Operation Contracts
Author: Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Workshop: Software Engineering (SE)
Reference: Vienna, Austria, 2016
Parity-based Soft Error Detection with Software-based Retry vs. Triplication-based Soft Error Correction - An Analytical Comparison on a Flash-based FPGA Architecture
Author: Gökçe Aydos, Görschwin Fey
Workshop: Workshop Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen
Pdf | Reference: Cottbus, Germany, 2015
Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses
Author: Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop: Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Reference: Ottawa, Canada, 2015
Towards Generating Test Suites with High Functional Coverage for Error Effect Simulation
Author: Aljoscha Windhorst, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 1st International ESWEEK Workshop on Resiliency in Embedded Electronic Systems
Reference: Amsterdam, The Netherlands, 2015
Game-based Synthesis of Distributed Controllers for Sampled Switched Systems
Author: Laurent Fribourg, Ulrich Kühne, Nicolas Markey
Workshop: International Workshop on Synthesis of Complex Parameters
Pdf | Reference: London, 2015
Simulation Graphs for Reverse Engineering
Author: Baruch Sterin, Mathias Soeken, Rolf Drechsler, Robert K. Brayton
Workshop: International Workshop on Logic Synthesis (IWLS)
Reference: Mountain View, CA, USA, 2015
Quo Vadis, Reversible Circuit Design? Towards Scaling Design and Synthesis of Reversible Circuits
Author: Eleonora Schönborn, Robert Wille, Rolf Drechsler
Workshop: Reed-Muller Workshop
Reference: Waterloo, Canada, 2015
Self-Inverse Functions and Palindromic Circuits
Author: Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller
Workshop: Reed-Muller Workshop
Reference: Waterloo, Canada, pre-print available at arXiv:1502.05825, 2015
Path-Based Program Repair
Author: Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Workshop: 12th International Workshop on Formal Engineering approaches to Software Components and Architectures, Satellite event of ETAPS (FESCA'15)
Pdf | Reference: pp. 22-32, London, United Kingdoms, 2015
Fehlereffektsimulation mittels virtueller Prototypen
Author: Sebastian Reiter, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Rolf Drechsler, Wolfgang Ecker, Thomas Kruse, Christoph Kuznik, Jo Laufenberg, Hoang M. Le, Petra Maier, Daniel Müller-Gritschneder, Hendrik Post, Jan-Hendrik Oetjens, Wolfgang Rosenstiel, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl
Workshop: GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference: Bad Urach, 2015
Analyzing an SET at Gate Level using a Conservative Approach
Author: Niels Thole, Görschwin Fey, Alberto Garcia-Ortiz
Workshop: GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Bad Urach, 2015
Erzeugung diagnostischer Testmuster unter komplexen Constraints
Author: Tobias Koal, Stephan Eggersglüß, Mario Schölzel
Workshop: GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference: Bad Urach, 2015
Verbesserung der Fehlersuche in inkonsistenten formalen Modellen
Author: Nils Przigoda, Robert Wille, Rolf Drechsler
Workshop: 18. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'15)
Reference: Chemnitz, Germany, 2015
Execution Tracing of C Code for Formal Analysis
Author: Heinz Riener, Michael Kirkedal Thomsen, Görschwin Fey
Workshop: 18. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'15)
Reference: Chemnitz, Germany, 2015
Towards analysing feature locations through testing traces with BUT4Reuse
Author: Jabier Martinez, Jan Malburg, Tewfik Ziadi, Görschwin Fey
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Grenoble, France, 2015
Ecore Model Generation from SystemC/C++ Implementations
Author: Jannis Stoppe, Rolf Drechsler
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Grenoble, France, 2015
Mutation based Feature Localization
Author: Jan Malburg, Emmanuelle Encrenaz-Tiphene, Görschwin Fey
Workshop: 15th International Workshop on Microprocessor Test and Verification
Pdf | Reference: Austin, USA, 2014
Coverage at the Formal Specification Level
Author: Rolf Drechsler, Julia Seiter, Mathias Soeken
Workshop: International Workshop on Design and Implementation of Formal Tools and Systems (DIFTS)
Reference: Lausanne, Switzerland, 2014
Towards a Base Model for UML and OCL Verification
Author: Frank Hilken, Philipp Niemann, Robert Wille, Martin Gogolla
Workshop: Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Reference: Valencia, Spain, 2014
A framework for reversible circuit complexity
Author: Mathias Soeken, Nabila Abdessaied, Rolf Drechsler
Workshop: 10th International Workshop on Boolean Problems
Pdf | Reference: Freiberg, Germany, post-print available at arXiv:1407.5878, 2014
Towards a Multi-dimensional and Dynamic Visualization for ESL Designs
Author: Jannis Stoppe, Marc Michael, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Reference: Dresden, Germany, 2014
Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques (Extended Abstract)
Author: Jan Malburg, Niklas Krafczyk, Görschwin Fey
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Pdf | Reference: page 30, Dresden, Germany, 2014
Mutation based Feature Localization
Author: Jan Malburg, Emmanuelle Encrenaz-Tiphene, Görschwin Fey
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Reference: pp. 55-60, Dresden, Germany, 2014
Formale Methoden für Alle
Author: Mathias Soeken, Max Nitze, Rolf Drechsler
Workshop: 17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Reference: Böblingen, Germany, 2014
Equivalence Checking on System Level using Stepwise Induction
Author: Niels Thole, Görschwin Fey
Workshop: 17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Pdf | Reference: Böblingen, Germany, 2014
Funktionale Abdeckungsanalyse von C-Programmen
Author: Aljoscha Windhorst, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Reference: pp. 201-204, Böblingen, Germany, 2014
A Logic for Cardinality Constraints
Author: Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey
Workshop: 17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Reference: Böblingen, Germany, 2014
Debug Automatisierung für logische Schaltungen unter Zeitvariation mittels Waveforms
Author: Mehdi Dehbashi, Görschwin Fey
Workshop: 26. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference: Bad Staffelstein, Germany, 2014
Hohe Testmengenkompaktierung durch formale Optimierungstechniken
Author: Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Workshop: Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference: Bad Staffelstein, 2014
Using Optimization Techniques to Increase Test Compaction
Author: Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Workshop: IEEE 14th Workshop on RTL and High Level Testing (WRTLT'13)
Reference: Yilan, Taiwan, 2013
Law-based Verification for Complex Swarm Systems
Author: Rolf Drechsler, Hoang M. Le, Mathias Soeken, Robert Wille
Workshop: International Workshop on the Swarm at the Edge of the Cloud
Reference: Montreal, Canada, 2013
lips: An IDE for Model Driven Engineering Based on Natural Language Processing
Author: Oliver Keszöcze, Mathias Soeken, Eugen Kuksa, Rolf Drechsler
Workshop: Workshop on Natural Language Analysis in Software Engineering (NaturaLiSE)
Pdf | Reference: pp. 31-38, San Francisco, 2013
Towards Automatic Scenario Generation from Coverage Information
Author: Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
Workshop: 8th International Workshop on Automation of Software Test (AST)
Pdf | Reference: pp. 82-88, San Francisco, 2013
SystemC Verifikation mittels symbolischer Simulation einer Zwischensprache
Author: Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
Workshop: edaWorkshop
Pdf | Reference: pp. 53-58, Dresden, Germany, 2013
Yet a Better Error Explanation Algorithm
Author: Heinz Riener, Görschwin Fey
Workshop: 16. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'13)
Pdf | Reference: pp.193-194, Rostock, Germany, 2013
Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen
Author: Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler
Workshop: 16. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: Rostock, Germany, 2013
Towards Debug Automation for Timing Bugs at RTL
Author: Mehdi Dehbashi, Görschwin Fey
Workshop: 25. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Dresden, Germany, 2013
Verification of Embedded Systems Using Modeling and Implementation Languages
Author: Mathias Soeken, Heinz Riener, Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop: International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs'12)
Pdf | Reference: pp. 67-72, Tampere, Finland, 2012
Towards Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints
Author: Stephan Eggersglüß, Melanie Diepenbeck, Robert Wille, Rolf Drechsler
Workshop: IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12)
Pdf | Reference: Niigata, Japan, 2012
Behavior Driven Development for Circuit Design and Verification
Author: Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
Workshop: IEEE International Workshop on High-Level Design Validation and Test (HLDVT)
Pdf | Reference: pp. 9-16, Huntington Beach, USA, 2012
Towards Embedding of Large Functions for Reversible Logic
Author: Mathias Soeken, Robert Wille, Laura Tague, D. Michael Miller, Rolf Drechsler
Workshop: International Workshop on Boolean Problems
Reference: Freiberg, 2012
Model-Based Diagnosis versus Error Explanation
Author: Heinz Riener, Görschwin Fey
Workshop: International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES'12) in conjunction with 49th Design Automation Conference (DAC'12)
Pdf | Reference: San Francisco, USA, 2012
FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation
Author: Heinz Riener, Görschwin Fey
Workshop: 19th International SPIN Workshop on Model Checking of Software (SPIN'12)
Pdf | Reference: pp. 234-240, Oxford, United Kingdoms, 2012
Using πDDs in the Design for Reversible Circuits
Author: Mathias Soeken, Robert Wille, Shin-Ichi Minato, Rolf Drechsler
Workshop: Workshop on Reversible Computation
Reference: Kopenhagen, 2012
Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams
Author: Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop: Workshop on Reversible Computation
Reference: Kopenhagen, 2012
Design Understanding by Feature Localization on ESL
Author: Marc Michael, Daniel Große, Rolf Drechsler
Workshop: 9. GMM/ITG/GI-Workshop Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS)
Reference: pp. 19-24, Dresden, 2012
Compilation of Methodologies to Speed up the Verification Process at System Level
Author: Stephan Radke, Steffen Rülke, Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Müller, Wolfgang Ecker, Volkan Esen, Simon Hufnagel, Nico Bannow, Helmut Brazdrum, Peter Janssen, Hoang M. Le, Daniel Große, Rolf Drechsler, Erhard Fehlauer, Gernot Koch, Andreas Burger, Oliver Bringmann, Wolfgang Rosenstiel, Finn Haedicke, Ralph Görgen, Jan-Hendrik Oetjens
Workshop: edaWorkshop
Reference: pp. 57-62, Hannover, 2012
Functional Analysis of Circuits Under Timing Variations
Author: Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Workshop: edaWorkshop
Pdf | Reference: Hannover, Germany, 2012
SystemC-based ESL Verification Flow Integrating Property Checking and Automatic Debugging
Author: Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: DATE Friday Workshop: OSCI and Accellera Core Technologies for the Next Generation of System-Level Design
Reference: Dresden, 2012
CRAVE: An Advanced Constrained Random Verification Environment for SystemC
Author: Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 15. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: pp. 37-48, Kaiserslautern
Software and benchmarks available at www.systemc-verification.org, 2012
Automated Debugging from Pre-Silicon to Post-Silicon
Author: Mehdi Dehbashi, Görschwin Fey
Workshop: 24. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference: Cottbus, Germany, 2012
Automated Feature Localization for Hardware Designs using Coverage Metrics
Author: Jan Malburg, Alexander Finder, Görschwin Fey
Workshop: 15. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: pp. 85-96, Kaiserslautern, Germany, 2012
Towards Proving TLM Properties with Local Variables
Author: Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 7th International Workshop on Constraints in Formal Verification (CFV)
Pdf | Reference: San Jose, 2011
Parametric Verification and Test Coverage for Hybrid Automata Using the Inverse Method
Author: Laurent Fribourg, Ulrich Kühne
Workshop: 5th Workshop on Reachability Problems (RP)
Pdf | Reference: Genua, 2011
Towards Automatic Determination of Problem Bounds for Object Instantiation in Static Model Verification
Author: Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop: Model-Driven Engineering, Verification, And Validation (MoDeVVa)
Reference: Wellington, 2011
metaSMT: Focus on Your Application not on Solver Integration
Author: Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler
Workshop: DIFTS'11: 1st International workshop on design and implementation of formal tools and systems
Pdf | Reference: pp. 22-29, Austin, USA, 2011
Tangicons - Programmieren im Kindergarten
Author: Thomas Winkler, Florian Scharf, Judith Peters, Michael Herczeg
Workshop: Tagung Mensch & Computer
Reference: pp. 23-24, Chemnitz, 2011
Synthesis of Reversible Circuits with Minimal Lines for Large Functions
Author: Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
Workshop: Workshop on Reversible Computation
Reference: pp. 59-70, Gent, 2011
Customized Design Flows for Reversible Circuits Using RevKit
Author: Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Workshop: Workshop on Reversible Computation
Reference: pp. 91-96, Gent, 2011
Formal Analysis Techniques: A Basis for High-Quality Designs
Author: Stephan Eggersglüß, Rolf Drechsler
Workshop: IEEE International Workshop on Processor Verification, Test and Debug
Pdf | Reference: Invited Talk, Trondheim, 2011
Test Case Generation from Mutants using Model Checking Techniques
Author: Heinz Riener, Roderick Bloem, Görschwin Fey
Workshop: IEEE Fourth International Conference on Software Testing, Verification and Validation Workshops (ICSTW'11)
Pdf | Reference: pp. 388-397, Berlin, Germany, 2011
On Timing-Aware ATPG using Pseudo-Boolean Optimization
Author: Stephan Eggersglüß, Rolf Drechsler
Workshop: IEEE European Test Symposium (ETS), Informal Digest of Papers
Pdf | Reference: Trondheim, 2011
Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines
Author: Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler
Workshop: SORT 2011: 2nd IEEE Workshop on Self-Organizing Real-Time Systems
Reference: pp. 181-188, Newport Beach, 2011
Improving ESOP-based Synthesis of Reversible Logic Using Evolutionary Algorithms
Author: Rolf Drechsler, Alexander Finder, Robert Wille
Workshop: 6th European Workshop on Hardware Optimization Techniques (EvoHOT)
Pdf | Reference: Applications of Evolutionary Computation, LNCS 6625, pp. 151-161, Turin, 2011
Protocol Compliance Checking of SystemC TLM Models
Author: Mohamed Bawadekji, Daniel Große, Rolf Drechsler
Workshop: 8. GMM/ITG/GI-Workshop Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS)
Reference: pp. 27-32, Bremen, 2011
Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction
Author: Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Workshop: 14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: pp. 269-278, Oldenburg, 2011
Designing a RISC CPU in Reversible Logic
Author: Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Workshop: 14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: pp. 249-258, Oldenburg, 2011
Towards Automatic Property Generation for the Formal Verification of Bus Bridges
Author: Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Workshop: 14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: Oldenburg, 2011
As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
Author: Stephan Eggersglüß, Rolf Drechsler
Workshop: 23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2011
Pdf | Reference: Passau, 2011
Latency Analysis for Sequential Circuits
Author: Alexander Finder, André Sülflow, Görschwin Fey
Workshop: 23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2011
Pdf | Reference: Passau, 2011
SAT-based ATPG for Reversible Circuits
Author: Hongyan Zhang, Robert Wille, Rolf Drechsler
Workshop: 5th International Design & Test Workshop (IDT)
Reference: pp. 149-154, Abu Dhabi, 2010
Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition
Author: Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop: 5th International Design & Test Workshop (IDT)
Pdf | Reference: pp. 143-148, Abu Dhabi, 2010
Automatic Fault Localization for SystemC TLM Designs
Author: Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 11th International Workshop on Microprocessor Test and Verification (MTV)
Pdf | Reference: pp. 35-40, Austin, Texas, 2010
Towards Unifying Localization and Explanation for Automated Debugging
Author: Görschwin Fey, André Sülflow, Rolf Drechsler
Workshop: 11th International Workshop on Microprocessor Test and Verification (MTV)
Pdf | Reference: pp. 3-8, Austin, Texas, 2010
Evaluating Debugging Algorithms from a Qualitative Perspective
Author: Alexander Finder, Görschwin Fey
Workshop: International Workshop on Boolean Problems
Pdf | Reference: Freiberg, 2010
RevKit: A Toolkit for Reversible Circuit Design
Author: Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Workshop: Workshop on Reversible Computation
Pdf | Reference: pp. 69-72, Bremen, 2010
Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition
Author: Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop: Workshop on Reversible Computation
Reference: pp. 55-58, Bremen, 2010
Towards Analyzing Functional Coverage in SystemC TLM Property Checking
Author: Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: IEEE International Workshop on High-Level Design Validation and Test (HLDVT)
Pdf | Reference: pp. 67-74, Anaheim, 2010
SyReC: A Programming Language for Synthesis of Reversible Circuits
Author: Robert Wille, Sebastian Offermann, Rolf Drechsler
Workshop: International Workshop on Logic Synthesis (IWLS)
Reference: Irvine, 2010
Technische Dokumentation im V-Modell XT
Author: Beate Kapturek, Rolf Drechsler
Workshop: 17. Workshop der Fachgruppe WI-VM der Gesellschaft für Informatik e.V.
Pdf | Reference: Stuttgart, 2010
RobuCheck: A Robustness Checker for Digital Circuits
Author: Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
Workshop: The First International Workshop on Dynamic Aspects in Dependability Models for Fault-Tolerant Systems (DYADEM-FTS)
Reference: Valencia, 2010
VisSAT: Visualization of SAT Solver Internals
Author: Robert Wille, Andre Sülflow, Christian Genz, Rolf Drechsler
Workshop: University Booth at Design, Automation and Test in Europe (DATE10)
Pdf | Reference: Dresden, 2010
A Better-Than-Worst-Case Robustness Measure
Author: Stefan Frehse, Görschwin Fey, Rolf Drechsler
Workshop: 22. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2010
Pdf | Reference: Paderborn, 2010
SyReC: A Programming Language for Synthesis of Reversible Circuits
Author: Robert Wille, Sebastian Offermann, Rolf Drechsler
Workshop: 13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: Dresden, 2010
Verifying UML/OCL Models Using Boolean Satisfiability
Author: Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
Workshop: 13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: pp. 57-66, Dresden, 2010
Induction-based Formal Verification of SystemC TLM Designs
Author: Daniel Große, Hoang M. Le, Rolf Drechsler
Workshop: 10th International Workshop on Microprocessor Test and Verification (MTV)
Reference: pp. 101-106, Austin, Texas, 2009
Using QBF to Increase the Accuracy of SAT-Based Debugging
Author: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: International Workshop on Constraints in Formal Verification (CFV)
Pdf | Reference: Grenoble, France, 2009
Reducing Reversible Circuit Cost by Adding Lines
Author: D. Michael Miller, Robert Wille, Rolf Drechsler
Workshop: International Workshop on Logic Synthesis (IWLS)
Reference: Berkeley, 2009
Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost
Author: Robert Wille, Mehdi Saeedi, Rolf Drechsler
Workshop: International Workshop on Logic Synthesis (IWLS)
Pdf | Reference: Berkeley, 2009
Model-Based Diagnosis for Programmable Logic Controllers
Author: Andre Sülflow, Rolf Drechsler
Workshop: Gemeinsamer Workshop der Informatik-Graduiertenkollegs und Forschungskollegs
Reference: Dagstuhl, 2009
A Two-Stage SAT-based ATPG Approach with Reduced Switching Activity
Author: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Workshop: Second International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR) 2009
Pdf | Reference: Sevilla, Spain, 2009
Robustness Check for Multiple Faults using Formal Techniques
Author: Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
Workshop: Constraints in Formal Verification (CFV)
Pdf | Reference: Grenoble, France, 2009
Synthesizing Reversible Logic: An Overview
Author: Robert Wille, Rolf Drechsler
Workshop: Reed-Muller Workshop
Reference: Naha, Okinawa, 2009
Synthesising Reversible Circuits from Irreversible Specifications using Reed-Muller Spectral Techniques
Author: D. Michael Miller, Gerhard W. Dueck, Robert Wille
Workshop: Reed-Muller Workshop
Reference: Naha, Okinawa, 2009
FormED: A Formal Environment for Debugging
Author: Andre Sülflow, Robert Wille, Christian Genz, Görschwin Fey, Rolf Drechsler
Workshop: University Booth at Design, Automation and Test in Europe (DATE09)
Pdf | Reference: Nizza, 2009
Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
Author: Robert Wille, Rolf Drechsler
Workshop: Reversible Computation
Reference: York, 2009
A Fast Untestability Proof for SAT-based ATPG
Author: Daniel Tille, Rolf Drechsler
Workshop: 21. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2009
Pdf | Reference: Bremen, 2009
Algorithms for ATPG under Leakage Constraints
Author: Görschwin Fey
Workshop: 21. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2009
Pdf | Reference: Bremen, 2009
Using a Two-Dimensional Fault List for Compact Automatic Test Pattern Generation
Author: Marc Messing, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
Workshop: 10th IEEE Latin-American TestWorkshop (LATW)
Reference: Búzios, Rio de Janeiro, 2009
Increasing the Accuracy of SAT-based Debugging
Author: Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Workshop: 12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Pdf | Reference: pp. 47-56, Berlin, 2009
Equivalence Checking of Reversible Circuits
Author: Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Workshop: 12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: Berlin, 2009
Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow
Author: Ulrich Kühne, Daniel Große, Rolf Drechsler
Workshop: 9th International Workshop on Microprocessor Test and Verification (MTV)
Pdf | Reference: pp. 88-93, Austin, Texas, 2008
Computing Bounds for Fault Tolerance using Formal Techniques
Author: Andre Sülflow, Görschwin Fey, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Workshop: IEEE Workshop on Design for Reliability and Variability (DRV)
Pdf | Reference: Santa Clara, USA, 2008
Experimental Studies on SMT-based Debugging
Author: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: IEEE 9th Workshop on RTL and High Level Testing (WRTLT'08)
Pdf | Reference: pp. 93-98, Japan, 2008
Reversible Logic Synthesis with Output Permutation
Author: Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Workshop: International Workshop on Boolean Problems
Reference: Freiberg, 2008
Effiziente automatische Generierung von Assertions für industrielle Hardware-Designs
Author: Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
Workshop: Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
Reference: Dresden, 2008
Contradiction Analysis for Constraint-based Random Simulation
Author: Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Workshop: Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
Reference: pp. 25-30, Dresden, 2008
Robust Tests for Transition Faults with Long Propagation Paths Using Boolean Satisfiability
Author: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Workshop: IEEE European Test Symposium (ETS), Informal Digest of Papers
Pdf | Reference: Lago Maggiore, 2008
Targeting Leakage Constraints during ATPG
Author: Görschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita
Workshop: IEEE International Workshop on Silicon Debug and Diagnosis
Pdf | Reference: San Diego, 2008
Formale Modellextraktion von SystemC Entwürfen
Author: Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard
Workshop: edaWorkshop
Pdf | Reference: pp. 7-12, Hannover, 2008
Ad-Hoc Translations to Close Verilog Semantics Gap
Author: Christian Haufe, Frank Rogin
Workshop: 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Reference: Bratislava, 2008
Incremental SAT Instance Generation for SAT-based ATPG
Author: Daniel Tille, Rolf Drechsler
Workshop: 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Pdf | Reference: pp. 68-73, Bratislava, 2008
Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking
Author: Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Workshop: 11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: pp. 169-178, Freiburg, 2008
Debugging Design Errors by Using Unsatisfiable Cores
Author: Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Workshop: 11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Pdf | Reference: pp. 159-168, Freiburg, 2008
False Noise Analysis Using Branch & Bound and SAT
Author: Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
Workshop: ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU 2008)
Reference: Monterey, 2008
Improved Circuit-to-CNF Transformation for SAT-based ATPG
Author: Daniel Tille, René Krenz-Bååth, Jürgen Schlöffel, Rolf Drechsler
Workshop: 20. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
Pdf | Reference: Wien, 2008
Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
Author: Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler
Workshop: IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07)
Pdf | Reference: pp. 31-36, Beijing, P.R.China, 2007
Formal Robustness Checking
Author: Görschwin Fey, Rolf Drechsler
Workshop: Workshop on Constraints in Formal Verification, 2007
Pdf | Reference: Bremen, 2007
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
Author: Rolf Drechsler, Görschwin Fey, Jürgen Schlöffel
Workshop: edaWorkshop 2007
Reference: Hannover, 2007
On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-Micron Interconnects.
Author: Tudor Murgan, Petru Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner
Workshop: In Intl. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sept. 2007.
Reference: pp. 242-254, Göteborg, Sweden, 2007
Parallelisierung von SAT-basierter Testmustergenerierung
Author: Daniel Tille, Robert Wille, Rolf Drechsler
Workshop: 21. Workshop der GI/ITG-Fachgruppe Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS 2007)
Reference: pp. 213-217, Hamburg, 2007
Building Free Binary Decision Diagrams Using SAT Solvers
Author: Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop: 8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007)
Reference: Oslo, 2007
SAT-based ATPG for Path Delay Fault in Industrial Circuits
Author: Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel
Workshop: IEEE European Test Symposium (ETS), Informal Digest of Papers
Reference: Freiburg, 2007
Estimating the Quality of AND-EXOR Optimization Results
Author: Sebastian Kinder, Görschwin Fey and Rolf Drechsler
Workshop: 8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007)
Reference: Oslo, 2007
Documentation Driven Software Development for Embedded Systems
Author: Beate Muranko, Rolf Drechsler
Workshop: 14. Workshop der Fachgruppe WI-VM der Gesellschaft für Informatik e.V. Vorgehensmodelle und Projektmanagement - Assessment, Zertifizierung, Akkreditierung -
Pdf | Reference: München, 2007
Studies on Integrating SAT-based ATPG in an Industrial Environment
Author: Daniel Tille, Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Workshop: 19. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
Pdf | Reference: Erlangen, 2007
Instance Generation for SAT-based ATPG
Author: Daniel Tille, Görschwin Fey, Rolf Drechsler
Workshop: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Pdf | Reference: Krakau, 2007
Debug Patterns for Efficient High-level SystemC Debugging
Author: Frank Rogin, Erhard Fehlauer, Christian Haufe, Sebastian Ohnewald
Workshop: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Reference: Krakau, 2007
Visualized SystemC Debugging
Author: Christian Genz, Frank Rogin, Rolf Drechsler, Steffen Rülke
Workshop: University Booth at Design, Automation and Test in Europe (DATE07)
Pdf | Reference: Nizza, 2007
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
Author: Rolf Drechsler
Workshop: Treffen der ASIM/GI-Fachgruppen "Simulation technischer Systeme" und "Grundlagen und Methoden in Modellbildung und Simulation"
Reference: Bremen, 2007
Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse
Author: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: pp. 101-110, Erlangen, 2007
Formal Verification on the Word Level using SAT-like Proof Techniques
Author: Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference: pp. 165-173, Erlangen, 2007
Efficient Design-Flow for Counting Heads
Author: Sebastian Kinder und Rolf Drechsler
Workshop: 8. Bieleschweig Workshop „Systems Engineering”: Modellbasierte Entwicklung & Human-Centered Engineering
Pdf | Reference: Braunschweig, 2006
Exact Toffoli Network Synthesis of Reversible Logic using Boolean Satisfiability
Author: Daniel Große, Xiaobo Chen, Rolf Drechsler
Workshop: Fifth IEEE Dallas Circuits and Systems Workshop
Reference: pp. 51-54, Dallas, 2006
Complete Formal Verification of Multi Core Embedded Systems using Bounded Model Checking
Author: Ulrich Kühne, Daniel Große, Rolf Drechsler
Workshop: Fifth IEEE Dallas Circuits and Systems Workshop
Reference: pp. 147-150, Dallas, 2006
Efficiency of Multi-Valued Encoding in SAT-based ATPG
Author: Görschwin Fey, Junhao Shi , Rolf Drechsler
Workshop: 18. Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“
Reference: Titisee, 2006
Technische Dokumentation von Soft- und Hardware-Systemen: Die vergessene Welt
Author: Beate Muranko, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: Dresden, 2006
SAT-Based Calculation of Source Code Coverage for BMC
Author: Görschwin Fey, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: Dresden, 2006
Efficient Evolutionary Approaches for the Data Ordering Problem with Inversion
Author: Doina Logofatu, Rolf Drechsler
Workshop: 3rd European Workshop on Hardware Optimisation Techniques (EvoHOT)
Reference: LNCS 3907, pp. 320-331, Budapest, 2006
Finding Compact BDDs Using Genetic Programming
Author: Ulrich Kühne, Nicole Drechsler
Workshop: 3rd European Workshop on Evolutionary Computation in Hardware Optimisation (EvoHOT)
Pdf | Reference: LNCS 3907, pp. 308-319, Budapest, 2006
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking
Author: Daniel Große, Ulrich Kühne, Rolf Drechsler
Workshop: 6th International Workshop on Microprocessor Test and Verification (MTV'05)
Pdf | Reference: pp. 133-137, Austin, 2005
Bounded Model Checking mit SystemC
Author: Sebastian Kinder, Rolf Drechsler, Jan Peleska
Workshop: Bieleschweig 6 - Workshop "Systems Engineering"
Reference: Braunschweig, 2005
Bounded Model Checking of Tram Control Systems
Author: Sebastian Kinder, Daniel Große, Jan Peleska, Rolf Drechsler
Workshop: TRain Workshop @ SEFM2005
Reference: Koblenz, 2005
Formale Verifikation des Befehlssatzes eines in SystemC modellierten Mikroprozessors
Author: Daniel Große, Ulrich Kühne, Rolf Drechsler
Workshop: Entwurfsmethoden für Nanometer VLSI Design
Pdf | Reference: pp. 308-312, Bonn, 2005
On the Exact Minimization of Path-Related Objective Functions for BDDs
Author: Rüdiger Ebendt, Rolf Drechsler
Workshop: International Workshop on Logic and Synthesis (IWLS'05)
Pdf | Reference: pp. 333-400, Lake Arrowhead, California, 2005
Acceleration of SAT-based Iterative Property Checking
Author: Daniel Große, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: München, 2005
Modellierung eines Mikroprozessors in SystemC
Author: Daniel Große, Ulrich Kühne, Christian Genz, Frank Schmiedle, Bernd Becker, Rolf Drechsler, Paul Molitor
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: München, 2005
SyCE: An Integrated Environment for System Design in SystemC
Author: Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große
Workshop: 16th IEEE International Workshop on Rapid System Prototyping (RSP)
Pdf | Reference: pp. 258-260, Montreal, 2005
PASSAT: Efficient SAT-based Test Pattern Generation
Author: Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Workshop: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference: Sopron, 2005
Efficient Hierarchical System Debugging for Property Checking
Author: Görschwin Fey, Rolf Drechsler
Workshop: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Sopron, 2005
ParSyC: An Efficient SystemC Parser
Author: Görschwin Fey, Daniel Große, Tim Cassens, Christian Genz, Tim Warode, Rolf Drechsler
Workshop: 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004)
Pdf | Reference: pp. 148-154, Kanazawa, 2004
Design Understanding by Automatic Property Generation
Author: Rolf Drechsler, Görschwin Fey
Workshop: 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004)
Pdf | Reference: pp.274-281, Kanazawa, 2004
Debugging Sequential Circuits Using Boolean Satisfiability
Author: Moayad Ali, Andreas Veneris, Sean Safarpour, Magdy Abadir, Rolf Drechsler, Alexander Smith
Workshop: 5th International Workshop on Microprocessor Test and Verification (MTV'04)
Reference: Austin, 2004
Experimental Studies on Test Pattern Generation for BDD Circuits
Author: Junhao Shi, Görschwin Fey, Rolf Drechsler
Workshop: International Workshop on Boolean Problems (IWSBP)
Pdf | Reference: pp. 71-76, Freiberg, 2004
Towards Formal Verification on the System Level
Author: Rolf Drechsler
Workshop: 15th IEEE International Workshop on Rapid System Prototyping
Pdf | Reference: Invited Talk, pp. 2-5, Geneva, 2004
Visualization of Diagnosis Results for Design Debugging
Author: Görschwin Fey, Rolf Drechsler
Workshop: 13th International Workshop on Post-Binary ULSI Systems
Reference: pp. 1-2, Toronto, 2004
Disjoint Sum of Product Minimization by Evolutionary Algorithms
Author: Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler
Workshop: 1st European Workshop on Hardware Optimisation Techniques (EvoHOT)
Pdf | Reference: Applications of Evolutionary Computing: EvoWorkshops 2004, LNCS 3005, p. 198-207, Coimbra, 2004
Efficient (Non-)Reachability Analysis of Counterexamples
Author: Rolf Drechsler, Wolfgang Günther, Burkhard Stubert
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: pp. 250-259, Kaiserslautern, 2004
Using Synthesis Techniques in SAT Solvers
Author: Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: pp. 165-173, Kaiserslautern, 2004
A Tight Lower Bound for Dynamic BDD Minimization
Author: Rüdiger Ebendt, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference: pp. 233-242, Kaiserslautern, 2004
An Approach to Formal Verification of Reconfigurable Systems
Author: Görschwin Fey, Rolf Drechsler, Muazzam Ali
Workshop: 1st IFIP WG 10.5 Workshop on "Frontiers in Automotive Electronics"
Reference: Darmstadt, 2003
BDD-Based Verification of Scalable Designs
Author: Daniel Große, Rolf Drechsler
Workshop: IEEE International High Level Design Validation and Test Workshop (HLDVT'2003)
Pdf | Reference: pp. 123-128, San Francisco, 2003
Random Pattern Testability of Circuits Derived from BDDs
Author: Junhao Shi, Göschwin Fey and Rolf Drechsler
Workshop: 4th Workshop on RTL and High Level Testing(WRTLT'03)
Pdf | Reference: p.70-78, Xi'an, 2003
Synthesizing Checkers for On-line Verification of System-on-Chip Designs
Author: Rolf Drechsler
Workshop: GI/GMM/ITG Fachtagung Entwurf Integrierter Schaltungen (11. E.I.S.-Workshop)
Reference: Erlangen, 2003, page 69, 2003
BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
Author: Junhao Shi, Görschwin Fey and Rolf Drechsler
Workshop: IEEE European Test Workshop (ETW'03)
Pdf | Reference: pp. 109-110, Maastricht, 2003, 2003
MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits
Author: Rolf Drechsler
Workshop: 15th ITG/GMM/GI Workshop Test methods and Reliability of Circuits and Systems
Reference: Timmendorfer Strand, 2003
BDD Circuit Optimization for Path Delay Fault-Testability
Author: Görschwin Fey, Junhao Shi, Rolf Drechsler
Workshop: 15th ITG/GMM/GI Workshop Test methods and Reliability of Circuits and Systems
Reference: Timmendorfer Strand, 2003 , 2003
A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization
Author: Görschwin Fey, Rolf Drechsler
Workshop: 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2003)
Reference: pp. 54-60, Hiroshima , 2003
GAME-HDL: Implementation of Evolutionary Algorithms using Hardware Description Languages
Author: Rolf Drechsler, Nicole Drechsler
Workshop: 5th European Workshop on Evolutionary Computation in Image Analysis and Signal Processing (EvoIASP2003)
Pdf | Reference: LNCS 2611, pp. 378-387, Colchester, 2003
Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen
Author: Daniel Große, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: pp. 229-238, Bremen, 2003
Cost-efficient Formal Block Verification for ASIC Design
Author: K. Winkelmann, J. Trylus, D. Stoffel, Görschwin Fey
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: pp. 184-188, Bremen, 2003
Complete BDDs for Fast and Efficient Equivalence Checking, In Workshop on Computational Intelligence and Information Technologies
Author: Rolf Drechsler
Workshop: XXXVII International Scientific Conference on Information Communication and Energy Systems and Technologies (ICEST 2002)
Reference: pp. 741-744, Nis, 2002
Gatecomp: Equivalence Checking of Digital Circuits in an Industrial Environment
Author: Rolf Drechsler, Stefan Höreth
Workshop: International Workshop on Boolean Problems
Pdf | Reference: pp. 195-200, Freiberg, 2002
Minimizing the Number of Paths in BDDs
Author: Görschwin Fey, Rolf Derchsler
Workshop: International Workshop on Boolean Problems
Pdf | Reference: pp. 149 - 156, Freiberg, 2002
Low Power Optimization Technique for BDD Mapped Finite State Machines
Author: M. Kerttu, P. Lindgren, Rolf Drechsler, M. Thornton
Workshop: International Workshop on Logic Synthesis (IWLS'2002)
Reference: New Orleans, 2002
Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation
Author: Rolf Drechsler, M. Kerttu, P. Lindgren, M. Thornton
Workshop: International Workshop on System-on-Chip for Real-Time Applications 2002
Reference: Banff, 2002
Symbolic Simulation of Algorithms Specified in HDL
Author: Klaus-Jürgen Englert, Bernd Becker, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: pp. 113 - 122, Tübingen, 2002
Implementation and Visualization of a BDD Package in JAVA
Author: Rolf Drechsler, Jochen Römmler
Workshop: GI/ITG/GMM-Workshop 2002, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: pp. 219 - 228, Tübingen, 2002

288 Papers




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