Authors
Görschwin Fey, Rolf Drechsler
ISBN 978-1-4020-6535-4
Ordering:
Book Summary:
The size of technically producible integrated circuits increases continuously. But the ability to
design and verify these circuits does not keep up with this development. Therefore today's design
flow has to be improved to achieve a higher productivity. In this book the current design methodology
and verification methodology are analyzed, a number of deficiencies are identified and solutions
suggested. Improvements in the methodology as well as in the underlying algorithms are proposed.
An in-depth presentation of preliminary concepts makes the book self-contained. Based on this
foundation, major design problems are targeted. In particular, a complete tool flow for Synthesis
for Testability of SystemC descriptions is presented. The resulting circuits are completely
testable and test pattern generation in polynomial time is possible. Verification issues are
covered in even more detail. A whole new paradigm for formal design verification is suggested.
This is based upon design understanding, the automatic generation of properties and powerful tool
support for debugging failures. All these new techniques are empirically evaluated and experimental
results are provided.
As a result, an enhanced design flow is created that provides more automation
(i.e. better usability) and reduces the probability of introducing conceptual errors (i.e.
higher robustness).
Authors:
Görschwin Fey received his Diploma in Computer Science from the Martin-Luther Universität,
Halle-Wittenberg, Germany in 2001. Since then he has been with the research group of computer
architecture at the University of Bremen, where he received the Dr. degree in 2006.
He is also with the VLSI Design & Education Center (VDEC) at the University of Tokyo during 2007
and 2008 as a visiting professor. His research interests are in testing and formal verification
of circuits and systems.
Rolf Drechsler received his diploma and Dr. phil. nat. degree in computer science from the J.W.
Goethe-University in Frankfurt am Main, Germany, in 1992 and 1995, respectively. He was with the
Institute of Computer Science at the Albert-Ludwigs-University of Freiburg im Breisgau, Germany
from 1995 to 2000. He joined the Corporate Technology Department of Siemens AG, Munich in 2000,
where he worked as a Senior Engineer in the formal verification group. Since October 2001 he has
been with the University of Bremen, Germany, where he is now a full professor for computer
architecture. His research interests include data structures logic synthesis, test, and
verification.
