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Group of Computer Architecture / AGRA | Computer Science | Faculty 03 | University of Bremen
Only available in German

Digital Systems Modeling using Verilog and SystemVerilog: Design, Test and Synthesis
G | 03-BE-701.07

(in englischer Sprache) Themen:
  • Digital systems design using Verilog
  • HDL simulation
  • Building robust testbenches using SystemVerilog
  • Good practices in Digital systems verification using SVA
  • Basic static timing analysis and HW optimization
  • Importance of synthesis concept

Prof. Dr. Rolf Drechsler, Dr. Mehran Goli

Ort & Zeit:
Mo 10-12 Uhr

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