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Arbeitsgruppe Rechnerarchitektur / AGRA | Informatik | FB03 | Universität Bremen
Digital Systems Modeling and Verification using SystemVerilog

(in englischer Sprache)

SystemVerilog is the industry's first Hardware Description and Verification Language (HDVL) as it combines the features of HDLs such as Verilog and VHDL with features from specialized Hardware Verification Languages, together with features from C and C++.
SystemVerilog has become the dominant language standard for functional verification in the industry. It significantly enhances the capabilities of Verilog in a number of areas, offering productivity improvements for RTL designers, assertions, and constrained random stimulus generation for verification engineers.


  • Overviewing the RTL design methodology
  • Introducing the new data types, array types, and structs in testbenches
  • Layered testbenches methodology using OOP techniques
  • SystemVerilog constrained randomization to testbench stimulus generation
  • Applying functional coverage to evaluate the quality of the testbench
  • Assertion-based verification using SystemVerilog Assertion (SVA)
  • Binding assertions to a DUT without modifying the DUT

Prof. Dr. Rolf Drechsler, Dr. Mehran Goli

Ort & Zeit:
Mo 10-12 Uhr MZH 1450

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