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Konferenzen


From Bugs to Fixes: HDL Bug Identification and Patching using LLMs and RAG
Autor: Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler
Konferenz: LLM-Aided Design, 2024 (LAD)
Referenz: San Jose, CA, USA, 2024
EvoAl — Codeless Domain-Optimisation
Autor: Bernhard J. Berger, Christina Plump, Lauren Paul, Rolf Drechsler
Konferenz: GECCO Companion
Pdf | Referenz: Melbourne, Australia, 2024
Finding the perfect MRI sequence for your patient --- Towards an optimisation workflow for MRI-sequences
Autor: Christina Plump, Daniel C. Hoinkiss, Jörn Huber, Bernhard J. Berger, Matthias Günther, Christoph Lüth, Rolf Drechsler
Konferenz: CEC 2024, at IEEE WCCI 2024
Pdf | Referenz: Yokohama, Japan, 2024
Is Simulation the Only Alternative for Effective Verification of Dynamic Quantum Circuits?
Autor: Liam Hurwitz, Kamalika Datta, Abhoy Kole, Rolf Drechsler
Konferenz: International Conference on Reversible Computation (RC)
Referenz: Torun, Poland, 2024
Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification
Autor: Khushboo Qayyum, Abhoy Kole, Kamalika Datta, Muhammad Hassan, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: Tempa Bay Area, Florida, USA , 2024
Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification
Autor: Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2024
Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent
Autor: Kemal Çağlar Coşkun, Muhammad Hassan, Lars Hedrich, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2024
Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences
Autor: Jan Zielasko, Rune Krauss, Marcel Merten, Rolf Drechsler
Konferenz: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Kielce, Poland, 2024
Polynomial Formal Verification of Approximate Adders with Constant Cutwidth
Autor: Mohamed Nadeem, Chandan Kumar Jha, Rolf Drechsler
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: The Hague, Netherlands, 2024
Polynomial Formal Verification of Multi-Valued Logic Circuits within Constant Cutwidth Architectures
Autor: Mohamed Nadeem, Rolf Drechsler
Konferenz: IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Brno, Czech Republic, 2024
Polynomial Formal Verification of Sequential Circuits
Autor: Caroline Dominik, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Valencia, Spain, 2024
Hidden Cost of Circuit Design with RFETs
Autor: Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Valencia, Spain, 2024
LLM-guided Formal Verification Coupled with Mutation Testing
Autor: Muhammad Hassan, Sallar Ahmadi-Pour, Khushboo Qayyum, Chandan Kumar Jha, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Valencia, Spain, 2024
Dynamic Realization of Multiple Control Toffoli Gate
Autor: Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Valencia, Spain, 2024
Complete and Efficient Verification for a RISC-V Processor using Formal Verification
Autor: Lennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Valencia, Spain, 2024
In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures
Autor: Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta and Rolf Drechsler
Konferenz: International Conference on VLSI Design (VLSID)
Pdf | Referenz: Kolkata, India, 2024
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array
Autor: Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana
Konferenz: International Conference on VLSI Design (VLSID)
Pdf | Referenz: Kolkata, India, 2024
Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic
Autor: Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler
Konferenz: International Conference on VLSI Design (VLSID)
Pdf | Referenz: Kolkata, India, 2024
A Dynamic Programming Based Graph Traversal Approach for Efficient Implementation of Nearest Neighbor Architecture in 2D
Autor: Sneha Lahiri, Megha Kesh, Rupsa Mandal, Sovan Bhattacharya, Anirban Bhattacharjee, Dola Sinha, Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler, Robert Wille
Konferenz: International Conference on VLSI Design (VLSID)
Referenz: Kolkata, India, 2024
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory
Autor: Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin Patkar, Rolf Drechsler, Farhad Merchant
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Referenz: Incheon Songdo Convensia, South Korea, 2024
Security Coverage Metrics for Information Flow at the System Level
Autor: Ece Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Incheon Songdo Convensia, South Korea, 2024
Energy-Efficient CNN inferencing on GPUs with Dynamic Frequency Scaling
Autor: Rolf Drechsler, Christopher Metz, und Christina Plump
Konferenz: International Conference on Innovations in Data Analytics (ICIDA)
Pdf | Referenz: West Bengal, India, 2023
PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor
Autor: Lennart Weingarten, Kamalika Datta, Rolf Drechsler
Konferenz: ACM International Symposium on Nanoscale Architectures (NANOARCH)
Referenz: Dresden, Germany, 2023
Memristors: Device Modeling, Design and Verification
Autor: Kamalika Datta, Rolf Drechsler
Konferenz: IEEE International Symposium on Smart Electronic Systems (iSES)
Referenz: Ahmedabad, India, 2023
Automated Polynomial Formal Verification: Human-Readable Proof Generation
Autor: Rolf Drechsler, Martha Schnieber
Konferenz: IEEE International Symposium on Smart Electronic Systems (iSES)
Pdf | Referenz: Ahmedabad, India, 2023
Aktuelle Entwicklungen und Perspektiven (an Hochschulen) im Bereich Data Science
Autor: Lena Steinmann, Dirk Nowotka, Lea Oberländer , Helen Pfuhl, Heiner Stuckenschmidt, Rolf Drechsler
Konferenz: INFORMATIK 2023
Referenz: Berlin, Deutschland, 2023
Das Data Science Center an der Universität Bremen: Interdisziplinärer Knotenpunkt und Service-Infrastruktur für die datenintensive Forschung
Autor: Lena Steinmann, Heike Thöricht, Sandra Zänkert, Rolf Drechsler
Konferenz: E-Science-Tage 2023
Pdf | Referenz: Heidelberg, Deutschland, 2023
Data Train – The Cross-disciplinary Training in Research Data Management and Data Science
Autor: Tanja Hörner, Maya Dalby, Rolf Drechsler, Frank Oliver Glöckner, Iris Pigeot
Konferenz: International Conference for YOUNG Marine Researchers (ICYMARE)
Referenz: Oldenburg, Germany, 2023
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style
Autor: Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin Patkar, Rolf Drechsler, Farhad Merchant
Konferenz: International Conference on Hardware/Software Codesign and System Synthesis | Embedded System Week (CODES+ISSS)
Pdf | Referenz: Hamburg, Germany, 2023
Virtual Prototypes and Open Source Hardware Design in Research and Education
Autor: Sallar Ahmadi-Pour, Rolf Drechsler
Konferenz: The premier open source silicon conference (ORConf)
Referenz: Munich, Germany, 2023
RADOPA: Robustifying a Design Against Optical Probing Attacks
Autor: Sajjad Parvin, Rolf Drechsler
Konferenz: The premier open source silicon conference (ORConf)
Referenz: Munich, Germany, 2023
RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan Networks
Autor: Payam Habiby, Sebastian Huhn, Rolf Drechsler
Konferenz: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Referenz: Juan-Les-Pins, France, 2023
Efficient ML-Based Performance Estimation Approach across Different Microarchitectures for RISC-V Processors
Autor: Weiyan Zhang, Mehran Goli, Muhammad Hassan, Rolf Drechsler
Konferenz: Euromicro Conference Series on Digital System Design (DSD)
Pdf | Referenz: Durres, Albania, 2023
Polynomial Formal Verification of KFDD Circuits
Autor: Martha Schnieber, Rolf Drechsler
Konferenz: International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Referenz: Hamburg, Germany, 2023
Next-Generation Automatic Human-Readable Proofs Enabling Polynomial Formal Verification
Autor: Rolf Drechsler, Martha Schnieber
Konferenz: International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Referenz: Hamburg, Germany, 2023
Hidden in Plain Sight: A Detailed Investigation of Selectively Increasing Local Density to Camouflage and Robustify Against Optical Probing Attacks
Autor: Sajjad Parvin, Chandan Kumar Jha, Sallar Ahmadi-Pour, Frank Sill Torres, and Rolf Drechsler
Konferenz: IEEE International Test Conference India (ITC India)
Pdf | Referenz: Bengaluru, India, 2023
Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core
Autor: Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler
Konferenz: IEEE INTERNATIONAL CONFERENCE ON OMNI-LAYER INTELLIGENT SYSTEMS (IEEE COINS)
Pdf | Referenz: Berlin, Germany, 2023
Hybrid PTX Analysis for GPU accelerated CNN inferencing aiding Computer Architecture Design
Autor: Christopher Metz, Christina Plump, Bernhard J. Berger, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Turin, Italy, 2023
Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models
Autor: Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Turin, Italy, 2023
Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification
Autor: Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Turin, Italy, 2023
Virtual Prototype driven Application Specific Hardware Optimization
Autor: Jan Zielasko, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Turin, Italy, 2023
LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing
Autor: Sajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Iguazu Falls, Brazil, 2023
Versatile and Flexible Modelling of the RISC-V Instruction Set Architecture
Autor: Sören Tempel, Tobias Brandt, Christoph Lüth
Konferenz: 24th International Symposium on Trends in Functional Programming (TFP)
Pdf | Referenz: UMass Boston, Boston, MA, USA, 2023
EvoAl: A domain-specific language-based approach to optimisation
Autor: Bernhard J. Berger, Christina Plump, Rolf Drechsler
Konferenz: IEEE 2023 Congress on Evolutionary Computation (CEC)
Referenz: Chicago, 2023
Verification of In-Memory Logic Design Using ReRAM Crossbars
Autor: Kamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler
Konferenz: IEEE Interregional NEWCAS Conference (NEWCAS)
Pdf | Referenz: Edinburgh, Scotland, 2023
Finite State Automata Design using 1T1R ReRAM Crossbar
Autor: Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad Shafik, Alex Yakovlev, Sachin Patkar, Farhad Merchant
Konferenz: IEEE Interregional NEWCAS Conference (NEWCAS)
Pdf | Referenz: Edinburgh, Scotland, 2023
Benchmarking Multiplier Architectures for MAGIC Based In-Memory Computing
Autor: Chandan Kumar Jha, Rolf Drechsler
Konferenz: IEEE Interregional NEWCAS Conference (NEWCAS)
Pdf | Referenz: Edinburgh, Scotland, 2023
Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures
Autor: Abhoy Kole, Kamalika Datta, Philipp Niemann, Indranil Sengupta and Rolf Drechsler
Konferenz: International Conference on Reversible Computation (RC)
Pdf | Referenz: Giessen, Germany, 2023
Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture
Autor: Kamalika Datta, Abhoy Kole, Indranil Sengupta and Rolf Drechsler
Konferenz: International Conference on Reversible Computation (RC)
Pdf | Referenz: Giessen, Germany, 2023
Scalable Neuroevolution of Ensemble Learners
Autor: Marcel Merten, Rune Krauss, Rolf Drechsler
Konferenz: The Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Referenz: Lisbon, Portugal, 2023
Repetitive Processes and their surrogate-model congruent encoding for evolutionary algorithms - A theoretic proposal
Autor: Christina Plump, Bernhard J. Berger, Rolf Drechsler
Konferenz: The Genetic and Evolutionary Computation Conference (GECCO)
Referenz: Lisbon, Portugal, 2023
Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes
Autor: Rune Krauss, Mehran Goli, Rolf Drechsler
Konferenz: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Tallinn, Estonia, 2023
Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques
Autor: Marcel Merten, Muhammad Hassan, Rolf Drechsler
Konferenz: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Tallinn, Estonia, 2023
Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips
Autor: Payam Habiby, Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich, Sebastian Huhn, Rolf Drechsler
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Venice, Italy, 2023
Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods
Autor: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Venice, Italy, 2023
VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking
Autor: Ece Nur Demirhan Coskun, Muhammad Hassan, Mehran Goli, Rolf Drechsler
Konferenz: International Symposium on Quality Electronic Design (ISQED'23)
Pdf | Referenz: San Francisco, USA, 2023
Polynomial Formal Verification of a Processor: A RISC-V Case Study
Autor: Lennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler
Konferenz: International Symposium on Quality Electronic Design (ISQED'23)
Pdf | Referenz: San Francisco, USA, 2023
A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin
Autor: Daniel Tille, Leon Klimasch, Sebastian Huhn
Konferenz: 41st IEEE VLSI Test Symposium (VTS)
Pdf | Referenz: San Diego, USA, 2023
Coverage-guided Fuzzing for Plan-based Robotics
Autor: Tim Meywerk, Vladimir Herdt, Rolf Drechsler
Konferenz: 15th International Conference on Agents and Artificial Intelligence (ICAART)
Pdf | Referenz: Lissabon, Portugal, 2023
Polynomial Formal Verification of Floating Point Adders
Autor: Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Antwerp, Belgium, 2023
Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors
Autor: Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed E. Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, Violetta Sessi, Maximilian Drescher, Sabine Kolodinski and Maciej Wiatr
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Antwerp, Belgium, 2023
Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex Circuits
Autor: Rolf Drechsler, Alireza Mahzoon
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Antwerp, Belgium, 2023
Analysis of Quantization Across DNN Accelerator Architecture Paradigms
Autor: Tom Glint, Chandan Kumar Jha, Manu Awasthi and Joycee Mekie
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Antwerp, Belgium, 2023
Processor Verification using Symbolic Execution: A RISC-V Case-Study
Autor: Niklas Bruns, Vladimir Herdt, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Antwerp, Belgium, 2023
Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits
Autor: Kemal Çağlar Coşkun, Muhammad Hassan, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Antwerp, Belgium, 2023
FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing
Autor: Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Antwerp, Belgium, 2023
Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network
Autor: Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Antwerp, Belgium, 2023
Automated Equivalence Checking Method for Majority based In-Memory Computing on ReRAM Crossbars
Autor: Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Tokyo, Japan, 2023
Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - a RISC-V Case Study
Autor: Sajjad Parvin, Mehran Goli, Frank Sill Torres, and Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Tokyo, Japan, 2023
EDDY: A Multi-Core BDD Package With Dynamic Memory Management and Reduced Fragmentation
Autor: Rune Krauss, Mehran Goli, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Tokyo, Japan, 2023
A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS
Autor: Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große
Konferenz: Design and Verification Conference in Europe (DVCon Europe)
Pdf | Referenz: Munich, Germany, 2022
Symbolic Fault Injection for Plan-based Robotics
Autor: Tim Meywerk, Vladimir Herdt, Rolf Drechsler
Konferenz: The 22nd International Conference on Control, Automation and Systems (ICCAS)
Pdf | Referenz: Busan, Korea, 2022
Investigating Various Adder Architectures for Digital In-Memory Computing Using MAGIC-based Memristor Design Style
Autor: Chandan Kumar Jha, Alireza Mahzoon, Rolf Drechsler
Konferenz: International Conference on Emerging Electronics (ICEE)
Pdf | Referenz: Bangalore, India, 2022
Monitoring the Effects of Static Variable Orders on the Construction of BDDs
Autor: Khushboo Qayyum, Alireza Mahzoon, Rolf Drechsler
Konferenz: International Interdisciplinary Conference on Mathematics, Engineering and Science (MESIICON)
Pdf | Referenz: Virtual Conference, 2022
Polynomial Formal Verification: Ensuring Correctness under Resource Constraints
Autor: Rolf Drechsler, Alireza Mahzoon
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: San Diego, USA, 2022
Divider Verification Using Symbolic Computer Algebra and Delayed Don’t Care Optimization
Autor: Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler
Konferenz: Formal Methods in Computer-Aided Design (FMCAD)
Pdf | Referenz: Trento, Italy, 2022
Preserving Design Hierarchy Information for Polynomial Formal Verification
Autor: Rolf Drechsler, Alireza Mahzoon
Konferenz: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Pdf | Referenz: Patras, Greece, 2022
Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications
Autor: Kamalika Datta, Saman Froehlich, Saeideh Shirinzadeh, Dev Narayan, Yadav Indranil Sengupta and Rolf Drechsler
Konferenz: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Pdf | Referenz: Patras, Greece, 2022
Fast and Exact is Doable: Polynomial Algorithms in Test and Verification
Autor: Rolf Drechsler
Konferenz: IEEE Latin-American Test Symposium (LATS)
Pdf | Referenz: Virtual Conference, 2022
Design Modification for Polynomial Formal Verification
Autor: Rolf Drechsler, Alireza Mahzoon
Konferenz: 2022 International Symposium on Electrical, Electronics and Information Engineering (ISEEIE)
Pdf | Referenz: Virtual Conference, 2022
Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency Scaling
Autor: Christopher Metz, Mehran Goli, Rolf Drechsler
Konferenz: ACM/IEEE Workshop on Machine Learning for CAD (MLCAD)
Pdf | Referenz: Snowbird, USA, 2022
Next Generation Design For Testability, Debug and Reliability Using Formal Techniques
Autor: Sebastian Huhn and Rolf Drechsler
Konferenz: International Test Conference (ITC)
Pdf | Referenz: Anaheim, CA, USA, 2022
Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device
Autor: Alexander Fratzer, Vladimir Herdt, Christoph Lüth, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Linz, Austria, 2022
Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification
Autor: Niklas Bruns, Vladimir Herdt, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Linz, Austria, 2022
3D Visualization of Symbolic Execution Traces
Autor: Jan Zielasko, Sören Tempel, Vladimir Herdt, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Linz, Austria, 2022
SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification
Autor: Sören Tempel, Vladimir Herdt and Rolf Drechsler
Konferenz: Automated Technology for Verification and Analysis (ATVA)
Pdf | Referenz: Beijing, China, 2022
Simulation-Based Debugging of Formal Environment Models
Autor: Tim Meywerk, Arthur Niedzwiecki, Vladimir Herdt and Rolf Drechsler
Konferenz: The 30th Mediterranean Conference on Control and Automation (MED)
Pdf | Referenz: Athen, Griechenland, 2022
AQuCiDe: Architecture Aware Quantum Circuit Decomposition
Autor: Soumya Sengupta, Abhoy Kole, Kamalika Datta, Indranil Sengupta and Rolf Drechsler
Konferenz: 2022 International Symposium on Quantum Computing: Circuits Systems Automation and Applications (QC-CSAA)
Pdf | Referenz: Knoxville, USA, 2022
Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study
Autor: Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler and Klaus McDonald-Maier
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Gran Canaria, Spain, 2022
Generation of Verified Programs for In-Memory Computing
Autor: Saman Froehlich and Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Gran Canaria, Spain, 2022
Polynomial Formal Verification of Approximate Adders
Autor: Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Gran Canaria, Spain, 2022
SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library
Autor: Abhoy Kole, Kamalika Datta, Indranil Sengupta and Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Gran Canaria, Spain, 2022
Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles
Autor: Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta and Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Gran Canaria, Spain, 2022
Polynomial Formal Verification of Approximate Functions
Autor: Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Pafos, Cyprus, 2022
Using density of training data to improve evolutionary algorithms with approximative fitness functions
Autor: Christina Plump, Bernhard J. Berger, Rolf Drechsler
Konferenz: Congress of Evolutionary Computation (CEC)
Pdf | Referenz: Padua, Italien, 2022
Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype
Autor: Pascal Pieper, Vladimir Herdt, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Referenz: Irvine, CA, USA, 2022
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
Autor: Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: Irvine, CA, USA, 2022
Adapting mutation and recombination operators to range-aware relations in real-world application data
Autor: Christina Plump, Bernhard J. Berger, Rolf Drechsler
Konferenz: The Genetic and Evolutionary Computation Conference (GECCO Companion)
Referenz: Boston, USA, 2022
Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal Qubit Architecture
Autor: Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler
Konferenz: IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Virtual Conference, Dallas, 2022
Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic
Autor: Philipp Niemann, Rolf Drechsler
Konferenz: IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Dallas, USA, 2022
Formal Verification of Modular Multipliers using Symbolic Computer Algebra and Boolean Satisfiability
Autor: Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2022
Verifying SystemC TLM Peripherals using Modern C++ Symbolic Execution Tools
Autor: Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2022
Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters
Autor: Kemal Çağlar Coşkun, Muhammad Hassan, Rolf Drechsler
Konferenz: 25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Prague, Czech Republic, 2022
Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression
Autor: Weiyan Zhang, Mehran Goli, Rolf Drechsler
Konferenz: 25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Prague, Czech Republic, 2022
Towards Polynomial Formal Verification of Complex Arithmetic Circuits
Autor: Rolf Drechsler, Alireza Mahzoon, Mehran Goli
Konferenz: 25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Prague, Czech Republic, 2022
Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions
Autor: Milan Funck, Vladimir Herdt, Rolf Drechsler
Konferenz: 25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Prague, Czech Republic, 2022
ML-based Power Estimation of Convolutional Neural Networks on GPGPUs
Autor: Christopher Metz, Mehran Goli, Rolf Drechsler
Konferenz: 25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Prague, Czech Republic, 2022
Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods
Autor: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Barcelona, Spain, 2022
Choosing the right technique for the right restriction - a domain-specific approach for enforcing search-space restrictions in evolutionary algorithms
Autor: Christina Plump, Bernhard Berger, Rolf Drechsler
Konferenz: LDIC-2022
Pdf | Referenz: Bremen, Germany
A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection
Autor: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Konferenz: 40th IEEE VLSI Test Symposium (VTS)
Pdf | Referenz: San Diego, USA, 2022
The Scale4Edge RISC-V Ecosystem
Autor: Wolfgang Ecker, Milos Krstic, Andreas Mauderer, Eyck Jentzsch, Mihaela Damian, Julian Oppermann, Andreas Koch, Peer Adelt, Wolfgang Müller, Vladimir Herdt, Rolf Drechsler, Rafael Stahl, Karsten Emrich, Daniel Müller-Gritschneder, Jan Schlamelcher, Kim Grüttner, Jörg Bormann, Wolfgang Kunz, Reinhold Heckmann, Gerhard Angst, Ralf Wimmer, Bernd Becker, Philipp Scholl, Paul Palomero Bernardo, Oliver Bringmann, Johannes Partzsch, Christian Mayr
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Antwerp, Belgium, 2022
Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
Autor: Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Antwerp, Belgium, 2022
LiM-HDL: HDL-Based Synthesis for In-Memory Computing
Autor: Saman Fröhlich, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Antwerp, Belgium, 2022
Polynomial Formal Verification of Arithmetic Circuits
Autor: Rolf Drechsler, Alireza Mahzoon, Lennart Weingarten
Konferenz: International Conference on Computational Intelligence and Data Engineering (ICCIDE)
Pdf | Referenz: Vijayawada, India, 2021
Polynomial Word-Level Verification of Arithmetic Circuits
Autor: Mohammed Barhoush, Alireza Mahzoon, Rolf Drechsler
Konferenz: International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Referenz: Beijing, China, 2021
Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques
Autor: Sajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres and Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Taipei, Taiwan, 2022
Automated Detection of Spatial Memory Safety Violations for Constrained Devices
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Taipei, Taiwan, 2022
Modeling for Explainability: Ethical Decision-Making in Automated Resource Allocation
Autor: Christina Cociancig, Christoph Lüth, Rolf Drechsler
Konferenz: Upper-Rhine Artificial Intelligence Symposium (UR-AI 2021)
Pdf | Referenz: Kaiserslautern, Germany, 2021
Polynomial Formal Verification of Prefix Adders
Autor: Alireza Mahzoon, Rolf Drechsler
Konferenz: Asian Test Symposium (ATS)
Pdf | Referenz: Virtual Conference, Japan, 2021
A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks
Autor: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Konferenz: 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Referenz: Athens, Greece, 2021
Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs
Autor: Mehran Goli, Rolf Drechsler
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: Munich, Germany, 2021
Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level
Autor: Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Pdf | Referenz: Virtual Conference, Singapore, 2021
RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems
Autor: Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Antibes, France, 2021
VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes
Autor: Mehran Goli, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Antibes, France, 2021
Best Paper Award
In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Antibes, France, 2021
Work-in-Progress: Early Power Estimation of CUDA-based CNNs on GPGPUs
Autor: Christopher Metz, Mehran Goli, Rolf Drechsler
Konferenz: International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
Pdf | Referenz: VIRTUAL CONFERENCE, 2021
Minimally Invasive HW/SW Co-debug Live Visualization on Architecture Level
Autor: Pascal Pieper, Ralf Wimmer, Gerhard Angst, Rolf Drechsler
Konferenz: 31st ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: Virtual Conference, 2021
Finding Optimal Implementations of Non-native CNOT Gates using SAT
Autor: Philipp Niemann, Luca Müller, Rolf Drechsler
Konferenz: Reversible Computation (RC)
Pdf | Referenz: Nagoya, Japan, 2021
Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation
Autor: Philipp Niemann, Luca Müller, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Palermo, Sicily, Italy, 2021
Automated Debugging-Aware Visualization Technique for SystemC HLS Designs
Autor: Mehran Goli, Alireza Mahzoon, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Palermo, Sicily, Italy, 2021
ALF – A Fitness-Based Artificial Life Form for Evolving Large-Scale Neural Networks
Autor: Rune Krauss, Marcel Merten, Mirco Bockholt, Rolf Drechsler
Konferenz: The Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Referenz: Lille, France, 2021
Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability
Autor: Payam Habiby, Sebastian Huhn, Rolf Drechsler
Konferenz: 28th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
Pdf | Referenz: Apulia, Italy, 2021
Synthesis of Asymptotically Optimal Adders for Multiple-Valued Logic
Autor: Philipp Niemann, Rolf Drechsler
Konferenz: 51st International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Video | Referenz: Nursultan, Kazakhstan, 2021
Depth Optimized Synthesis of Symmetric Boolean Functions
Autor: Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Tampa, Florida, USA, 2021
Domain-driven correlation-aware recombination and mutation operators for complex real-world applications
Autor: Christina Plump, Bernhard J. Berger, Rolf Drechsler
Konferenz: IEEE Congress on Evolutionary Computation (CEC)
Pdf | Referenz: Kraków, Poland, 2021
Improving evolutionary algorithms by enhancing an approximative fitness function through prediction intervals
Autor: Christina Plump, Bernhard J. Berger, Rolf Drechsler
Konferenz: IEEE Congress on Evolutionary Computation (CEC)
Pdf | Referenz: Krakow, Poland, 2021
PolyAdd: Polynomial Formal Verification of Adder Circuits
Autor: Rolf Drechsler
Konferenz: 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Vienna, Austria, 2021
Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2021
Late Breaking Results: Polynomial Formal Verification of Fast Adders
Autor: Alireza Mahzoon, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2021
XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding
Autor: Lucas Klemmer, Saman Fröhlich, Rolf Drechsler, Daniel Große
Konferenz: IEEE International Symposium on Circuits & Systems (ISCAS)
Pdf | Referenz: Daegu, Korea, 2021
Performance Aspects of Correctness-oriented Synthesis Flows
Autor: Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Konferenz: Int’l Conf. on Model-Driven Engineering and Software Development (MODELSWARD)
Pdf | Referenz: 2021
Vertical IP Protection of the Next-Generation Devices: Quo Vadis?
Autor: Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Grenoble, France, 2021
Nano Security: From Nano-Electronics to Secure Systems
Autor: Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Grenoble, France, 2021
Combining SWAPs and Remote Toffoli Gates in the Mapping to IBM QX Architectures
Autor: Philipp Niemann, Chandan Bandyopadhyay, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Grenoble, France, 2021
Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization
Autor: Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Grenoble, France, 2021
An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Grenoble, France, 2021
System Level verification of Phase-Locked Loop using Metamorphic Relations
Autor: Muhammad Hassan, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Grenoble, France, 2021
ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs
Autor: Mehran Goli, Rolf Drechsler
Konferenz: 26th Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Tokyo, Japan, 2021
One-pass Synthesis for Field-coupled Nanocomputing Technologies
Autor: Marcel Walter, Winston Haaswijk, Robert Wille, Frank Sill Torres, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Tokyo, Japan, 2021
Best Paper Candidate
System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations
Autor: Muhammad Hassan, Daniel Große, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Tokyo, Japan, 2021
Mutation-based Compliance Testing for RISC-V
Autor: Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Tokyo, Japan, 2021
Clustering-Guided SMT(LRA) Learning
Autor: Tim Meywerk, Marcel Walter, Daniel Große, Rolf Drechsler
Konferenz: International Conference on integrated Formal Methods (iFM)
Pdf | Referenz: Lugano, Switzerland, 2020
Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime
Autor: Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
Konferenz: 38th IEEE International Conference on Computer Design (ICCD)
Pdf | Referenz: Hartford, USA, 2020
ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique
Autor: Mehran Goli, Alireza Mahzoon, Rolf Drechsler
Konferenz: 38th IEEE International Conference on Computer Design (ICCD)
Pdf | Referenz: Hartford, USA, 2020
Verifying Safety Properties of Robotic Plans operating in Real-World Environments via Logic-based Environment Modeling
Autor: Tim Meywerk, Marcel Walter, Vladimir Herdt, Jan Kleinekathöfer, Daniel Große, Rolf Drechsler
Konferenz: 9th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation (ISoLA)
Pdf | Referenz: Rhodes, Greece, 2020
Power-aware Test Scheduling for IEEE 1687 Networks with Multiple Power Domains
Autor: Payam Habiby, Sebastian Huhn, Rolf Drechsler
Konferenz: 33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Referenz: Frascati (Rome), Italy, 2020
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
Autor: Vladimir Herdt, Daniel Große, Eyck Jentzsch, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Kiel, Germany, 2020
Best Paper Award
RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms
Autor: Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Automated Technology for Verification and Analysis (ATVA)
Pdf | Referenz: Hanoi, Vietnam, 2020
ToPoliNano and fiction: Design Tools for Field-coupled Nanocomputing
Autor: Umberto Garlando, Marcel Walter, Robert Wille, Fabrizio Riente, Frank Sill Torres, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Portorož, Slowenien, 2020
Design Space Exploration in the Mapping of Reversible Circuits to IBM Quantum Computers
Autor: Philipp Niemann, Alexandre A. A. de Almeida, Gerhard Dueck, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Portorož, Slowenien, 2020
Combining Machine Learning and Formal Techniques for Small Data Applications - A Framework to Explore New Structural Materials
Autor: Rolf Drechsler, Sebastian Huhn, Christina Plump
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Portorož, Slowenien, 2020
Post Synthesis-Optimization of Reversible Circuit using Template Matching
Autor: Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Konferenz: In 2020 24th International Symposium on VLSI Design and Test (VDAT)
Pdf | Referenz: pp. 1-4. IEEE, 2020, DOI: 10.1109/VDAT50263.2020.9190279
Design Automation for Field-coupled Nanotechnologies
Autor: Marcel Walter, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Limassol, Cyprus, 2020
Best Student Forum Paper Award
Efficient Techniques to Strongly Enhance the Virtual Prototype based Design Flow
Autor: Vladimir Herdt, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Limassol, Cyprus, 2020
Automated Design Understanding of SystemC-based Virtual Prototypes: Data Extraction, Analysis and Visualization
Autor: Mehran Goli, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Limassol, Cyprus, 2020
Bail on Balancing: An Alternative Approach to the Physical Design of Field-coupled Nanocomputing Circuits
Autor: Marcel Walter, Robert Wille, Frank Sill Torres, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Limassol, Cyprus, 2020
Best Paper Candidate
Towards Generation of a Programmable Power Management Unit at the Electronic System Level
Autor: David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
Konferenz: 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Novi Sad, Serbia, 2020
LLVM-based Hybrid Fuzzing with LibKluzzer (Competition Contribution)
Autor: Hoang M. Le
Konferenz: International Conference on Fundamental Approaches to Software Engineering (FASE)
Referenz: Dublin, Ireland, 2020
Impacts of Block-based Programming on Young Learners' Programming Skills and Attitudes in the Context of Smart Environments
Autor: Mazyar Seraj, Rolf Drechsler
Konferenz: The 25th ACM annual conference on Innovation and Technology in Computer Science Education (ITiCSE)
Referenz: Trondheim, Norway, 2020
Efficient Machine Learning through Evolving Combined Deep Neural Networks
Autor: Rune Krauss, Marcel Merten, Mirco Bockholt, Saman Fröhlich, Rolf Drechsler
Konferenz: Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Referenz: Electronic-only, 2020
Early Verification of ISA Extension Specifications Using Deep Reinforcement Learning
Autor: Niklas Bruns, Daniel Große, Rolf Drechsler
Konferenz: 30th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: Beijing, China, 2020
Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes
Autor: Vladimir Herdt, Daniel Große, Jonas Wloka, Tim Güneysu, Rolf Drechsler
Konferenz: 30th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: Beijing, China, 2020
Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side
Autor: Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2020
Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes
Autor: Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2020
Verification for Field-coupled Nanocomputing Circuits
Autor: Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2020
Efficient Implementation of Nearest Neighbor Quantum Circuits Using Clustering with Genetic Algorithm
Autor: Anirban Bhattacharjee, Chandan Bandyopadhyay, Angshu Mukherjee, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Konferenz: 50th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Miyazaki, Japan, 2020
ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks
Autor: Saman Fröhlich, Lucas Klemmer, Daniel Große, Rolf Drechsler
Konferenz: 50th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Miyazaki, Japan, 2020
Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars
Autor: Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits & Systems (ISCAS)
Pdf | Referenz: Sevilla, Spain, 2020
Impacts of Creating Smart Everyday Objects on Young Female Students' Programming Skills and Attitudes
Autor: Mazyar Seraj, Eva-Sophie Katterfeldt, Serge Autexier, Rolf Drechsler
Konferenz: The 51st ACM Technical Symposium on Computer Science Education (SIGCSE)
Pdf | Referenz: Portland, Oregon, USA, 2020
Towards Specification and Testing of RISC-V ISA Compliance
Autor: Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Grenoble, France, 2020
Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes
Autor: Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Grenoble, France, 2020
Towards Formal Verification of Optimized and Industrial Multipliers
Autor: Alireza Mahzoon, Daniel Große, Christoph Scholl, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Grenoble, France, 2020
Integer Overflow Detection in Hardware Designs at the Specification Level
Autor: Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Konferenz: 8th International Conference on Model-Driven Engineering and Software Development (MODELSWARD)
Pdf | Referenz: Valetta, Malta, 2020
Towards Automatic Hardware Synthesis from Formal Specification to Implementation
Autor: Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Beijing, China, 2020
Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems
Autor: Rolf Drechsler, Daniel Große
Konferenz: Asian Test Symposium (ATS)
Pdf | Referenz: Kolkata, India, 2019
Scratch and Google Blockly: How Girls’ Programming Skills and Attitudes are Influenced
Autor: Mazyar Seraj, Eva-Sophie Katterfeldt, Kerstin Bub, Serge Autexier, Rolf Drechsler
Konferenz: The 19th Koli Calling International Conference on Computing Education Research (Koli Calling)
Pdf | Referenz: Koli, Finland, 2019
KLUZZER: Whitebox Fuzzing on top of LLVM
Autor: Hoang M. Le
Konferenz: Automated Technology for Verification and Analysis (ATVA)
Referenz: Taipei, Taiwan, 2019
A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems
Autor: Sebastian Huhn, Daniel Tille, Rolf Drechsler
Konferenz: International Test Conference in Asia (ITC-Asia)
Pdf | Referenz: Tokyo, Japan, 2019
Functional Coverage-Driven Characterization of RF Amplifiers
Autor: Muhammad Hassan, Daniel Große, Thilo Vörtler, Karsten Einwich and Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Southampton, United Kingdom, 2019
Best Paper Candidate
Systematic RISC-V based Firmware Design
Autor: Vladimir Herdt, Daniel Große, Rolf Drechsler, Christoph Gerum, Alexander Jung, Joscha-Joel Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Southampton, United Kingdom, 2019
SAT-Hard: A Learning-based Hardware SAT-Solver
Autor: Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Große and Rolf Drechsler
Konferenz: EUROMICRO Digital System Design Conference (DSD)
Pdf | Referenz: Kallithea - Chalkidiki, Greece, 2019
Towards Formal Verification of Plans for Cognition-enabled Autonomous Robotic Agents
Autor: Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: EUROMICRO Digital System Design Conference (DSD)
Pdf | Referenz: Kallithea - Chalkidiki, Greece, 2019
Scalable Simulation-based Verification of SystemC-based Virtual Prototypes
Autor: Mehran Goli, Rolf Drechsler
Konferenz: EUROMICRO Digital System Design Conference (DSD)
Pdf | Referenz: Kallithea - Chalkidiki, Greece, 2019
Code is Ethics —Formal Techniques for a Better World
Autor: Rolf Drechsler, Christoph Lüth
Konferenz: EUROMICRO Digital System Design Conference (DSD)
Pdf | Referenz: Kallithea - Chalkidiki, Greece, 2019
Property-driven Timestamps Encoding for Timeprints-based Tracing and Monitoring
Autor: Rehab Massoud, Hoang M. Le, Rolf Drechsler
Konferenz: 17th International Conference on Formal Modeling and Analysis of Timed Systems, (FORMATS)
Pdf | Referenz: Amsterdam, Netherlands, 27-29 August, 2019
Temporal Tracing of On-Chip Signals using Timeprints
Autor: Rehab Massoud, Hoang M. Le, Peter Chini, Prakash Saivasan, Roland Meyer and Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: Las Vegas, USA, 2019
RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers
Autor: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: Las Vegas, USA, 2019
Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study
Autor: Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: Las Vegas, USA, 2019
ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing
Autor: Steffen Frerix, Saeideh Shirinzadeh, Saman Fröhlich, Rolf Drechsler
Konferenz: International Symposium on Nanoscale Architectures (NanoArch 2019)
Pdf | Referenz: Qingdao, China, 2019
Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits
Autor: Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Miami, Florida, USA, 2019
Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-coupled Nanotechnologies
Autor: Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Miami, Florida, USA, 2019
Improved Look-ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits
Autor: Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler and Hafizur Rahaman
Konferenz: International Conference on VLSI Design (VLSI Design)
Pdf | Referenz: Florida, USA, 2019
Smart Homes Programming: Development and Evaluation of an Educational Programming Application for Young Learners
Autor: Mazyar Seraj, Cornelia Große, Serge Autexier, Rolf Drechsler
Konferenz: The 18th ACM International Conference on Interaction Design and Children (IDC)
Pdf | Referenz: Boise, Idaho, USA, 2019
Automated Analysis of Virtual Prototypes at Electronic System Level
Autor: Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
Konferenz: 29th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: Washington, D.C., USA, 2019
Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns
Autor: Sebastian Huhn, Daniel Tille, Rolf Drechsler
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Baden Baden, Germany, 2019
Machine Learning-based Prediction of Test Power
Autor: Harshad Dhotre, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Baden Baden, Germany, 2019
HotAging - Impact of Power Dissipation on Hardware Degradation
Autor: Frank Sill Torres, Alberto Garcia Ortiz and Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS)
Pdf | Referenz: Sapporo, Japan, 2019.
Look What I Can Do: Acquisition of Programming Skills in the Context of Living Labs
Autor: Mazyar Seraj, Cornelia Große, Serge Autexier, Rolf Drechsler
Konferenz: The IEEE/ACM 41st International Conference on Software Engineering: Software Engineering Education and Training (ICSE-SEET)
Pdf | Referenz: Montréal, QC, Canada, 2019
T-Depth Optimization for Fault-Tolerant Quantum Circuits
Autor: Philipp Niemann, Anshu Gupta, Rolf Drechsler
Konferenz: 49th IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Fredericton, NB, Canada, 2019
One Additional Qubit is Enough: Encoded Embeddings for Boolean Components in Quantum Circuits
Autor: Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille
Konferenz: 49th IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Fredericton, NB, Canada, 2019
(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-based Countermeasures on FPGAs
Autor: Kenneth Schmitz, Buse Ustaoglu, Daniel Große, Rolf Drechsler
Konferenz: International Symposium on Applied Reconfigurable Computing (ARC)
Pdf | Referenz: Darmstadt, Germany, 2019
Impact of NBTI on Increasing the Susceptibility of FinFET to Radiation
Autor: Frank Sill Torres, Hussam Amrouch, Jörg Henkel and Rolf Drechsler
Konferenz: IEEE International Reliability Physics Symposium (IRPS 2019)
Pdf | Referenz: Monterey, California, USA, March 31 - April 4, 2019
Accuracy and Compactness in Decision Diagrams for Quantum Computation
Autor: Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Florence, Italy, 2019
One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing
Autor: Saman Fröhlich, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Florence, Italy, 2019
Verifying Instruction Set Simulators using Coverage-guided Fuzzing
Autor: Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Florence, Italy, 2019
Data Flow Testing for SystemC-AMS Timed Data Flow Models
Autor: Muhammad Hassan, Daniel Große, Hoang M. Le, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Florence, Italy, 2019
Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing
Autor: Hoang M. Le, Daniel Große, Niklas Bruns, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Florence, Italy, 2019
Better Late Than Never: Verification of Embedded Systems After Deployment
Autor: Martin Ring, Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Florence, Italy, 2019
Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements
Autor: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Konferenz: 20th IEEE Latin American Test Symposium (LATS)
Pdf | Referenz: Santiago, Chile, 2019
Scalable Design for Field-coupled Nanocomputing Circuits
Autor: Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Tokyo, Japan, 2019
Maximizing Power State Cross Coverage in Firmware-based Power Management
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: 24th Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Tokyo, Japan, 2019
Reliable Integration of Thermal Flow Sensors into Air Data Systems
Autor: Felipe Augusto Braga Viana, Frank Sill Torres
Konferenz: 7th Brazilian Symposium on Computing System Engineering (SBESC 2018)
Pdf | Referenz: Salvador, Brazil, 2018
PolyCleaner: Clean your Polynomials before Backward Rewriting to Verify Million-gate Multipliers
Autor: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: San Diego, USA, 2018
Best Paper Award
IC/IP Piracy Assessment of Reversible Logic
Autor: Samah Mohamed Saeed, Xiaotong Cui, Alwin Zulehner,, Robert Wille, Rolf Drechsler, Kaijie Wu, Ramesh Karri
Konferenz: International Conference on Computer-Aided Design (ICCAD)
Pdf | Referenz: San Diego, 2018
Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters
Autor: David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
Konferenz: IEEE Nordic Circuits and Systems Conference (NORCAS)
Pdf | Referenz: Tallinn, Estonia, 2018
Using Constraints for SystemC AMS Design and Verification
Autor: Thilo Vörtler, Karsten Einwich, Muhammad Hassan, Daniel Große
Konferenz: Design and Verification Conference and Exhibition Europe (DVCon Europe)
Pdf | Referenz: Munich, Germany, 2018
Best Paper Award
Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques
Autor: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Konferenz: IEEE International Symposium on Rapid System Prototyping (RSP), 2018
Pdf | Referenz: Torino, Italy, 2018
BEESM, a Block-Based Educational Programming Tool for End Users
Autor: Mazyar Seraj, Serge Autexier, Jan Janssen
Konferenz: The 10th Nordic Conference on Human-Computer Interaction (NordiCHI)
Pdf | Referenz: Oslo, Norway, 2018
Multi-Objective Synthesis of Quantum Circuits Using Genetic Programming
Autor: Moein Sarvaghad-Moghaddam, Philipp Niemann, Rolf Drechsler
Konferenz: Reversible Computation
Pdf | Referenz: pp. 220-227, Leicester, UK, 2018
Extensible and Configurable RISC-V based Virtual Prototype
Autor: Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Munich, Germany, 2018
Automatic Design of Microfluidic Devices: An Overview of Platforms and Corresponding Design Tasks
Autor: Robert Wille, Bing Li, Rolf Drechsler and Ulf Schlichtmann
Konferenz: In Forum on specification & Design Languages (FDL), München, 2018
Pdf | Referenz:
Design criteria of a thermal mass flow sensor for aircraft air data applications
Autor: Lucas C. Ribeiro, Rubens A. Souza, Michael Lopes Oliveira, S.P.L. Vieira, W.O. Avelino, Clarice F.R. Oliveira, Davies Wiliiam de Lima Monteiro, Frank Sill Torres, Roana M.O. Hansen
Konferenz: 31st Congress of the International Council of the Aeronautical Sciences (ICAS 2018)
Pdf | Referenz: Belo Horizonte, Brazil, 2018
Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata
Autor: Frank Sill Torres, Pedro A. Silva, Geraldo Fontes, José Augusto M. Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Prague, Czech Republic, 2018
Towards Self-explaining Intelligent Environments
Autor: Serge Autexier, Rolf Drechsler
Konferenz: International Converence on Reliability, Infocom Technologies and Optimization (ICRITO)
Pdf | Referenz: Noida, India, 2018
Cell Library Design for Ultra-Low Power Internet-of-Things Applications
Autor: Michael Lopes Oliveira, Keyliane Fernandes, Frank Sill Torres
Konferenz: 3rd International Symposium on Instrumentation Systems, Circuits and Transducers (INSCIT 2018)
Pdf | Referenz: Bento Gonçalves, Brazil, 2018
Towards Reversed Approximate Hardware Design
Autor: Saman Fröhlich, Daniel Große, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Prague, Czech Republic, 2018
Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata
Autor: Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Große, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 649-656, Prague, Czech Republic, 2018
Synchronization of Clocked Field-Coupled Circuits
Autor: Frank Sill Torres, Marcel Walter, Robert Wille, Daniel Große, Rolf Drechsler
Konferenz: IEEE International Conference on Nanotechnology (Nano)
Pdf | Referenz: Cork, Ireland, 2018
On overcoming photodetector saturation due to background illumination while maintaining high sensitivity by means of a tailored CMOS pixel
Autor: Pablo Nunes Agra Belmonte, Lucas Chaves, Frank Sill Torres, Davies William de Lima Monteiro
Konferenz: Global LiFi Congress
Pdf | Referenz: Paris, France, 2018
Enhancing Fundamental Energy Limits of Field-Coupled Nanocomputing Circuits
Autor: Jeferson Figueiredo Chave, Marco Ribeiro, Frank Sill Torres, Omar Paranaiba Vilela Neto
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS)
Pdf | Referenz: Florence, Italy, 2018
Logic Synthesis for In-Memory Computing using Resistive Memories
Autor: Saeideh Shirinzadeh, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Hong Kong SAR, China, 2018
A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits
Autor: Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Hong Kong SAR, China, 2018
Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers
Autor: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: pp. 351-356, Hong Kong SAR, China, 2018
Towards Dynamic Execution Environment for System Security Protection against Hardware Flaws
Autor: Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: pp. 557-562, Hong Kong SAR, China, 2018
Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling
Autor: Robert Schmidt, Rehab Massoud, Jaan Raik, Alberto Garcia-Ortiz, Rolf Drechsler
Konferenz: 24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)
Pdf | Referenz: Costa Brava, Spain, 2018
Natural Language based Power Domain Partitioning
Autor: David Lemma, Daniel Große, Rolf Drechsler
Konferenz: 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 101-106, Budapest, Hungary, 2018
Augmenting All Solution SAT Solving for Circuits with Structural Information
Autor: Abraham Temesgen Tibebu, Görschwin Fey
Konferenz: 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Referenz: Budapest, Hungary, 2018
Constraint-based Pattern Retargeting for Reducing Localized Power Activity during Testing
Autor: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen
Konferenz: 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Budapest, Hungary, 2018
SAT-Lancer: A Hardware SAT-Solver for Self-Verification
Autor: Buse Ustaoglu, Sebastian Huhn, Daniel Große, Rolf Drechsler
Konferenz: 28th ACM Great Lakes Symposium on VLSI (GLVLSI)
Pdf | Referenz: pp. 479-482, Chicago, Illinois, USA, 2018
Received Best Poster Award
Translating between the roots of the identity in quantum computers
Autor: Wouter Castryck, Jeroen Demeyer, Alexis De Vos, Oliver Keszocze, Mathias Soeken
Konferenz: IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Linz, Austria, 2018
Synthesis of Reversible Circuits Using Conventional Hardware Description Languages
Autor: Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Konferenz: IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Linz, Austria, 2018
Logic Design using Memristors: An Emerging Technology
Autor: Saeideh Shirinzadeh, Kamalika Datta, Rolf Drechsler
Konferenz: IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Linz, Austria, 2018
Translating between the roots of identity in quantum circuits
Autor: Wouter Castryck, Jeroen Demeyer, Alexis De Vos, Oliver Keszöcze, Mathias Soeken
Konferenz: 48th IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Referenz: Linz, Austria, 2018
Building Fast Multi-Agent Systems using Hardware Design Languages for High-Throughput Systems
Autor: Jannis Stoppe, Christina Plump, Sebastian Huhn, Rolf Drechsler
Konferenz: 6th International Conference on Dynamics in Logistics (LDIC)
Pdf | Referenz: Bremen, Germany, 2018
Confident Leakage Assessment - A Side-Channel Evaluation Framework based on Confidence Intervals
Autor: Florian Bache, Christina Plump, Tim Güneysu
Konferenz: Design, Automation and Test in Europe (DATE)
Referenz: Dresden, Germany, 2018
Improved Synthesis of Clifford+T Quantum Functionality
Autor: Philipp Niemann, Robert Wille, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 597-600, Dresden, Germany, 2018
Resiliency Evaluation via Symbolic Fault Injection on Intermediate Code
Autor: Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 845-850, Dresden, Germany, 2018
Towards Fully Automated TLM-to-RTL Property Refinement
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1508-1511, Dresden, Germany, 2018
Testbench Qualification for SystemC-AMS Timed Data Flow Models
Autor: Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 857-860, Dresden, Germany, 2018
Approximate Hardware Generation using Symbolic Computer Algebra employing Gröbner Basis
Autor: Saman Fröhlich, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 889-892, Dresden, Germany, 2018
An Exact Method for Design Exploration of Quantum-dot Cellular Automata
Autor: Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 503-508, Dresden, Germany, 2018
Analyzing Frame Conditions in UML/OCL Models: Consistency, Equivalence, and Independence
Autor: Philipp Niemann, Nils Przigoda, Robert Wille, Rolf Drechsler
Konferenz: 6th International Conference on Model-Driven Engineering and Software Development (MODELSWARD)
Pdf | Referenz: pp. 139-151, Funchal, Portugal, 2018
Approximation-aware Testing for Approximate Circuits
Autor: Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler
Konferenz: 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: pp. 239 - 244, Jeju, Korea, 2018
Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips
Autor: Oliver Keszöcze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Konferenz: International Conference on VLSI Design (VLSID)
Pdf | Referenz: Pune, Indien, 2018
Revealing Properties of Structural Materials by Combining Regression-based Algorithms and Nano Indentation Measurements
Autor: Sebastian Huhn, Heike Sonnenberg, Stephan Eggersglüß, Brigitte Clausen, Rolf Drechsler
Konferenz: 10th IEEE Symposium Series on Computational Intelligence (SSCI)
Pdf | Referenz: Hawaii, USA, 2017
Towards Lightweight Satisfiability Solvers for Self-Verification
Autor: Fritjof Bornebusch, Robert Wille, Rolf Drechsler
Konferenz: 7th International Symposium on Embedded Computing and System Design (ISED)
Pdf | Referenz: Durgapur, Indien, 2017
Verifying Next Generation Electronic Systems
Autor: Rolf Drechsler, Daniel Große
Konferenz: International Conference on Infocom Technologies and Unmanned Systems (ICTUS)
Pdf | Referenz: pp. 6 - 10, Dubai, United Arab Emirates, 2017
Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata
Autor: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Konferenz: 35th IEEE International Conference on Computer Design (ICCD)
Pdf | Referenz: Boston Area, Massachusetts, USA, 2017
Identification of Efficient Clustering Techniques for Test Power Activity on the Layout
Autor: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Konferenz: 26th IEEE Asian Test Symposium (ATS)
Pdf | Referenz: Taipei, Taiwan, 2017
More than true or false: Native Support of Irregular Values in the Automatic Validation & Verification of UML/OCL Models
Autor: Nils Przigoda, Philipp Niemann, Judith Peters, Frank Hilken, Robert Wille, Rolf Drechsler
Konferenz: 15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Referenz: pp. 77-86, Vienna, Austria, 2017
Yise - A novel Framework for Boolean Networks using Y-Inverter Graphs
Autor: Arun Chandrasekharan, Daniel Große, Rolf Drechsler
Konferenz: 15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Referenz: pp. 114-117, Vienna, Austria, 2017
Reconfigurable TAP Controllers with Embedded Compression for Large Test Data Volume
Autor: Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler
Konferenz: 30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Referenz: Cambridge, UK, 2017
Machine Learning Based Test Pattern Analysis for Localizing Critical Power Activity Areas
Autor: Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler
Konferenz: 30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Referenz: Cambridge, UK, 2017
Unintrusive Aging Analysis based on Offline Learning
Autor: Frank Sill Torres, Pedro F. R. Leite Junior and Rolf Drechsler
Konferenz: 30th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Referenz: Cambridge, UK, 2017
Towards Early Validation of Firmware-Based Power Management using Virtual Prototypes: A Constrained Random Approach
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: pp. 1-8, Verona, Italy, 2017
Best Paper Candidate
Semi-Formal Cycle-Accurate Temporal Execution Traces Reconstruction
Autor: Rehab Massoud, Jannis Stoppe, Daniel Große, Rolf Drechsler
Konferenz: 15th International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS)
Pdf | Referenz: pp. 335-351, Berlin, Germany, 2017
Early SoC Security Validation by VP-based Static Information Flow Analysis
Autor: Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: pp. 400-407, Irvine, USA, 2017
Dedicated Synthesis for MZI-based Optical Circuits based on AND-Inverter Graphs
Autor: Arighna Deb, Robert Wille, Rolf Drechsler
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: Irvine, USA, 2017
Self-practicing of logic circuits through mobile devices: Lecturers' and students' perceptions
Autor: Mazyar Seraj, Cornelia Große, Rolf Drechsler
Konferenz: The 9th annual International Conference on Education and New Learning Technologies (EduLearn17)
Pdf | Referenz: Barcelona, Spain, 2017
BioViz: An Interactive Visualization Engine for Digital Microfluidic Biochips
Autor: Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Bochum, Germany, 2017
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects
Autor: Tino Flenker, Jan Malburg, Goerschwin Fey, Serhiy Avramenko, Massimo Violante and Matteo Sonza Reorda
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Bochum, Germany, 2017
Towards VHDL-based Design of Reversible Circuits
Autor: Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Konferenz: Reversible Computation
Pdf | Referenz: Kolkata, India, 2017
Efficient Construction of QMDDs for Irreversible, Reversible and Quantum Functions
Autor: Philipp Niemann, Alwin Zulehner, Robert Wille, Rolf Drechsler
Konferenz: Reversible Computation
Pdf | Referenz: pp. 214-231, Kolkata, India, 2017
Mapping Abstract and Concrete Hardware Models for Design Understanding
Autor: Tino Flenker, Görschwin Fey
Konferenz: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Dresden, Germany, 2017
An Adaptive Prioritized ε-Preferred Evolutionary Algorithm for Approximate BDD Optimization
Autor: Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
Konferenz: Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Referenz: Berlin, Germany, 2017
Hiding Higher-Order Side-Channel Leakage - Randomizing Cryptographic Implementations in Reconfigurable Hardware
Autor: Pascal Sasdrich, Amir Moradi, Tim Güneysu
Konferenz: RSA Conference Cryptographers’ Track (CT-RSA)
Pdf | Referenz: San Francisco, US, 2017.
ProACt: A Processor for High Performance On-demand Approximate Computing
Autor: Arun Chandrasekharan, Daniel Große, Rolf Drechsler
Konferenz: 27th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 463-466, Banff, Alberta, Canada, 2017
OR-Inverter Graphs for the Synthesis of Optical Circuits
Autor: Arighna Deb, Robert Wille, Rolf Drechsler
Konferenz: 47th International Symposium on Multiple-Valued Logic (ISMVL)
Referenz: Novi Sad, Serbia, 2017
Extensions to the Reversible Hardware Description Language SyReC
Autor: Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Konferenz: 47th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Novi Sad, Serbia, 2017
Error Bounded Exact BDD Minimization in Approximate Computing
Autor: Saman Fröhlich, Daniel Große, Rolf Drechsler
Konferenz: 47th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 254-259, Novi Sad, Serbia, 2017
Exact Synthesis of Ternary Reversible Functions using Ternary Toffoli Gates
Autor: Abhoy Kole, P. Mercy Nesa Rani, Kamalika Datta, Indranil Sengupta, Rolf Drechsler
Konferenz: 47th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Novi Sad, Serbia, 2017
Effects of Cell Shapes on the Routability of Digital Microfluidic Biochips
Autor: Kevin Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Lausanne, Switzerland, 2017
Automatic Equivalence Checking for SystemC-TLM 2.0 Models Against their Formal Specifications
Autor: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Lausanne, Switzerland, 2017
Data Flow Testing for Virtual Prototypes
Autor: Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Lausanne, Switzerland, 2017
Endurance Management for Resistive Logic-In-Memory Computing Architectures
Autor: Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Lausanne, Switzerland, 2017
Optimization of Retargeting for IEEE 1149.1 TAP Controllers with Embedded Compression
Autor: Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Lausanne, Schweiz, 2017
Trust is good, Control is better: Hardware-based Instruction-Replacement for Reliable Processor-IPs
Autor: Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler
Konferenz: 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Chiba/Tokyo, Japan, 2017
Enhancing Robustness of Sequential Circuits Using Application-specific Knowledge and Formal Methods
Autor: Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler
Konferenz: 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Chiba/Tokyo, Japan, 2017
CEGAR-based EF Synthesis of Boolean Functions with an Application to Circuit Rectification
Autor: Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Konferenz: 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: pp. 251-256, Chiba/Tokyo, Japan, 2017
Exact Routing for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
Autor: Oliver Keszöcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Konferenz: 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Chiba/Tokyo, Japan, 2017
Property mining using dynamic dependency graphs
Autor: Jan Malburg, Tino Flenker, Goerschwin Fey
Konferenz: 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Chiba/Tokyo, Japan, 2017
White-Box Cryptography in the Gray Box - A Hardware Implementation and its Side Channels
Autor: Pascal Sasdrich, Amir Moradi, Tim Güneysu
Konferenz: FSE 2016: 185-203
Referenz: http://dx.doi.org/10.1007/978-3-662-52993-5_10
Exploring Superior Structural Materials Using Multi-Objective Optimization and Formal Techniques
Autor: Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler
Konferenz: 6th IEEE International Symposium on Embedded Computing & System Design (ISED)
Pdf | Referenz: Indian Institute of Technology, Patna, India, 2016
Clocks vs. Instants Relations: Verifying CCSL Time Constraints in UML/MARTE Models
Autor: Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler
Konferenz: 14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Referenz: Indian Institute of Technology, Kanpur, India, 2016
Frame Conditions in Symbolic Representations of UML/OCL Models
Autor: Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler
Konferenz: 14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Referenz: pp. 65-70, Indian Institute of Technology, Kanpur, India, 2016
Guided Lightweight Software Test Qualification for IP Integration using Virtual Prototypes
Autor: Daniel Große, Hoang M. Le, Muhammad Hassan, Rolf Drechsler
Konferenz: IEEE International Conference on Computer Design (ICCD)
Pdf | Referenz: Phoenix, USA, 2016
AIBA: an Automated Intra-Cycle Behavioral Analysis for SystemC-based Design Exploration
Autor: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Konferenz: IEEE International Conference on Computer Design (ICCD)
Pdf | Referenz: Phoenix, USA, 2016
Generating and Checking Control Logic in the HDL-based Design of Reversible Circuits
Autor: Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Konferenz: International Symposium on Electronic System Design (ISED)
Referenz: Patna, Indien, 2016
An Improved Gate Library for Logic Synthesis of Optical Circuits
Autor: Shuchisman Burman, Kamalika Datta, Robert Wille, Indranil Sengupta, Rolf Drechsler
Konferenz: International Symposium on Electronic System Design (ISED)
Referenz: Patna, Indien, 2016
Towards a Model-Based Verification Methodology for Complex Swarm Systems
Autor: Jonas Gomes Filho, Nils Przigoda, Robert Wille, Rolf Drechsler
Konferenz: International Symposium on Electronic System Design (ISED)
Referenz: Patna, Indien, 2016
Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test
Autor: Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen
Konferenz: IEEE Asian Test Symposium (ATS)
Pdf | Referenz: Hiroshima, Japan, 2016
Automated Optimization of Scan Chain Structure for Test Compression-Based Designs
Autor: Harshad Dhotre, Mehdi Dehbashi, Ulrike Pfannkuchen, Klaus Hofmann
Konferenz: IEEE Asian Test Symposium (ATS)
Referenz: Hiroshima, Japan, 2016
A Hybrid Algorithm to Conservatively Check the Robustness of Circuits
Autor: Niels Thole, Lorena Anghel, Görschwin Fey
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Referenz: Pittsburgh, USA, 2016
Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding
Autor: Nils Przigoda, Robert Wille, Rolf Drechsler
Konferenz: ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Pdf | Referenz: Saint Malo, Brittany, France, 2016
Equivalence Checking Using Gröbner Bases
Autor: Amr Sayed Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler
Konferenz: Formal Methods in Computer Aided Design (FMCAD)
Pdf | Referenz: Mountain View, USA, 2016
On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-based Error Effect Simulation - A Case Study
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Bremen, Germany, 2016
Best Paper Candidate
Designing Reliable Cyber-Physical Systems
Autor: Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon Ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Bremen, Germany, 2016
Equivalence Checking on ESL Utilizing A Priori Knowledge
Autor: Niels Thole, Heinz Riener, Görschwin Fey
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Bremen, Germany, 2016
WCET Overapproximation for Software in the Context of Cyber-Physical Systems
Autor: Niklas Krafczyk, Heinz Riener, Görschwin Fey
Konferenz: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Pdf | Referenz: Tallinn, Estonia, 2016
Strong 8-bit Sboxes with Efficient Masking in Hardware
Autor: Erik Boss, Vincent Grosso, Tim Güneysu, Gregor Leander, Amir Moradi, Tobias Schneider
Konferenz: CHES 2016: 171-193
Referenz: http://dx.doi.org/10.1007/978-3-662-53140-2_9
ParTI - Towards Combined Hardware Countermeasures Against Side-Channel and Fault-Injection Attacks
Autor: Tobias Schneider, Amir Moradi, Tim Güneysu
Konferenz: CRYPTO (2), Santa Barbara, USA, 2016: 302-332
Referenz: http://dx.doi.org/10.1007/978-3-662-53008-5_11
Approximation-aware Rewriting of AIGs for Error Tolerant Applications
Autor: Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: Austin, USA, 2016
Compiled Symbolic Simulation for SystemC
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: Austin, USA, 2016
Exact Diagnosis Using Boolean Satisfiability
Autor: Heinz Riener, Görschwin Fey
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: Austin, USA, 2016
On the problems of realizing reliable and efficient ring oscillator PUFs on FPGAs.
Autor: Alexander Wild, Georg T. Becker, Tim Güneysu
Konferenz: Hardware-Oriented Security and Trust (HOST) 2016: 103-108
Referenz: http://dx.doi.org/10.1109/HST.2016.7495565
Secure and Private, yet Lightweight, Authentication for the IoT via PUF and CBKA
Autor: Christopher Huth, Aydin Aysu, Jorge Guajardo, Paul Duplys, Tim Güneysu
Konferenz: ICISC 2016: 28-48
Referenz: http://dx.doi.org/10.1007/978-3-319-53177-9_2
Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs
Autor: Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Konferenz: Reversible Computation
Referenz: Bologna, Italy, 2016
Enumeration of reversible functions and its application to circuit complexity
Autor: Mathias Soeken, Nabila Abdessaied, Giovanni De Micheli
Konferenz: Reversible Computation
Pdf | Referenz: Bologna, Italy, 2016
High-Performance and Lightweight Lattice-Based Public-Key Encryption
Autor: Johannes A. Buchmann, Florian Göpfert, Tim Güneysu, Tobias Oder, Thomas Pöppelmann
Konferenz: IoTPTS@AsiaCCS 2016: 2-9
Referenz: http://doi.acm.org/10.1145/2899007.2899011
IND-CCA Secure Hybrid Encryption from QC-MDPC Niederreiter
Autor: Ingo von Maurich, Lukas Heberle, Tim Güneysu
Konferenz: Post-Quantum Cryptography (PQCrypto 2016)
Referenz: pages 1-17, LNCS Vol. 9606, Fukuoka, Japan
Secure software update and IP protection for untrusted devices in the Internet of Things via physically unclonable functions
Autor: Christopher Huth, Paul Duplys, Tim Güneysu
Konferenz: IEEE International Conference on Pervasive Computing and Communication Workshops (PerCom Workshops)
Referenz: pages 1-6, Sydney, Australia
ParCoSS: Efficient Parallelized Compiled Symbolic Simulation
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: International Conference on Computer Aided Verification (CAV)
Pdf | Referenz: Toronto, Canada, 2016
Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables
Autor: Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Goerschwin Fey
Konferenz: IEEE Latin-American Test Symposium (LATS2016)
Pdf | Referenz: Foz do Iguaçu, Brazil, 2016
Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm
Autor: Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
Konferenz: Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Referenz: Denver, USA, 2016
Robust and One-Pass Parallel Computation of Correlation-Based Attacks at Arbitrary Order
Autor: Tobias Schneider, Amir Moradi, Tim Güneysu
Konferenz: COSADE 2016, Graz, p. 199-217
Referenz: http://dx.doi.org/10.1007/978-3-319-43283-0_12
Standard lattices in hardware
Autor: James Howe, Ciara Moore, Máire O'Neill, Francesco Regazzoni, Tim Güneysu, K. Beeden
Konferenz: Design Automation Conference (DAC), Austin, USA, 2016, 162:1-162:6
Referenz: http://doi.acm.org/10.1145/2903150.2907756
An MIG-based Compiler for Programmable Logic-in-Memory Architectures
Autor: Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: Austin, USA, 2016
Precise Error Determination of Approximated Components in Sequential Circuits with Model Checking
Autor: Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: Austin, USA, 2016
Multi-Objective BDD Optimization for RRAM based Circuit Design
Autor: Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
Konferenz: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'16)
Pdf | Referenz: Košice, Slovakia, 2016
A grain in the silicon: SCA-protected AES in less than 30 slices
Autor: Pascal Sasdrich, Tim Güneysu
Konferenz: IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) 2016: 25-32
Referenz: http://dx.doi.org/10.1109/ASAP.2016.7760769
Exploiting Error Detection Latency for Parity-based Soft Error Detection
Autor: Gökçe Aydos, Görschwin Fey
Konferenz: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Košice, Slovakia, 2016
On the Energy Cost of Channel Based Key Agreement
Autor: Christopher Huth, René Guillaume, Paul Duplys, Kumaragurubaran Velmurugan, Tim Güneysu
Konferenz: TrustED@CCS 2016: 31-41
Referenz: http://doi.acm.org/10.1145/2995289.2995291
Secure architectures of future emerging cryptography SAFEcrypto
Autor: Máire O'Neill, Elizabeth O'Sullivan, Gavin McWilliams, Markku-Juhani Saarinen, Ciara Moore, Ayesha Khalid, James Howe, Rafaël Del Pino, Michel Abdalla, Francesco Regazzoni, Felipe Valencia, Tim Güneysu, Tobias Oder, Adrian Waller, Glyn Jones, Anthony Barnett, Robert Griffin, Andrew Byrne, Bassem Ammar, David Lund
Konferenz: Conf. Computing Frontiers 2016: 315-322
Referenz: http://doi.acm.org/10.1145/2903150.2907756
VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers
Autor: Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Amsterdam, Niederlande, 2016
SAT-Based Post-Processing for Regional Capture Power Reduction in At-Speed Scan Test Generation
Autor: Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Amsterdam, Niederlande, 2016
A Hybrid Algorithm to Conservatively Check the Robustness of Circuits
Autor: Niels Thole, Lorena Anghel, Görschwin Fey
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Amsterdam, Niederlande, 2016
Towards a Catalog of Structural and Behavioral Verification Tasks for UML/OCL Models
Autor: Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Konferenz: Modellierung
Pdf | Referenz: pp. 117-124, Karlsruhe, Germany, 2016
Fault Detection in Parity Preserving Reversible Circuits
Autor: Nils Przigoda, Gerhard Dueck, Robert Wille, Rolf Drechsler
Konferenz: 46th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Sapporo, Japan, 2016
Re-writing HDL Descriptions for Line-aware Synthesis of Reversible Circuits
Autor: Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Konferenz: 46th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Sapporo, Japan, 2016
Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation
Autor: Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Konferenz: 46th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Sapporo, Japan, 2016
Logic Synthesis for Quantum State Generation
Autor: Philipp Niemann, Rhitam Datta, Robert Wille
Konferenz: 46th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 247-252, Sapporo, Japan, 2016
Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits
Autor: Md. Mazder Rahman, Gerhard W. Dueck, Anupam Chattopadhyay, Robert Wille
Konferenz: 46th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Sapporo, Japan, 2016
Technology mapping of reversible circuits to Clifford+T quantum circuits
Autor: Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler
Konferenz: 46rd International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Sapporo, Japan, 2016
Quantitative Timing Analysis of UML Activity Diagrams Using Statistical Model Checking
Autor: Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 780-785, Dresden, Germany, 2016
Towards Formal Verification of Real-World SystemC TLM Peripheral Models - A Case Study
Autor: Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1160-1163, Dresden, Germany, 2016
Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction
Autor: Amr Sayed Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1048-1053, Dresden, Germany, 2016
Best Paper Candidate
Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs
Autor: Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Dresden, Germany, 2016
Optimizing Majority-Inverter Graphs With Functional Hashing
Autor: Mathias Soeken, Pierre-Emmanuel Gaillardon, Luca Amaru, Giovanni De Micheli
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Dresden, Germany, 2016
Synthesis of Approximate Coders for On-chip Interconnects Using Reversible Logic
Autor: Robert Wille, Oliver Keszöcze, Stefan Hillmich, Marcel Walter, Alberto Garcia-Ortiz
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Dresden, Germany, 2016
Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking
Autor: Luca Amaru, Pierre-Emmanuel Gaillardon, Robert Wille, Giovanni De Micheli
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Dresden, 2016
Look-ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits
Autor: Robert Wille, Oliver Keszöcze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Macao, China, 2016
BDD Minimization for Approximate Computing
Autor: Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: pp. 474-479, Macao, China, 2016
Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library
Autor: Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Konferenz: International Conference on VLSI Design (VLSI Design)
Referenz: Kolkata, India, 2016
Hardware/Software Co-Visualization on the Electronic System Level using SystemC
Autor: Rolf Drechsler, Jannis Stoppe
Konferenz: International Conference on VLSI Design
Pdf | Referenz: Kolkata, India, 2016
Ensuring Safety and Reliability of IP-based System Design – A Container Approach
Autor: Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, Rolf Drechsler
Konferenz: IEEE International Symposium on Rapid System Protoyping (RSP), 2015
Pdf | Referenz:
Empirical Results on Parity-based Soft Error Detection with Software-based Retry
Autor: Gökçe Aydos, Görschwin Fey
Konferenz: IEEE Nordic Circuits and Systems Conference (NORCAS)
Pdf | Referenz: Oslo, Norway, 2015
Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation
Autor: Tino Flenker, André Sülflow, Görschwin Fey
Konferenz: 24th IEEE Asian Test Symposium (ATS)
Pdf | Referenz: Mumbai, India, 2015
Reversible Computation: An Alternative Computation Paradigm for Low Power Applications
Autor: Rolf Drechsler, Robert Wille
Konferenz: International Green and Sustainable Computing Conference (IGSC)
Pdf | Referenz: Las Vegas, USA, 2015
Checking Concurrent Behavior in UML/OCL Models
Autor: Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, Rolf Drechsler
Konferenz: ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Pdf | Referenz: Ottawa, Kanada, 2015
Extracting Frame Conditions from Operation Contracts
Autor: Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Konferenz: ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Pdf | Referenz: pp. 266-275, Ottawa, Canada, 2015
Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation
Autor: Hoang M. Le, Rolf Drechsler
Konferenz: Design and Verification Conference and Exhibition Europe (DVCon Europe)
Pdf | Referenz: Munich, Germany, 2015
Reverse Engineering with Simulation Graphs
Autor: Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton
Konferenz: Formal Methods in Computer Aided Design (FMCAD)
Pdf | Referenz: Austin, 2015
Reversible Circuit Rewriting with Simulated Annealing
Autor: Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, and Rolf Drechsler
Konferenz: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Pdf | Referenz: Daejeon, Korea, 2015
A General and Exact Routing Methodology for Digital Microfluidic Biochips
Autor: Oliver Keszöcze, Robert Wille, Krishnendu Chakrabarty Rolf Drechsler
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: Austin, USA, 2015
Formal Methods for Emerging Technologies
Autor: Robert Wille, Rolf Drechsler
Konferenz: International Conference on Computer Aided Design (ICCAD)
Referenz: Austin, USA, 2015
Leveraging the Analysis for Invariant Independence in Formal System Models
Autor: Nils Przigoda, Robert Wille, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Funchal, Madeira, Portugal, 2015
Verification-driven Design Across Abstraction Levels - A Case Study
Autor: Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Funchal, Madeira, Portugal, 2015
Envisioning Self-Verification of Electronic Systems
Autor: Rolf Drechsler, Martin Fränzle, Robert Wille
Konferenz: Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Pdf | Referenz: Bremen, Germany, 2015
Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits
Autor: Amr Sayed Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015).
Pdf | Referenz: pp. 1-6, Montpellier, France, 2015.
Conservatively Analyzing Transient Faults
Autor: Niels Thole, Görschwin Fey, Alberto Garcia-Ortiz
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Montpelier, France, 2015
Coverage of OCL Operation Specifications and Invariants
Autor: Mathias Soeken, Julia Seiter, Rolf Drechsler
Konferenz: 9th International Conference on Tests & Proofs (TAP)
Pdf | Referenz: L’Aquila, Italy, 2015
Ricercar: A Language for Describing and Rewriting Reversible Circuits with Ancillae and its Permutation Semantics
Autor: Michael Kirkedal Thomsen, Mathias Soeken, Robin Kaarsgaard
Konferenz: Reversible Computation
Pdf | Referenz: Grenoble, France, 2015
Towards Line-aware Realizations of Expressions for HDL-based Synthesis of Reversible Circuits
Autor: Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Konferenz: Reversible Computation
Pdf | Referenz: Grenoble, France, 2015
Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions
Autor: Philipp Niemann, Saikat Basu, Amlan Chakrabarti, Niraj K. Jha, Robert Wille
Konferenz: Reversible Computation
Pdf | Referenz: pp. 248-264, Grenoble, France, 2015
Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits
Autor: Abhoy Kole, Kamalika Datta, Indranil Sengupta, Robert Wille
Konferenz: Reversible Computation
Pdf | Referenz: Grenoble, France, 2015
Technology mapping for quantum circuits using Boolean functional decomposition
Autor: Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
Konferenz: Reversible Computation
Pdf | Referenz: Grenoble, France, 2015
From UML/OCL to Base Models: Transformation Concepts for Generic Validation and Verification
Autor: Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Konferenz: International Conference on Model Transformation (ICMT)
Pdf | Referenz: pp. 149-165, L’Aquila, Italy, 2015
Multi-Objective BDD Optimization with Evolutionary Algorithms
Autor: Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
Konferenz: Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Referenz: Madrid, 2015
Contradiction Analysis for Inconsistent Formal Models
Autor: Nils Przigoda, Robert Wille, Rolf Drechsler
Konferenz: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Pdf | Referenz: Belgrade, Serbia, 2015
Requirement Phrasing Assistance using Automatic Quality Assessment
Autor: Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler
Konferenz: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Pdf | Referenz: Belgrade, Serbia, 2015
Equivalence Checking on System Level using A Priori Knowledge
Autor: Niels Thole, Heinz Riener, Görschwin Fey
Konferenz: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Pdf | Referenz: Belgrade, Serbia, 2015
Compact Test Set Generation for Test Compression-based Designs
Autor: Stephan Eggersglüß
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Cluj-Napoca, Romania, 2015
A Generic Representation of CCSL Time Constraints for UML/MARTE Models
Autor: Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, 2015
Verifying SystemC using Stateful Symbolic Simulation
Autor: Vladimir Herdt, Hoang M. Le, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, 2015
Fredkin-Enabled Transformation-based Reversible Logic Synthesis
Autor: Mathias Soeken, Anupam Chattopadhyay
Konferenz: 45th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Waterloo, Canada, 2015
Dynamic Template Matching with Mixed-polarity Toffoli Gates
Autor: Md Mazder Rahman, Mathias Soeken, Gerhard W. Dueck
Konferenz: 45th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Waterloo, Canada, 2015
An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization
Autor: Arighna Deb, Robert Wille, Rolf Drechsler, Debesh Das
Konferenz: 45th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Waterloo, Canada, 2015
An Examination of the NCV-v1 Quantum Library Based on Minimal Circuits
Autor: Arman Allahyari-Abhari, Robert Wille, Rolf Drechsler
Konferenz: 45th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Waterloo, Canada, 2015
Automated Feature Localization for Dynamically Generated SystemC Designs
Autor: Jannis Stoppe, Robert Wille, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE'15)
Pdf | Referenz: Grenoble, France, 2015
Assisted Generation of Frame Conditions for Formal Models
Autor: Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Konferenz: Design, Automation and Test in Europe (DATE'15)
Pdf | Referenz: pp. 309-312, Grenoble, France, 2015
A Unified Formulation of Behavioral Semantics for SysML Models
Autor: Christoph Hilken, Jan Peleska, Robert Wille
Konferenz: International Conference on Model-Driven Engineering and Software Development
Pdf | Referenz: Angers, France, 2015
BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits
Autor: Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Konferenz: International Conference on VLSI Design (VLSI Design)
Pdf | Referenz: Bengaluru, India, 2015
Determining the Minimal Number of SWAP Gates for Multi-dimensional Nearest Neighbor Quantum Circuits
Autor: Aaron Lye, Robert Wille, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Chiba/Tokyo, 2015
Reverse BDD-based Synthesis for Splitter-free Optical Circuits
Autor: Robert Wille, Oliver Keszöcze, Clemens Hopfmuller, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Chiba/Tokyo, 2015
Safe IP Integration Using Container Modules
Autor: Rolf Drechsler, Ulrich Kühne
Konferenz: International Symposium on Electronic System Design (ISED)
Pdf | Referenz: Mangalore, India, 2014
Automated Formal Verification of X Propagation with Respect to Testability Issues
Autor: Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß
Konferenz: IEEE International Design and Test Symposium 2014 (IDT)
Pdf | Referenz: pp. 106-111, Algiers, Algerien, 2014
Exact Routing for Digital Microfluidic Biochips with Temporary Blockages
Autor: Oliver Keszöcze, Robert Wille, Rolf Drechsler
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: San Jose, 2014
Automated and Quality-driven Requirements Engineering
Autor: Rolf Drechsler, Mathias Soeken, Robert Wille,
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: San Jose, 2014
CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC
Autor: Hoang M. Le, Rolf Drechsler
Konferenz: Design and Verification Conference and Exhibition Europe (DVCon Europe)
Pdf | Referenz: Munich, Germany, 2014
metaSMT: A Unified Interface to SMT-LIB2
Autor: Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL'14)
Pdf | Referenz: pp. 1-6, Munich, Germany, 2014
Automating the Translation of Assertions Using Natural Language Processing Techniques
Autor: Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris and Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Munich, Germany, 2014
Automatic Refinement Checking for Formal System Models
Autor: Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Munich, Germany, 2014
Verifying Consistency between Activity Diagrams and Their Corresponding OCL Contracts
Autor: Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Munich, Germany, 2014
(Semi-)Automatic Translation of Legal Regulations to Formal Representations: Expanding the Horizon of EDA Applications
Autor: Oliver Keszöcze, Betina Keiner, Matthias Richter, Gottfried Antpöhler, Robert Wille
Konferenz: Special Session at the Forum on specification & Design Languages (FDL'14)
Pdf | Referenz: Munich, Germany, 2014
Quality Assessment for Requirements based on Natural Language Processing
Autor: Mathias Soeken, Nabila Abdessaied, Arman Allahyari-Abhari, Andi Buzo, Liana Musat, Georg Pelz, Rolf Drechsler
Konferenz: Special Session at the Forum on Specification & Design Languages (FDL'14)
Pdf | Referenz: Munich, Germany, 2014
Improving Coverage of Simulation-based Verification by Dedicated Stimuli Generation
Autor: Shuo Yang, Robert Wille, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 599-606, Verona, Italy, 2014
Determining Cases of Scenarios to Improve Coverage in Simulation-based Verication
Autor: Shuo Yang, Robert Wille, Rolf Drechsler
Konferenz: Symposium on Integrated Circuits and System Design (SBCCI)
Pdf | Referenz: Aracaju, Brazil, 2014
Validating SystemC Implementations Against Their Formal Specifications
Autor: Jannis Stoppe, Robert Wille, Rolf Drechsler
Konferenz: Symposium on Integrated Circuits and System Design (SBCCI)
Pdf | Referenz: Aracaju, Brazil, 2014
Self-Verification as the Key Technology for Next Generation Electronic Systems
Autor: Rolf Drechsler, Hoang M. Le, Mathias Soeken
Konferenz: Symposium on Integrated Circuits and System Design (SBCCI)
Pdf | Referenz: Aracaju, Brazil, 2014
Recent Advances in SAT-based ATPG: Non-Standard Fault Models, Multi Constraints and Optimization
Autor: Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer
Konferenz: International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
Pdf | Referenz: pp. 1-10, Santorini, Greece, 2014
Behaviour Driven Development for Tests and Verification
Autor: Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Konferenz: 8th International Conference on Tests & Proofs (TAP)
Pdf | Referenz: pp. 61-77, York, 2014
Filmstripping and Unrolling: A Comparison of Verification Approaches for UML and OCL Behavioral Models
Autor: Frank Hilken, Philipp Niemann, Martin Gogolla, Robert Wille
Konferenz: 8th International Conference on Tests & Proofs (TAP)
Pdf | Referenz: pp. 99-116, York, 2014
Generating SystemC Implementations for Clock Constraints specified in UML/MARTE CCSL
Autor: Judith Peters, Robert Wille, Rolf Drechsler
Konferenz: International Conference on Engineering of Complex Computer Systems (ICECCS)
Pdf | Referenz: pp. 116-125, Tianjin, China, 2014
Exact One-pass Synthesis of Digital Microfluidic Biochips
Autor: Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, 2014
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State-of-the-Art and Research Challenges
Autor: Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Gruettner, Thomas Kruse, Christoph Kuznik, Hoang M. Le, Andreas Mauderer, Wolfgang Mueller, Daniel Mueller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, Simon Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl
Konferenz: Design Automation Conference (DAC)
Referenz: pp. 113:1-6, San Francisco, 2014
Mapping NCV Circuits to Optimized Clifford+T Circuits
Autor: D. Michael Miller, Mathias Soeken, Rolf Drechsler
Konferenz: Reversible Computation
Pdf | Referenz: Kyoto, Japan, 2014
Equivalence Checking in Multi-level Quantum Systems
Autor: Philipp Niemann, Robert Wille, Rolf Drechsler
Konferenz: Reversible Computation
Pdf | Referenz: pp. 201-215, Kyoto, Japan, 2014
RevVis: Visualization of Structures and Properties in Reversible Circuits
Autor: Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler
Konferenz: Reversible Computation
Pdf | Referenz: Kyoto, Japan, 2014
Quantum Circuit Optimization by Hadamard Gate Reduction
Autor: Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
Konferenz: Reversible Computation
Pdf | Referenz: Kyoto, Japan, 2014
Optimizing DD-based Synthesis of Reversible Circuits using Negative Control Lines
Autor: Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Konferenz: IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 129-134, Warschau, Polen, 2014
Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques
Autor: Jan Malburg Niklas Krafczyk Görschwin Fey
Konferenz: IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 21-26, Warschau, Polen, 2014
SAT-Based Speedpath Debugging Using Waveforms
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 19th IEEE European Test Symposium (ETS)
Referenz: Paderborn, Germany, 2014
Verification of the Decimal Floating-Point Square Root Operation,
Autor: Amr Sayed Ahmed, Hossam Fahmy, Ulrich Kühne
Konferenz: 19th IEEE European Test Symposium,
Pdf | Referenz: Paderborn, Germany, 2014.
Optimization-based Multiple Target Test Generation for Highly Compacted Test Sets
Autor: Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Konferenz: 19th IEEE European Test Symposium (ETS)
Pdf | Referenz: Paderborn, Germany, 2014
A Cube Pairing Approach for Synthesis of ESOP based Reversible Circuit
Autor: Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler
Konferenz: 44rd International Symposium on Multiple-Valued Logic (ISMVL)
Referenz: Bremen, 2014
Future SoC Verification Methodology: UVM Evolution or Revolution?
Autor: Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev
Konferenz: Design, Automation and Test in Europe (DATE'14)
Pdf | Referenz: Dresden, Germany, 2014
Towards Verifying Determinism of SystemC Designs
Autor: Hoang M. Le, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE'14)
Pdf | Referenz: pp. 153:1-4, Dresden, Germany, 2014
Grammar-based Program Generation Based on Model Finding
Autor: Mathias Soeken, Rolf Drechsler
Konferenz: IEEE Design and Test Symposium 2013 (IDT)
Pdf | Referenz: Marrakesch, 2013
Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 22nd Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP)
Pdf | Referenz: Turin, Italy, 2014
Debug Automation for Synchronization Bugs at RTL
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 27th International Conference on VLSI Design
Pdf | Referenz: pp. 44-49, Mumbai, India, 2014
Optimal SWAP Gate Insertion for Nearest Neighbor Quantum Circuits
Autor: Robert Wille, Aaron Lye, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: pp. 489-494, Singapore, 2014
Efficient Synthesis of Quantum Circuits Implementing Clifford Group Operations
Autor: Philipp Niemann, Robert Wille, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: pp. 483-488, Singapore, 2014
Constraint-based Platform Variants Specification for Early System Verification
Autor: Andreas Burger, Alexander Viehl, Andreas Braun, Finn Haedicke, Daniel Große, Oliver Bringmann, Wolgang Rosenstiel
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: pp. 800-805, Singapore, 2014
Supporting Clinical Guidelines Using DL-Temporal Reasoning
Autor: Serge Autexier, Mohamed Bawadekji, Dieter Hutter, Regine Wolters
Konferenz: International Conference & Expo on Emerging Technologies for a Smarter World (CEWIT)
Referenz: Melville, NY, USA, 2013
Task-Driven Software Summarization
Autor: Dave Binkley, Dawn Lawrie, Emily Hill, Janet Burge, Ian Harris, Regina Hebig, Oliver Keszöcze, Karl Reed, John Slankas
Konferenz: 29th IEEE International Conference on Software Maintenance (ICSM)
Referenz: Eindhoven, The Netherlands, 2013
Analyse dynamischer Abhängigkeitsgraphen zum Debugging von Hardwaredesigns
Autor: Jan Malburg Alexander Finder Görschwin Fey
Konferenz: 7. ITG/GMM/GI-Fachtagung Zuverlässigkeit und Entwurf (ZuE2013)
Pdf | Referenz: pp. 59-66, Dresden, Germany, 2013
Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill
Autor: Stephan Eggersglüß
Konferenz: 22nd IEEE Asian Test Symposium (ATS)
Pdf | Referenz: pp. 31-16, Yilan, Taiwan, 2013
Self-Adaptive Evolutionary Many-Objective Optimization based on Relation Epsilon-Preferred
Autor: Nicole Drechsler
Konferenz: International Conference on Soft Computing MENDEL
Pdf | Referenz: Brno, Czech Republic, 2013
Improved SAT-based ATPG: More Constraints, Better Compaction
Autor: Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Konferenz: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Pdf | Referenz: pp. 85-90, San Jose, USA, 2013
A Compact and Efficient SAT Encoding for Quantum Circuits
Autor: Robert Wille, Nils Przigoda, Rolf Drechsler
Konferenz: IEEE Africon
Pdf | Referenz: Mauritius, 2013
Exploiting Reversibility in the Complete Simulation of Reversible Circuits
Autor: Robert Wille, Simon Stelter, Rolf Drechsler
Konferenz: IEEE Africon
Pdf | Referenz: Mauritius, 2013
Cone of Influence Analysis at the Electronic System Level Using Machine Learning
Autor: Jannis Stoppe, Robert Wille, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Santander, Spain, 2013
Minimal Stimuli Generation in Simulation-based Verification
Autor: Shuo Yang, Robert Wille, Daniel Große and Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Santander, Spain, 2013
The SyReC Hardware Description Language: Enabling Scalable Synthesis of Reversible Circuits
Autor: Robert Wille, Rolf Drechsler
Konferenz: International Midwest Symposium on Circuits and Systems (MWSCAS)
Referenz: Columbus, USA, 2013
Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred
Autor: Nicole Drechsler, André Sülflow, Rolf Drechsler
Konferenz: International Conference on Evolutionary Computation Theory and Applications (ECTA)
Referenz: Vilamoura, Portugal, 2013
Data Extraction from SystemC Designs using Debug Symbols and the SystemC API
Autor: Jannis Stoppe, Robert Wille, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Natal, Brazil, 2013
On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure
Autor: Philipp Niemann, Robert Wille, Rolf Drechsler
Konferenz: Reversible Computation
Pdf | Referenz: pp. 125-140, Victoria, Canada, 2013
Exploiting Negative Control Lines in the Optimization of Reversible Circuits
Autor: Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Konferenz: Reversible Computation
Pdf | Referenz: pp. 209-220, Victoria, Canada, 2013
Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure
Autor: Arighna Deb, Debesh Kumar Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler
Konferenz: Reversible Computation
Pdf | Referenz: pp. 182-195, Victoria, Canada, 2013
White Dots do Matter: Rewriting Reversible Logic Circuits
Autor: Mathias Soeken, Michael Kirkedal Thomsen
Konferenz: Reversible Computation
Pdf | Referenz: pp. 196-208, Victoria, Canada, 2013
Reducing the Depth of Quantum Circuits Using Additional Lines
Autor: Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler
Konferenz: Reversible Computation
Pdf | Referenz: pp. 221-233, Victoria, Canada, 2013
Hardware-Software Co-Visualization: Developing Systems in the Holodeck
Autor: Rolf Drechsler, Mathias Soeken
Konferenz: 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 1-4, Karlovy Vary, Czech Republic, 2013
Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications
Autor: Alexander Finder, Jan-Philipp Witte, Görschwin Fey
Konferenz: 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Karlovy Vary, Czech Republic, 2013
Efficient Automated Speedpath Debugging
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 48-53, Karlovy Vary, Czech Republic, 2013
Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation
Autor: Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: pp. 116:1-6 Austin, Texas, 2013
Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits
Autor: Robert Wille, Hongyan Zhang, Rolf Drechsler
Konferenz: 43rd International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 29-34, Toyama, 2013
Debugging of Reversible Circuits using πDDs
Autor: Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler
Konferenz: 43rd International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 316-321, Toyama, Japan, 2013
Exact Template Matching Using Boolean Satisfiability
Autor: Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler
Konferenz: 43rd International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 328-333, Toyama, Japan, 2013
Synchronized Debugging across Different Abstraction Levels in System Design
Autor: Rolf Drechsler, Daniel Große, Hoang M. Le, André Sülflow
Konferenz: embedded world Conference 2013
Pdf | Referenz: Nürnberg, 2013
Scalable Fault Localization for SystemC TLM Designs
Autor: Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE'13)
Pdf | Referenz: pp. 35-38, Grenoble, France, 2013
Reliability Analysis Reloaded: How Will We Survive?
Autor: Robert Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda
Konferenz: Design, Automation and Test in Europe (DATE'13)
Pdf | Referenz: Grenoble, France, 2013
Tuning Dynamic Data Flow Analysis to Support Design Understanding
Autor: Jan Malburg, Alexander Finder, Görschwin Fey
Konferenz: Design, Automation and Test in Europe (DATE'13)
Pdf | Referenz: pp. 1179-1184, Grenoble, France, 2013
Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis
Autor: Heinz Riener, Stefan Frehse, Görschwin Fey
Konferenz: Design, Automation and Test in Europe (DATE'13)
Pdf | Referenz: pp. 939-943, Grenoble, France, 2013
Determining Relevant Model Elements for the Verification of UML/OCL Specifications
Autor: Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1189-1192, Grenoble, France, 2013
Towards a Generic Verification Methodology for System Models
Autor: Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1193-1196, Grenoble, France, 2013
Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines
Autor: Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: pp. 145-150. Yokohama, Japan, 2013
An Evolutionary Approach to Reversible Logic Synthesis using Output Permutation
Autor: Kamalika Datta, Indranil Sen Gupta, Hafizur Rahaman, Rolf Drechsler
Konferenz: IEEE Design and Test Symposium 2012 (IDT)
Pdf | Referenz: Doha, 2012
Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems
Autor: Rolf Drechsler, Mathias Soeken, Robert Wille
Konferenz: IEEE Design and Test Symposium 2012 (IDT)
Pdf | Referenz: Doha, 2012
Synthesis of Reversible Circuits Using Decision Diagrams
Autor: Rolf Drechsler, Robert Wille
Konferenz: International Symposium on Electronic System Design (ISED)
Pdf | Referenz: pp. 1-5, Kolkata, WB, India, 2012
SyDe - a New Graduate School for System Design in an Excellent Setting
Autor: Ulrich Kühne, Rolf Drechsler
Konferenz: Informatics Europe (ECSS)
Referenz: Barcelona, 2012
From Requirements and Scenarios to ESL Design in SystemC
Autor: Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: International Symposium on Electronic System Design (ISED)
Pdf | Referenz: pp. 183-187, Kolkata, WB, India, 2012
FoREnSiC - An Automatic Debugging Environment for C Programs
Autor: Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
Konferenz: Haifa Verification Conference (HVC)
Pdf | Referenz: Haifa, 2012
Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization
Autor: Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty
Konferenz: 21st IEEE Asian Test Symposium (ATS)
Pdf | Referenz: pp. 290-295, Niigata, Japan, 2012
Automated Post-Silicon Debugging of Failing Speedpaths
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 21st IEEE Asian Test Symposium (ATS)
Pdf | Referenz: pp. 13-18, Niigata, Japan, 2012
The System Verification Methodology for Advanced TLM Verification
Autor: Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, Volkan Esen
Konferenz: International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
Pdf | Referenz: pp. 313-322, Tampere, 2012
Complete and Effective Robustness Checking by Means of Interpolation
Autor: Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav and Rolf Drechsler
Konferenz: Formal Methods in Computer-Aided Design (FMCAD'12)
Pdf | Referenz: Cambridge, UK, 2012, page 82-90
Completeness-Driven Development
Autor: Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille
Konferenz: International Conference on Graph Transformation
Pdf | Referenz: pp. 38-50, Bremen, 2012
CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC
Autor: Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: International Symposium on System-on-Chip (SoC)
Pdf | Referenz: pp. 1-7, Tampere, 2012
Distributed and Coupled Electrothermal Model of Power Semiconductor Devices
Autor: G. Belkacem, D. Labrousse, S. Lefebvre, P.-Y. Joubert, U. Kühne, L. Fribourg, R. Soulat, E. Florentin, C. Rey
Konferenz: International Conference on Renewable Energies and Vehicular Technology
Referenz: Hammamet, 2012
Hardware-Software-Co-Synthese zur Verbesserung der Fehlertoleranz
Autor: Stefan Frehse, Heinz Riener, Görschwin Fey
Konferenz: 6. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE'12)
Pdf | Referenz: pp. 90-96, Bremen, Germany, 2012
Application of Timing Variation Modeling to Speedpath Diagnosis
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 4th International Conference on System, Software, SoC and Silicon Debug (S4D)
Pdf | Referenz: pp. 34-37, Vienna, Austria, 2012
Localizing Features of ESL Models for Design Understanding
Autor: Marc Michael, Daniel Große, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Vienna, 2012
Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing
Autor: Rolf Drechsler, Mathias Soeken, Robert Wille
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: pp. 53-58, Vienna, Austria, 2012
Parametric Analysis of Hybrid Systems Using HyMITATOR (Tool Presentation)
Autor: Étienne André, Ulrich Kühne
Konferenz: International Conference on Integrated Formal Methods (iFM)
Referenz: Pisa, Italy, 2012
IMITATOR 2.5: A Tool for Analyzing Robustness in Scheduling Problems (Tool Paper)
Autor: Étienne André, Laurent Fribourg, Ulrich Kühne, Romain Soulat
Konferenz: International Symposium on Formal Methods (FM)
Referenz: Paris, France, 2012
Model-Based Diagnosis versus Error Explanation
Autor: Heinz Riener, Görschwin Fey
Konferenz: 10th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'12)
Pdf | Referenz: pp. 43-52, Arlington, Virginia, USA, 2012
Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic
Autor: Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: pp. 213-218, Amherst, USA, 2012
On Modeling and Evaluation of Logic Circuits Under Timing Variations
Autor: Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Konferenz: 15th Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 431-436, Izmir, Turkey, 2012
Coverage-driven Stimuli Generation
Autor: Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler
Konferenz: 15th Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Izmir, Turkey, 2012
Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology
Autor: Rolf Drechsler, Robert Wille
Konferenz: International Symposium on VLSI Design and Test (VDAT)
Pdf | Referenz: Shibpur, India, 2012
Assisted Behavior Driven Development Using Natural Language Processing
Autor: Mathias Soeken, Robert Wille, Rolf Drechsler
Konferenz: 50th International Conference on Objects, Models, Components, Patterns (TOOLS)
Pdf | Referenz: pp. 269-287, Prague, Czech Republic, 2012
A New SAT-based ATPG for Generating Highly Compacted Test Sets
Autor: Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
Konferenz: 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 230-235, Tallinn, Estonia, 2012
Automated Debugging from Pre-Silicon to Post-Silicon
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 324-329, Tallinn, Estonia, 2012
Automated Feature Localization for Hardware Designs using Coverage Metrics
Autor: Jan Malburg, Alexander Finder, Görschwin Fey
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: pp. 941-946, San Francisco, 2012
Realizing Reversible Circuits Using a New Class of Quantum Gates
Autor: Zahra Sasanian, Robert Wille, Michael Miller
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, 2012
Functional Analysis of Circuits Under Timing Variations
Autor: Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Konferenz: 17th IEEE European Test Symposium (ETS)
Pdf | Referenz: pp. 177, Annecy, France, 2012
Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits
Autor: Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler
Konferenz: 42nd International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 173-178, Victoria, Canada, 2012
A Synthesis Flow for Sequential Reversible Circuits
Autor: Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler
Konferenz: 42nd International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 299-304, Victoria, Canada, 2012
Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines
Autor: Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Konferenz: 42nd International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 69-74, Victoria, Canada, 2012
Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis
Autor: Robert Wille, Rolf Drechsler, Christof Oswald, Alberto Garcia-Ortiz
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Dresden, 2012
A Guiding Coverage Metric for Formal Verification
Autor: Finn Haedicke, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Dresden, 2012
Eliminating Invariants in UML/OCL Models
Autor: Mathias Soeken, Robert Wille, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1142-1145, Dresden, 2012
Debugging of Inconsistent UML/OCL Models
Autor: Robert Wille, Mathias Soeken, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1078-1083, Dresden, 2012
Synthesis of Reversible Circuits with Minimal Lines for Large Functions
Autor: Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: pp. 85-92, Sydney, 2012
Improved Fault Diagnosis for Reversible Circuits
Autor: Hongyan Zhang, Robert Wille, Rolf Drechsler
Konferenz: Asian Test Symposium (ATS)
Pdf | Referenz: New Delhi, 2011
Automated Post-Silicon Debugging of Design Bugs
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 3rd International Conference on System, Software, SoC and Silicon Debug (S4D)
Pdf | Referenz: pp. 67-71, Munich, Germany, 2011
Hochoptimierter Ablauf zur Robustheitsprüfung
Autor: Stefan Frehse, Finn Haedicke, Melanie Diepenbeck, Görschwin Fey, Rolf Drechsler
Konferenz: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)
Pdf | Referenz: Hamburg-Harburg, 2011
Analyzing Dependability Measures at the Electronic System Level
Autor: Marc Michael, Daniel Große, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: pp. 1-8, Oldenburg, 2011
Efficient Realization of Control Logic in Reversible Circuits
Autor: Sebastian Offermann, Robert Wille, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Oldenburg, 2011
Determining Minimal Testsets for Reversible Circuits Using Boolean Satisfiability
Autor: Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler
Konferenz: 10th IEEE Africon
Pdf | Referenz: Livingstone, 2011
Automated Design Debugging in a Testbench-Based Verification Environment
Autor: Mehdi Dehbashi, André Sülflow, Görschwin Fey
Konferenz: 14th Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 479-486, Oulu, Finland, 2011
Best Paper Candidate
VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification
Autor: Robert Wille, André Sülflow, Rolf Drechsler
Konferenz: International Conference on Modeling, Simulation and Visualization Methods (MSV)
Pdf | Referenz: pp. 36-39, Las Vegas, 2011
Orchestrated Multi-level Information Flow Analysis to Understand SoCs
Autor: Görschwin Fey
Konferenz: 48th Design Automation Conference (DAC)
Pdf | Referenz: San Diego, USA, 2011
Promotion video on YouTube
ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization
Autor: Robert Wille, Hongyan Zhang, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: pp. 120-125, Chennai, 2011
An Introduction to Reversible Circuit Design
Autor: Robert Wille
Konferenz: Saudi International Electronics, Communications and Photonics Conference (SIECPC)
Referenz: Riyadh, 2011
Encoding OCL Data Types for SAT-based Verification of UML/OCL Models
Autor: Mathias Soeken, Robert Wille, Rolf Drechsler
Konferenz: 5th International Conference on Tests & Proofs (TAP)
Pdf | Referenz: pp. 152-170, Zurich, 2011
Latency Analysis for Sequential Circuits
Autor: Alexander Finder, André Sülflow, Görschwin Fey
Konferenz: 16th IEEE European Test Symposium (ETS)
Pdf | Referenz: pp. 129-134, Trondheim, 2011
Automatic Property Generation for the Formal Verification of Bus Bridges
Autor: Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Konferenz: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 417-422, Cottbus, 2011
TLM Protocol Compliance Checking at the Electronic System Level
Autor: Mohamed Bawadekji, Daniel Große, Rolf Drechsler
Konferenz: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 435-440, Cottbus, 2011
Designing a RISC CPU in Reversible Logic
Autor: Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Konferenz: 41st International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 170-175, Tuusula, 2011
From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits
Autor: Rolf Drechsler, Robert Wille
Konferenz: 41st International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 78-85, Tuusula, 2011
Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates
Autor: D. Michael Miller, Robert Wille, Z. Sasanian
Konferenz: 41st International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 288-293, Tuusula, 2011
Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction
Autor: Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 223-228, Lausanne, 2011
Verifying Dynamic Aspects of UML Models
Autor: Mathias Soeken, Robert Wille, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1077-1082, Grenoble, 2011
Determining the Minimal Number of Lines for Large Reversible Circuits
Autor: Robert Wille, Oliver Keszöcze, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1204—1207, Grenoble, 2011
As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
Autor: Stephan Eggersglüß, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1291-1296, Grenoble, 2011
Automatic Fault Localization for Programmable Logic Controllers
Autor: Andre Sülflow, Rolf Drechsler
Konferenz: Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT)
Pdf | Referenz: pp. 247-256, Braunschweig, 2010
Automated Formal Verification of Processors Based on Architectural Models
Autor: Ulrich Kühne, Sven Beyer, Jörg Bormann, John Barstow
Konferenz: Formal Methods in Computer Aided Design (FMCAD)
Referenz: Lugano, Switzerland, 2010
Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability
Autor: Stephan Eggersglüß, Rolf Drechsler
Konferenz: International Test Conference (ITC)
Pdf | Referenz: pp. 1-10, Austin, 2010
Polynomial Datapath Optimization using Constraint Solving and Formal Modelling
Autor: Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler
Konferenz: IEEE/ACM International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: San Jose, 2010
SyReC: A Programming Language for Synthesis of Reversible Circuits
Autor: Robert Wille, Sebastian Offermann, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: pp. 184-189, Southampton, 2010
Received Best Paper Award
Evaluating Debugging Algorithms from a Qualitative Perspective
Autor: Alexander Finder, Görschwin Fey
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: pp. 37-42, Southampton, 2010
Kompositionelle Formale Robustheitsprüfung
Autor: Stefan Frehse, Görschwin Fey
Konferenz: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)
Referenz: Wildbad Kreuth, 2010
Proving Transaction and System-level Properties of Untimed SystemC TLM Designs
Autor: Daniel Große, Hoang M. Le, Rolf Drechsler
Konferenz: International Conference on Formal Methods and Models for Codesign (MEMOCODE)
Pdf | Referenz: pp. 113-122, Grenoble, 2010
RobuCheck: A Robustness Checker for Digital Circuits
Autor: Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 226-231, Lille, 2010
Reducing the Number of Lines in Reversible Circuits
Autor: Robert Wille, Mathias Soeken, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: pp. 647-652, Anaheim, 2010
Graph Transformation Units Guided by a SAT Solver
Autor: Hans-Jörg Kreowski, Susanne Kuske, Robert Wille
Konferenz: International Conference on Graph Transformations (ICGT)
Referenz: pp. 27-42, Enschede, 2010
Synthesizing Multiplier in Reversible Logic
Autor: Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Konferenz: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 335-340, Vienna, 2010
Window Optimization of Reversible and Quantum Circuits
Autor: Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Konferenz: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 431-435, Vienna, 2010
A Better-Than-Worst-Case Robustness Measure
Autor: Stefan Frehse, Görschwin Fey, Rolf Drechsler
Konferenz: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 78-83, Vienna, 2010
Enhancing Debugging of Multiple Missing Control Errors in Reversible Logic
Autor: Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 465-470, Rhode Island, 2010
Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs
Autor: Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler
Konferenz: 15th IEEE European Test Symposium (ETS)
Pdf | Referenz: pp. 176-181, Prag, 2010
An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions
Autor: Alexander Finder, Rolf Drechsler
Konferenz: 40th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 150-155, Barcelona, 2010
Efficient Simulation-based Debugging of Reversible Logic
Autor: Stefan Frehse, Robert Wille, Rolf Drechsler
Konferenz: 40th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 156-161, Barcelona, 2010
Reducing Reversible Circuit Cost by Adding Lines
Autor: D. Michael Miller, Robert Wille, Rolf Drechsler
Konferenz: 40th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 217-222, Barcelona, 2010
Efficient Test Generation with Maximal Crosstalk-Induced Noise using Unconstrained Aggressor Excitation
Autor: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS)
Pdf | Referenz: pp. 649-652, Paris, 2010
Using QBF to Increase Accuracy of SAT-Based Debugging
Autor: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS)
Pdf | Referenz: pp.641-644, Paris, 2010
Verifying UML/OCL Models Using Boolean Satisfiability
Autor: Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1341-1344, Dresden, 2010, 2010
Timing Arc Based Logic Analysis for False Noise Reduction
Autor: Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler
Konferenz: IEEE/ACM International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: pp. 225-230, San Jose, 2009
Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen
Autor: Andre Sülflow, Stefan Frehse, Görschwin Fey, Rolf Drechsler
Konferenz: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)
Pdf | Referenz: pp. 45-52, Stuttgart, 2009
Structural Heuristics for SAT-based ATPG
Autor: Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler
Konferenz: 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009)
Pdf | Referenz: pp. 77-82, Florianópolis, 2009
Speeding up SAT-based ATPG using Dynamic Clause Activation
Autor: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Konferenz: 18th Asian Test Symposium (ATS'09)
Pdf | Referenz: pp. 177-182, Taichung, 2009
Deterministc Algorithms for ATPG under Leakage Constraints
Autor: Görschwin Fey
Konferenz: 18th Asian Test Symposium (ATS'09)
Pdf | Referenz: Taichung, 2009
Automatic Debugging of System-on-a-Chip Designs
Autor: Frank Rogin, Rolf Drechsler, Steffen Rülke
Konferenz: IEEE International SOC Conference (SOCC)
Pdf | Referenz: Belfast, 2009
SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults
Autor: Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada
Konferenz: European Conference on Circuit Theory and Design
Referenz: Antalya, 2009
SMT-based Stimuli Generation in the SystemC Verification Library
Autor: Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: pp. 1-6, Sophia Antipolis, 2009
Robustness Check for Multiple Faults using Formal Techniques
Autor: Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 85-90, Patras, 2009
Synthesizing Reversible Circuits for Irreversible Functions
Autor: D. Michael Miller, Robert Wille, Gerhard W. Dueck
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 749-756, Patras, 2009
BDD-based Synthesis of Reversible Logic for Large Functions
Autor: Robert Wille, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: pp. 270-275, San Francisco, 2009
Computing Bounds for Fault Tolerance using Formal Techniques
Autor: Görschwin Fey, Andre Sülflow, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: pp. 190-195, San Francisco, USA, 2009
Generating an Efficient Instruction Set Simulator from a Complete Property Suite
Autor: Ulrich Kühne, Sven Beyer, Christian Pichler
Konferenz: IEEE/IFIP International Symposium on Rapid System Prototyping (RSP)
Pdf | Referenz: pp. 109-115, Paris, 2009
WoLFram - A Word Level Framework for Formal Verification
Autor: Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
Konferenz: IEEE/IFIP International Symposium on Rapid System Prototyping (RSP)
Pdf | Referenz: pp. 11-17, Paris, 2009
A Fast Untestability Proof for SAT-based ATPG
Autor: Daniel Tille, Rolf Drechsler
Konferenz: 12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Pdf | Referenz: pp. 38-43, Liberec, 2009
Increasing Robustness of SAT-based Delay Test Generation using Efficient Dynamic Learning Techniques
Autor: Stephan Eggersglüß, Rolf Drechsler
Konferenz: 14th IEEE European Test Symposium (ETS)
Pdf | Referenz: pp. 81-86, Sevilla, 2009
Contradictory Antecedent Debugging in Bounded Model Checking
Autor: Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 173-176, Boston, 2009
Evaluation of Cardinality Constraints on SMT-based Debugging
Autor: Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler
Konferenz: 39th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 298-303, Naha, Okinawa, 2009
Equivalence Checking of Reversible Circuits
Autor: Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Konferenz: 39th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 324-330, Naha, Okinawa, 2009
Approximate BDD Minimization by Weighted A*
Autor: Rüdiger Ebendt, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'09)
Referenz: Taipei, 2009
Overcoming Limitations of the SystemC Data Introspection
Autor: Christian Genz, Rolf Drechsler
Konferenz: Design Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 590-593, Nice, 2009
Property Analysis and Design Understanding
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1246-1249, Nice, 2009
Debugging of Toffoli Networks
Autor: Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1284-1289, Nice, 2009
Increasing the Accuracy of SAT-based Debugging
Autor: Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1326-1332, Nice, 2009
Reversible Logic Synthesis with Output Permutation
Autor: Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Konferenz: 22nd International Conference on VLSI Design
Pdf | Referenz: pp. 189-194, New Delhi, 2009
Formaler Nachweis der Fehlertoleranz von Schaltkreisen
Autor: Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Konferenz: GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008)
Pdf | Referenz: pp. 75-82, Ingolstadt, 2008
Targeting Leakage Constraints during ATPG
Autor: Görschwin Fey, Sathoshi Komatsu, Yasuo Furukawa, Masahiro Fujita
Konferenz: Asian Test Symposium (ATS)
Pdf | Referenz: pp. 225-230, 2008
Fault Effects in FlexRay-Based Networks with Hybrid Topology
Autor: Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi
Konferenz: 3rd IEEE International Conference on Availability, Reliability and Security (ARES)
Pdf | Referenz: pp. 491-496, Barcelona, Spain, 2008
Verification of PLC Programs using Formal Proof Techniques
Autor: Andre Sülflow, Rolf Drechsler
Konferenz: Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
Pdf | Referenz: pp. 43-50, Budapest, 2008
Efficient Formal Verification of Track Vacancy Detection Sections
Autor: Sebastian Kinder und Rolf Drechsler
Konferenz: Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
Referenz: pp. 233-240, Budapest, 2008
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking
Autor: Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 542-549, Parma, 2008
Contradiction Analysis for Constraint-based Random Simulation
Autor: Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: pp. 130-135, Stuttgart, 2008
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
Autor: Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: pp. 411-416, Montpellier, 2008
RevLib: An Online Resource for Reversible Functions and Reversible Circuits
Autor: Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler
Konferenz: 38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Pdf | Referenz: pp. 220-225, Dallas
RevLib is available at www.revlib.org, 2008
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don’t Cares
Autor: Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Konferenz: 38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Pdf | Referenz: pp. 214-219, Dallas
Received IEEE Young Researcher Award, 2008
On the Influence of Boolean Encodings in SAT-based ATPG for Path Delay Faults
Autor: Stephan Eggersglüß, Rolf Drechsler
Konferenz: 38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Pdf | Referenz: pp. 94-99, Dallas, 2008
Using Unsatisfiable Cores to Debug Multiple Design Errors
Autor: Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Konferenz: IEEE Great Lakes Symposium on VLSI (GLSVLSI'08)
Pdf | Referenz: pp. 77-82, Orlando, 2008
Process Variations Aware Robust on-Chip Bus Architecture Synthesis for MPSoCs
Autor: Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'08)
Referenz: Seattle, 2008
A Basis for Formal Robustness Checking
Autor: Görschwin Fey, Rolf Drechsler
Konferenz: International Symposium on Quality of Electronic Design (ISQED)
Pdf | Referenz: San Jose, 2008
Adaptive Branch and Bound using SAT to Estimate False Crosstalk
Autor: Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
Konferenz: International Symposium on Quality of Electronic Design (ISQED)
Referenz: San Jose, 2008
Automatic Generation of Complex Properties for Hardware Designs
Autor: Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler Steffen Rülke
Konferenz: Design, Automation, and Test in Europe (DATE)
Pdf | Referenz: Munich, 2008
Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs
Autor: Sujan Pandey, Rolf Drechsler
Konferenz: Design, Automation, and Test in Europe (DATE)
Pdf | Referenz: Munich, 2008
Quantified Synthesis of Reversible Logic
Autor: Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große
Konferenz: Design, Automation, and Test in Europe (DATE)
Pdf | Referenz: pp. 1015-1020, Munich, 2008
Robust On-Chip Bus architecture Synthesis for MPSoCs Under Random Tasks Arrival
Autor: Sujan Pandey, Rolf Drechsler
Konferenz: 13th Asia and South Pacific Design Automation Conference, (ASP-DAC 2008)
Pdf | Referenz: Seoul, 2008
Fast Exact Toffoli Network Synthesis of Reversible Logic
Autor: Robert Wille, Daniel Große
Konferenz: IEEE International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: pp. 60-64, San Jose, 2007
SWORD: A SAT like Prover Using Word Level Information
Autor: Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
Konferenz: IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC)
Pdf | Referenz: pp. 88-93, Atlanta, 2007
Co-Synthesis of Custom On-Chip Bus and Memory for MPSoC Architectures
Autor: Sujan Pandey, Christian Genz, Rolf Drechsler
Konferenz: IFIP International Conference on Very Large Scale Integration Systems and Systems on Chip (VLSI-SoC)
Pdf | Referenz: pp. 304-307, Atlanta, 2007
Improving Test Pattern Compactness in SAT-based ATPG
Autor: Stephan Eggersglüß, Rolf Drechsler
Konferenz: 16th Asian Test Symposium (ATS’07)
Pdf | Referenz: pp. 445-450, Beijing, 2007
An Integrated SystemC Debugging Environment
Autor: Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: pp. 140-145, Barcelona, 2007
Measuring the Quality of a SystemC Testbench by using Code Coverage Technqiues
Autor: Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: pp. 146-151, Barcelona
Received Best Paper Award, 2007
Evaluation of Babbling Idiot Failures in FlexRay-Based Networks
Autor: Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Mojtaba Amiri
Konferenz: 7th IFAC International Conference on Fieldbuses and Networks in Industrial and Embedded Systems (FET)
Pdf | Referenz: pp. 399-406, Toulouse, France, 2007
Assessment of Message Missing Failures in FlexRay-Based Networks
Autor: Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Navid Farazmand
Konferenz: 13th IEEE/IFIP Pacific Rim International Symposium on Dependable Computing (PRDC)
Pdf | Referenz: pp. 191-194, Melbourne, Australia, 2007
Proving Completeness of Properties in Formal Verification of Counting Heads for Railways
Autor: Sebastian Kinder and Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools

Pdf | Referenz: Lübeck, 2007
On the Construction of Small Fully Testable Circuits with Low Depth
Autor: Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools

Pdf | Referenz: Lübeck, 2007
Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?
Autor: Rolf Drechsler, Andreas Breiter
Konferenz: 2nd International Conference on Software and Data Technologies
Pdf | Referenz: Barcelona, 2007
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Autor: Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel
Konferenz: Fifth ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2007)
Pdf | Referenz: pp. 181-187, Nice, 2007
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Pdf | Referenz: pp. 165-170, Porto Alegre, 2007
Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^m) in SystemC
Autor: Andre Sülflow, Rolf Drechsler
Konferenz: 37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Pdf | Referenz: pp. 42, Oslo, 2007
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
Autor: Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler
Konferenz: 37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Pdf | Referenz: Oslo, 2007
Experimental Studies on SAT-based ATPG for Gate Delay Faults
Autor: Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Konferenz: 37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Pdf | Referenz: Oslo, 2007
Visualization of SystemC Designs
Autor: Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS)
Pdf | Referenz: pp. 413-416, New Orleans, 2007
SAT-based ATPG for Path Delay Faults in Sequential Circuits
Autor: Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'07)
Pdf | Referenz: pp. 3671-3674, New Orleans, 2007
Improvements for Constraint Solving in the SystemC Verification Library
Autor: Daniel Große, Rüdiger Ebendt, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 493-496, Stresa, 2007
Exact SAT-based Toffoli Network Synthesis
Autor: Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 96-101, Stresa, 2007
Ein formaler Ansatz zum Robustheitsnachweis
Autor: Görschwin Fey, Rolf Drechsler
Konferenz: Zuverlässigkeit und Entwurf
Pdf | Referenz: München, 2007
Robust Multi-Objective Optimization in High Dimensional Spaces
Autor: André Sülflow, Nicole Drechsler, Rolf Drechsler
Konferenz: Fourth International Conference on Evolutionary Multi-Criterion Optimization
Pdf | Referenz: pp. 715-726, Matsushima, 2007
Estimating Functional Coverage in Bounded Model Checking
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1176-1181, Nice, 2007
Modeling and Formal Verification of Counting Heads for Railways
Autor: Sebastian Kinder, Rolf Drechsler
Konferenz: Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2007)
Pdf | Referenz: Braunschweig, 2007
Reusing Learned Information in SAT-based ATPG
Autor: Görschwin Fey, Tim Warode, Rolf Drechsler
Konferenz: 20th International Conference on VLSI Design
Pdf | Referenz: Bangalore, 2007
Automatic Fault Localization for Property Checking
Autor: Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Konferenz: Haifa Verification Conference
Pdf | Referenz: Haifa, 2006
Technical Documentation of Software and Hardware in Embedded Systems
Autor: Beate Muranko, Rolf Drechsler
Konferenz: IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2006)
Pdf | Referenz: Nice, France, 2006
A Framework for Quasi-Exact Optimization using Relaxed Best-First Search
Autor: Rüdiger Ebendt, Rolf Drechsler
Konferenz: 29th Annual German Conference on Artificial Intelligence (KI'06)
Pdf | Referenz: Bremen, 2006, 2006
Non-Intrusive High-level SystemC Debugging
Autor: Frank Rogin, Erhard Fehlauer, Steffen Ruelke, Sebastian Ohnewald, Thomas Berndt
Konferenz: Forum on specification & Design Languages (FDL)
Referenz: Darmstadt, 2006
HW/SW Co-Verification of Embedded Systems using Bounded Model Checking
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 43-48, Philadelphia, 2006
Efficiency of Multiple-Valued Encoding in SAT-based ATPG
Autor: Görschwin Fey, Junhao Shi, Rolf Drechsler
Konferenz: IEEE International Symposium on Multiple-Valued Logic (ISMVL '06)
Pdf | Referenz: Singapore, 2006
Integrating Observability Don't Cares in All-Solution SAT Solvers
Autor: Sean Safarpour, Andreas Veneris, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'06)
Pdf | Referenz: Kos, 2006
On the Sensitivity of BDDs with Respect to Path-Related Objective Functions
Autor: Rüdiger Ebendt, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'06)
Pdf | Referenz: Kos, 2006
System Exploration of SystemC Designs
Autor: Christian Genz, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: pp. 335-340, Karlsruhe, 2006
On the Relation Between Simulation-based and SAT-based Diagnosis
Autor: Görschwin Fey, Sean Safarpour, Andreas Veneris, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1139-1144, Munich, 2006
Efficient Minimization of Fully Testable 2-SPP Networks
Autor: Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1300-1305, Munich, 2006
Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks
Autor: Görschwin Fey, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1225-1226, Munich, 2006
An Integrated Approach for Combining BDD and SAT Provers
Autor: Rolf Drechsler, Görschwin Fey, Sebastian Kinder
Konferenz: International Conference on VLSI Design
Pdf | Referenz: Hyderabad, 2006
Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits
Autor: Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
Konferenz: International Conference on ASIC (ASICON 2005)
Pdf | Referenz: pp. 967-970, Shanghai, 2005
Post-Verification Debugging of Hierarchical Designs
Autor: Moayad Ali, Sean Safarpour, Andreas Veneris, Magdy Abadir, Rolf Drechsler
Konferenz: IEEE International Conference on Computer Aided Design (ICCAD'05)
Pdf | Referenz: pp. 871-876, San Jose, 2005
Exact BDD Minimization for Path-Related Objective Functions
Autor: Rüdiger Ebendt, Rolf Drechsler
Konferenz: IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2005)
Referenz: pp. 525-530, Perth, 2005
Acceleration of SAT-based Iterative Property Checking
Autor: Daniel Große, Rolf Drechsler
Konferenz: Correct Hardware Design and Verification Methods (CHARME)
Pdf | Referenz: pp. 349-353, Saarbrücken, 2005
Quasi-Exact BDD Minimization using Relaxed Best-First Search
Autor: Rüdiger Ebendt and Rolf Drechsler
Konferenz: IEEE Annual Symposium on VLSI (ISVLSI '05)
Pdf | Referenz: pp. 59-64, Tampa, Florida, 2005
PASSAT: Efficient SAT-based Test Pattern Generation
Autor: Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Konferenz: IEEE Annual Symposium on VLSI (ISVLSI '05)
Referenz: pp.212-217, Tampa, Florida, 2005
Controlling the Memory During Manipulation of Word-Level Decision Diagrams
Autor: Sebastian Kinder, Görschwin Fey, Rolf Drechsler
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL 2005)
Referenz: pp. 250-255, Calgary, 2005
Utilizing Don't Care States in SAT-based Bounded Sequential Problems
Autor: Sean Safarpour, Görschwin Fey, Andreas Veneris, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI'05)
Pdf | Referenz: Chicago, 2005
CheckSyC: An Efficient Property Checker for RTL SystemC Designs
Autor: Daniel Große, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'05)
Pdf | Referenz: pp. 4167-4170, Kobe, 2005
Bridging Fault Testability of BDD Circuits
Autor: Junhao Shi, Görschwin Fey, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005)
Pdf | Referenz: pp. 188-191 Shanghai, 2005
Lower Bounds for Dynamic BDD Reordering
Autor: Rüdiger Ebendt and Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005)
Pdf | Referenz: pp. 579-582, Shanghai, 2005
Automated Verification For Train Control Systems
Autor: Jan Peleska, Daniel Große, Anne E. Haxthausen, Rolf Drechsler
Konferenz: Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2004)
Pdf | Referenz: pp. 252-265, Braunschweig, 2004
Debugging Sequential Circuits Using Boolean Satisfiability
Autor: Moayad Ali, Andreas Veneris, Sean Safarpour, Magdy Abadir, Rolf Drechsler, Alexander Smith
Konferenz: IEEE International Conference on Computer Aided Design (ICCAD'04)
Pdf | Referenz: pp. 204-209, San Jose, 2004
BDD Circuit Optimization for Path Delay Fault Testability
Autor: Görschwin Fey, Junhao Shi, Rolf Drechsler
Konferenz: Euromicro Symposium on Digital System Design (DSD'2004)
Referenz: pp. 168-172, Rennes, 2004
Checkers for SystemC Designs
Autor: Daniel Große, Rolf Drechsler
Konferenz: Second ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2004)
Pdf | Referenz: pp. 171-178, San Diego, 2004
Reduction of Sizes of Multiple-Valued Decision Diagrams by Copy Properties
Autor: Dragan Jankovic, Radomir Stankovic, Rolf Drechsler
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL'2004)
Referenz: pp. 229-234, Toronto, 2004
Algorithms for Taylor Expansion Diagrams
Autor: Görschwin Fey, Rolf Drechsler, Maciej Ciesielski
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL'2004)
Referenz: pp. 235-240, Toronto, 2004
Placement and Routing Optimization for Circuits Derived from BDDs
Autor: Thomas Eschbach, Rolf Drechsler, Bernd Becker
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'04)
Pdf | Referenz: Vancouver, 2004
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
Autor: Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey
Konferenz: IEEE Design, Automation and Test in Europe
Pdf | Referenz: Vol. I, pp. 162-167, Paris, 2004
Managing Don't Cares in Boolean Satisfiability
Autor: Sean Safarpour, Andreas Veneris, Rolf Drechsler, Joanne Hang
Konferenz: IEEE Design, Automation and Test in Europe
Pdf | Referenz: Vol. I, pp. 260-265, Paris, 2004
Improving Simulation-Based Verification by Means of Formal Methods
Autor: Görschwin Fey, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
Pdf | Referenz: pp. 640-643, Yokohama, 2004
Minimization of the Expected Path Length in BDDs Based on Local Changes
Autor: Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
Pdf | Referenz: pp. 866-871, Yokohama, 2004
Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization
Autor: Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
Pdf | Referenz: pp. 876-879, Yokohama, 2004
Hardware Project Management – What we Can Learn from the Software Development Process for Hardware Design?
Autor: Rolf Drechsler, Andreas Breiter
Konferenz: 4th Conference of Informatics and Information Technologies
Referenz: Bitola, 2003
Minimizing the Number of One-Paths in BDDs by an Evolutionary Algorithm
Autor: Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler
Konferenz: Congress on Evolutionary Computation 2003 (CEC2003)
Pdf | Referenz: Vol.3, pp. 1724-1731, Canberra, 2003
Testability of SPP Three-Level Logic Networks
Autor: Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
Konferenz: IFIP International Conference on Very Large Scale Integration (VLSI'03)
Pdf | Referenz: pp. 331-336, Darmstadt, 2003
Exploration of Sequential Depth by Evolutionary Algorithms
Autor: Nicole Drechsler, Rolf Drechsler
Konferenz: IFIP International Conference on Very Large Scale Integration (VLSI'03)
Pdf | Referenz: pp. 81-85, Darmstadt, 2003
BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
Autor: Junhao Shi, Görschwin Fey, Rolf Drechsler
Konferenz: Twelfth Asian Test Symposium (ATS03)
Referenz: pp. 290-293, Xi'an, 2003
Efficient Automatic Visualization of SystemC Designs
Autor: Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst
Konferenz: Forum on Specification & Design Languages (FDL'03)
Pdf | Referenz: pp. 646-657, Frankfurt, 2003
Finding Good Counter-Examples to Aid Design Verification
Autor: Görschwin Fey, Rolf Drechsler
Konferenz: First ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2003)
Pdf | Referenz: pp. 51-52, Mont Saint-Michel, 2003
Fast Heuristics for the Edge Coloring of Large Graphs
Autor: Mario Hilgemeier, Nicole Drechsler and Rolf Drechsler
Konferenz: Euromicro Symposium on Digital System Design (DSD'2003)
Pdf | Referenz: pp. 230-237, Antalya, 2003
MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits
Autor: Rolf Drechsler, Junhao Shi and Görschwin Fey
Konferenz: IEEE Great Lakes Symposium on VLSI (GLSV'03)
Pdf | Referenz: p. 80-83, Washington, 2003
Efficient Minimization of Multi-Valued Decision Diagrams for Incompletely Specified Functions
Autor: Denis Popel and Rolf Drechsler
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Referenz: pp. 241-246, Tokyo, 2003
Augmented Sifting for Multiple-Valued Decision Diagrams
Autor: Michael Miller and Rolf Drechsler
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Pdf | Referenz: pp. 375-382, Tokyo, 2003
Modeling Multi-Valued Circuits in SystemC
Autor: Daniel Große, Görschwin Fey and Rolf Drechsler
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Pdf | Referenz: pp. 281-286, Tokyo, 2003
Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques
Autor: Görschwin Fey, Sebastian Kinder and Rolf Drechsler
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Referenz: pp. 361-366, Tokyo, 2003
Formal Verification of LTL Formulas for SystemC Designs
Autor: Daniel Große, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'03)
Pdf | Referenz: pp. V:245-V:248, Bangkok, 2003
Reducing the Number of Variable Movements in Exact BDD Minimization
Autor: Rüdiger Ebendt
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'03)
Pdf | Referenz: pp. V:605-V:608, Bangkok, 2003
Synthesizing Checkers for On-line Verification of System-on-Chip Designs
Autor: Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'03)
Pdf | Referenz: pp. IV:748-IV:751, Bangkok, 2003
Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms
Autor: Rolf Drechsler and Nicole Drechsler
Konferenz: 21st IASTED International Multi-Conference Applied Informatics (AI 2003)
Referenz: Innsbruck, 2003
Combination of Lower Bounds in Exact BDD Minimization
Autor: Rüdiger Ebendt, Wolfgang Günther and Rolf Drechsler
Konferenz: IEEE Design, Automation and Test in Europe (DATE'03)
Pdf | Referenz: pp. 758-763, Munich, 2003
SPIHT implemented in a XC4000 device
Autor: Jörg Ritter, Görschwin Fey and Paul Molitor
Konferenz: IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002)
Pdf | Referenz: volume I, pp. 239-242, Tulsa, 2002
Utilizing BDDs for disjoint SOP minimization
Autor: Görschwin Fey and Rolf Drechsler
Konferenz: IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002)
Referenz: volume II, pp. 306-309, Tulsa, 2002
Minimizing the Number of Paths in BDDs
Autor: Görschwin Fey and Rolf Drechsler
Konferenz: 15th Symposium on Integrated Circuits and System Design
Pdf | Referenz: pp. 359-364, Porto Alegre, 2002
Crossing Reduction by Windows Optimization
Autor: Thomas Eschbach, Wolfgang Günther, Rolf Drechsler and Bernd Becker
Konferenz: 10th International Symposium on Graph Drawing (GD'2002)
Pdf | Referenz: LNCS 2528, pp. 285-294, Irvine, 2002
Reachability Analysis for Formal Verification of SystemC
Autor: Rolf Drechsler and Daniel Große
Konferenz: Euromicro Symposium on Digital System Design (DSD'2002)
Pdf | Referenz: pp. 337-340, Dortmund, 2002
Decision Diagrams Optimization Using Copy Properties
Autor: Dragan Jankovic, Radomir Stankovic and Rolf Drechsler
Konferenz: Euromicro Symposium on Digital System Design (DSD'2002)
Pdf | Referenz: p. 236-243, Dortmund, 2002
Recursive Bi-Partitioning of Netlists for Large Number of Partitions
Autor: Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard and Gerhard Angst
Konferenz: Euromicro Symposium on Digital System Design (DSD'2002)
Pdf | Referenz: pp. 38-44, Dortmund, 2002
JADE: Implementation and Visualization of a BDD Package in JAVA
Autor: Rolf Drechsler
Konferenz: IEEE Design, Automation and Test in Europe (DATE'02) - User Forum
Pdf | Referenz: pp. 259, Paris, 2002
Computing Walsh, Arithmetic and Reed-Muller Spectral Decision Diagrams Using Graph Transformations
Autor: Whitney Townsend, Mitch Thornton, Rolf Drechsler and Michael Miller
Konferenz: IEEE Great Lakes Symposium on VLSI (GLSV'02)
Pdf | Referenz: pp. 178-183, New York, 2002
Switching Activity Estimation for Finite State Machines for Low Power Synthesis (Poster)
Autor: Mikael Kerttu, Per Lindgren, Mitch Thornton and Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'02)
Pdf | Referenz: Scottsdale, 2002
Multi-Output Timed Shannon Circuits
Autor: Mitch Thorton, Rolf Drechsler and Michael Miller
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002)
Pdf | Referenz: pp. 47-52, Pittsburgh, 2002
Evaluation of Static Variable Ordering Heuristics for MDD Construction
Autor: Rolf Drechsler
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL'2002)
Pdf | Referenz: pp. 254-260, Boston, 2002
On the Construction of Multi-Valued Decision Diagrams
Autor: Michael Miller and Rolf Drechsler
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL'2002)
Pdf | Referenz: pp. 245-253, Boston, 2002
Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multi-Valued Logic Functions
Autor: Dragan Jankovic, Radomir Stankovic and Rolf Drechsler
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL'2002)
Pdf | Referenz: pp. 76-82, Boston, 2002
On the Relation Between SAT and BDDs for Equivalence Checking
Autor: Sherif Reda, Rolf Drechsler and Alex Orailoglu
Konferenz: International Symposium on Quality of Electronic Design (ISQED 2002)
Pdf | Referenz: pp. 394-399, San Jose, 2002
RTL-Datapath Verification using Integer Linear Programming
Autor: Raik Brinkmann and Rolf Drechsler
Konferenz: IEEE VLSI Design'02 & Asia and South Pacific Design Automation Conference
Pdf | Referenz: pp. 741-746, Bangalore, 2002
Fast and Efficient Equivalence Checking based on NAND-BDDs
Autor: Rolf Drechsler and Mitch Thornton
Konferenz: IFIP International Conference on Very Large Scale Integration (VLSI'01)
Pdf | Referenz: pp. 401-405, Montpellier, 2001
Formal Verification on Register Transfer Level - Utilizing High-Level Information for Hardware Verification
Autor: Peer Johannsen and Rolf Drechsler
Konferenz: IFIP International Conference on Very Large Scale Integration (VLSI'01)
Pdf | Referenz: pp. 127-132, Montpellier, 2001

699 Papers




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