RISC-V Opt-VP: An Application Analysis
Platform Using Bounded Execution Trees
Autor: Jan Zielasko, Rune Krauss, Marcel Merten, Rolf Drechsler
Workshop:
RISC-V Summit Europe
Pdf | Referenz: Munich, Germany, 2024
Cross-Level Verification of Hardware Peripherals
Autor: Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Workshop:
RISC-V Summit Europe
Pdf | Referenz: Munich, Germany, 2024
Workshop: „Aktuelle Entwicklungen und Perspektiven (an Hochschulen) im Bereich Data Science“
Autor: Lena Steinmann, Dirk Nowotka, Lea Oberländer, Helen Pfuhl, Heiner Stuckenschmidt und Rolf Drechsler
Workshop:
INFORMATIK 2023
Pdf | Referenz: Berlin, Deutschland, 2023
Establishing discipline-specific Data Stewardship at the Data Science Center of the University of Bremen – One Year Review
Autor: Sandra Zänkert, Heike Thöricht, Lena Steinmann, Rolf Drechsler
Workshop:
Data Stewardship goes Germany
Referenz: Dresden, Germany, 2023
Automated Testing of Stateful Network
Protocol Implementations in the IoT
Autor: Sören Tempel, Rolf Drechsler
Workshop:
RIOT Summit
Video | Referenz: Frankfurt, Germany, 2023
Automated Formal Verification Methodology for MAGIC Design Style Based In-Memory Computing
Autor: Chandan Kumar Jha, Khushboo Qayyum, Kemal Çağlar Coşkun, Simranjeet Singh, Muhammad Hassan, Rainer Leupers, Farhad Merchant, Rolf Drechsler
Workshop:
International Workshop on Logic & Synthesis (IWLS)
Referenz: EPFL, Lausanne, Switzerland, 2023
Expanding RISC-V Horizons: Streamlining Heterogeneous Systems Evaluation with Open Source RISC-V AMS VP Framework
Autor: Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Workshop:
RISC-V Summit Europe
Pdf | Referenz: Barcelona, Spain, 2023
Scale4Edge – Scaling RISC-V for Edge Applications
Autor: Wolfgang Ecker, Milos Krstic, Markus Ulbricht, Andreas Mauderer, Eyck Jentzsch, Andreas Koch,
Bastian Koppelmann, Wolfgang Mueller, Babak Sadiye, Niklas Bruns, Rolf Drechsler, Daniel Mueller-Gritschneder, Jan Schlamelcher, Kim Grüttner, Jörg Bormann, Wolfgang Kunz, Reinhold
Heckmann, Gerhard Angst, Ralf Wimmer, Bernd Becker, Tobias Faller, Paul Palomero Bernardo, Oliver Bringmann, Johannes Partzsch, Christian Mayr
Workshop:
RISC-V Summit Europe
Pdf | Referenz: Barcelona, Spain, 2023
Polynomial Formal Verification of KFDD Circuits
Autor: Martha Schnieber, Rolf Drechsler
Workshop:
2023 Reed-Muller Workshop (RM2023)
Referenz: Matsue, Shimane, Japan, 2023
Polynomial Formal Verification of Adder Circuits Using Answer Set Programming
Autor: Mohamed Nadeem, Jan Kleinekathöfer and Rolf Drechsler
Workshop:
2023 Reed-Muller Workshop (RM2023)
Pdf | Referenz: Matsue, Shimane, Japan, 2023
OPTI-RISK: Design of an Optical Probing Attack Hardened RISC-V Core with an Industrially Compatible CMOS Gate Library
Autor: Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, and Rolf Drechsler
Workshop:
5th RISC-V Activity Workshop
Referenz: Berlin, Germany, 2022
Automated Testing of RIOT modules using SymEx-VP
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Workshop:
RIOT Summit
Video | Referenz: Hamburg, Germany, 2022
Feature Importance and Extensibility for
Predicting Loan Defaults in Marketplace
Lending using BiLSTM
Autor: Sana Hassan Imam, Sebastian Huhn, Lars Hornuf, Rolf Drechsler
Workshop:
Frontiers of Factor Investing Conference (FoFi)
Referenz: Lancaster, UK, 2022
Verification of RISC-V Embedded Software by Integrating Concolic Testing with SystemC-based Virtual Prototypes
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Workshop:
4th Workshop on RISC-V Activities
Referenz: Virtual Conference, 2021
SAT-based Exact Physical Design for Field-coupled Nanocomputing Technologies
Autor: Marcel Walter, Winston Haaswijk, Robert Wille, Frank Sill Torres, Rolf Drechsler
Workshop:
International Workshop on Logic & Synthesis (IWLS)
Referenz: San Francisco, USA, 2020
Integrating Hybrid Analysis with Machine Learning Techniques for Portion Resilience Evaluation in Approximating SystemC-based Designs
Autor: Mehran Goli, Rolf Drechsler
Workshop:
Workshop on Machine Learning for CAD (MLCAD)
Referenz: Canmore (Banff Area), Alberta, Canada, 2019
fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits
Autor: Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Workshop:
International Workshop on Logic & Synthesis (IWLS)
Referenz: Lausanne, Switzerland, 2019
A Document-oriented, Heterogeneous Database
Model for Large Experimental Data Sets
Autor: Timo Kohorst and Sebastian Huhn and Rolf Drechsler
Workshop:
MAPEX Symposium
Pdf | Referenz: Bremen, Germany, 2018
Evaluation of Power State Cross Coverage in Firmware-Based Power Management
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop:
Embedded Software for Industrial IoTs (ESIIT)
Referenz: Dresden, Germany, 2018
On the computational complexity of error metrics in approximate computing
Autor: Oliver Keszöcze, Mathias Soeken, Rolf Drechsler
Workshop:
International Workshop on Boolean Problems
Referenz: Freiberg, Germany, 2016
Extraktion von Frame Conditions aus Operation Contracts
Autor: Philipp Niemann, Frank Hilken, Martin Gogolla, Robert Wille
Workshop:
Software Engineering (SE)
Referenz: Vienna, Austria, 2016
Quo Vadis, Reversible Circuit Design? Towards Scaling Design and Synthesis of Reversible Circuits
Autor: Eleonora Schönborn, Robert Wille, Rolf Drechsler
Workshop:
Reed-Muller Workshop
Referenz: Waterloo, Canada, 2015
Self-Inverse Functions and Palindromic Circuits
Autor: Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller
Workshop:
Reed-Muller Workshop
Referenz: Waterloo, Canada, pre-print available at
arXiv:1502.05825, 2015
Fehlereffektsimulation mittels virtueller Prototypen
Autor: Sebastian Reiter, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Rolf Drechsler, Wolfgang Ecker, Thomas Kruse, Christoph Kuznik, Jo Laufenberg, Hoang M. Le, Petra Maier, Daniel Müller-Gritschneder, Hendrik Post, Jan-Hendrik Oetjens, Wolfgang Rosenstiel, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl
Workshop:
GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Referenz: Bad Urach, 2015
SystemC Verifikation mittels symbolischer Simulation einer Zwischensprache
Autor: Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
Workshop:
edaWorkshop
Pdf | Referenz: pp. 53-58, Dresden, Germany, 2013
Towards Embedding of Large Functions for Reversible Logic
Autor: Mathias Soeken, Robert Wille, Laura Tague, D. Michael Miller, Rolf Drechsler
Workshop:
International Workshop on Boolean Problems
Referenz: Freiberg, 2012
Using πDDs in the Design for Reversible Circuits
Autor: Mathias Soeken, Robert Wille, Shin-Ichi Minato, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Referenz: Kopenhagen, 2012
Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams
Autor: Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Referenz: Kopenhagen, 2012
Compilation of Methodologies to Speed up the Verification Process
at System Level
Autor: Stephan Radke, Steffen Rülke, Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Müller, Wolfgang Ecker, Volkan Esen, Simon Hufnagel, Nico Bannow, Helmut Brazdrum, Peter Janssen, Hoang M. Le, Daniel Große, Rolf Drechsler, Erhard Fehlauer, Gernot Koch, Andreas Burger, Oliver Bringmann, Wolfgang Rosenstiel, Finn Haedicke, Ralph Görgen, Jan-Hendrik Oetjens
Workshop:
edaWorkshop
Referenz: pp. 57-62, Hannover, 2012
Functional Analysis of Circuits Under Timing
Variations
Autor: Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Workshop:
edaWorkshop
Pdf | Referenz: Hannover, Germany, 2012
Tangicons - Programmieren im Kindergarten
Autor: Thomas Winkler, Florian Scharf, Judith Peters, Michael Herczeg
Workshop:
Tagung Mensch & Computer
Referenz: pp. 23-24, Chemnitz, 2011
Synthesis of Reversible Circuits with Minimal Lines for Large Functions
Autor: Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Referenz: pp. 59-70, Gent, 2011
Customized Design Flows for Reversible Circuits Using RevKit
Autor: Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Referenz: pp. 91-96, Gent, 2011
Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines
Autor: Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler
Workshop:
SORT 2011: 2nd IEEE Workshop on Self-Organizing Real-Time Systems
Referenz: pp. 181-188, Newport Beach, 2011
Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition
Autor: Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
5th International Design & Test Workshop (IDT)
Pdf | Referenz: pp. 143-148, Abu Dhabi, 2010
RevKit: A Toolkit for Reversible Circuit Design
Autor: Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Pdf | Referenz: pp. 69-72, Bremen, 2010
Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition
Autor: Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop:
Workshop on Reversible Computation
Referenz: pp. 55-58, Bremen, 2010
Model-Based Diagnosis for Programmable Logic Controllers
Autor: Andre Sülflow, Rolf Drechsler
Workshop: Gemeinsamer Workshop der Informatik-Graduiertenkollegs und Forschungskollegs
Referenz: Dagstuhl, 2009
Robustness Check for Multiple Faults using Formal Techniques
Autor: Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
Workshop:
Constraints in Formal Verification (CFV)
Pdf | Referenz: Grenoble, France, 2009
Synthesizing Reversible Logic: An Overview
Autor: Robert Wille, Rolf Drechsler
Workshop:
Reed-Muller Workshop
Referenz: Naha, Okinawa, 2009
Synthesising Reversible Circuits from Irreversible Specifications using Reed-Muller Spectral Techniques
Autor: D. Michael Miller, Gerhard W. Dueck, Robert Wille
Workshop:
Reed-Muller Workshop
Referenz: Naha, Okinawa, 2009
Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
Autor: Robert Wille, Rolf Drechsler
Workshop:
Reversible Computation
Referenz: York, 2009
Using a Two-Dimensional Fault List for Compact Automatic Test Pattern Generation
Autor: Marc Messing, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
Workshop:
10th IEEE Latin-American TestWorkshop (LATW)
Referenz: Búzios, Rio de Janeiro, 2009
Formale Modellextraktion von SystemC Entwürfen
Autor: Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard
Workshop:
edaWorkshop
Pdf | Referenz: pp. 7-12, Hannover, 2008
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
Autor: Rolf Drechsler, Görschwin Fey, Jürgen Schlöffel
Workshop:
edaWorkshop 2007
Referenz: Hannover, 2007
Documentation Driven Software Development for
Embedded Systems
Autor: Beate Muranko, Rolf Drechsler
Workshop: 14. Workshop der Fachgruppe WI-VM der Gesellschaft für Informatik e.V. Vorgehensmodelle und Projektmanagement
- Assessment, Zertifizierung, Akkreditierung -
Pdf | Referenz: München, 2007
Visualized SystemC Debugging
Autor: Christian Genz, Frank Rogin, Rolf Drechsler, Steffen Rülke
Workshop: University Booth at Design, Automation and Test in Europe (DATE07)
Pdf | Referenz: Nizza, 2007
Efficiency of Multi-Valued Encoding in SAT-based ATPG
Autor: Görschwin Fey, Junhao Shi , Rolf Drechsler
Workshop: 18. Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“
Referenz: Titisee, 2006
Technische Dokumentation von Soft- und Hardware-Systemen:
Die vergessene Welt
Autor: Beate Muranko, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: Dresden, 2006
SAT-Based Calculation of Source Code Coverage for BMC
Autor: Görschwin Fey, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: Dresden, 2006
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Workshop: 6th International Workshop on Microprocessor Test and Verification (MTV'05)
Pdf | Referenz: pp. 133-137, Austin, 2005
Bounded Model Checking mit SystemC
Autor: Sebastian Kinder, Rolf Drechsler, Jan Peleska
Workshop: Bieleschweig 6 - Workshop "Systems Engineering"
Referenz: Braunschweig, 2005
Bounded Model Checking of Tram Control Systems
Autor: Sebastian Kinder, Daniel Große, Jan Peleska, Rolf Drechsler
Workshop: TRain Workshop @ SEFM2005
Referenz: Koblenz, 2005
Formale Verifikation des Befehlssatzes eines in SystemC modellierten Mikroprozessors
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Workshop: Entwurfsmethoden für Nanometer VLSI Design
Pdf | Referenz: pp. 308-312, Bonn, 2005
On the Exact Minimization of Path-Related Objective Functions for BDDs
Autor: Rüdiger Ebendt, Rolf Drechsler
Workshop: International Workshop on Logic and Synthesis (IWLS'05)
Pdf | Referenz: pp. 333-400, Lake Arrowhead, California, 2005
Acceleration of SAT-based Iterative Property Checking
Autor: Daniel Große, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: München, 2005
Modellierung eines Mikroprozessors in SystemC
Autor: Daniel Große, Ulrich Kühne, Christian Genz, Frank Schmiedle, Bernd Becker, Rolf Drechsler, Paul Molitor
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: München, 2005
SyCE: An Integrated Environment for System Design in SystemC
Autor: Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große
Workshop: 16th IEEE International Workshop on Rapid System Prototyping (RSP)
Pdf | Referenz: pp. 258-260, Montreal, 2005
PASSAT: Efficient SAT-based Test Pattern Generation
Autor: Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Workshop: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Referenz: Sopron, 2005
Efficient Hierarchical System Debugging for Property Checking
Autor: Görschwin Fey, Rolf Drechsler
Workshop: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Sopron, 2005
ParSyC: An Efficient SystemC Parser
Autor: Görschwin Fey, Daniel Große, Tim Cassens, Christian Genz, Tim Warode, Rolf Drechsler
Workshop: 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004)
Pdf | Referenz: pp. 148-154, Kanazawa, 2004
Design Understanding by Automatic Property Generation
Autor: Rolf Drechsler, Görschwin Fey
Workshop: 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004)
Pdf | Referenz: pp.274-281, Kanazawa, 2004
Debugging Sequential Circuits Using Boolean Satisfiability
Autor: Moayad Ali, Andreas Veneris, Sean Safarpour, Magdy Abadir, Rolf Drechsler, Alexander Smith
Workshop: 5th International Workshop on Microprocessor Test and Verification (MTV'04)
Referenz: Austin, 2004
Experimental Studies on Test Pattern Generation for BDD Circuits
Autor: Junhao Shi, Görschwin Fey, Rolf Drechsler
Workshop: International Workshop on Boolean Problems (IWSBP)
Pdf | Referenz: pp. 71-76, Freiberg, 2004
Towards Formal Verification on the System Level
Autor: Rolf Drechsler
Workshop: 15th IEEE International Workshop on Rapid System Prototyping
Pdf | Referenz: Invited Talk, pp. 2-5, Geneva, 2004
Visualization of Diagnosis Results for Design Debugging
Autor: Görschwin Fey, Rolf Drechsler
Workshop: 13th International Workshop on Post-Binary ULSI Systems
Referenz: pp. 1-2, Toronto, 2004
Disjoint Sum of Product Minimization by Evolutionary Algorithms
Autor: Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler
Workshop: 1st European Workshop on Hardware Optimisation Techniques (EvoHOT)
Pdf | Referenz: Applications of Evolutionary Computing: EvoWorkshops 2004, LNCS 3005, p. 198-207, Coimbra, 2004
Efficient (Non-)Reachability Analysis of Counterexamples
Autor: Rolf Drechsler, Wolfgang Günther, Burkhard Stubert
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: pp. 250-259, Kaiserslautern, 2004
Using Synthesis Techniques in SAT Solvers
Autor: Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: pp. 165-173, Kaiserslautern, 2004
A Tight Lower Bound for Dynamic BDD Minimization
Autor: Rüdiger Ebendt, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Referenz: pp. 233-242, Kaiserslautern, 2004
An Approach to Formal Verification of Reconfigurable Systems
Autor: Görschwin Fey, Rolf Drechsler, Muazzam Ali
Workshop: 1st IFIP WG 10.5 Workshop on "Frontiers in Automotive Electronics"
Referenz: Darmstadt, 2003
BDD-Based Verification of Scalable Designs
Autor: Daniel Große, Rolf Drechsler
Workshop: IEEE International High Level Design Validation and Test Workshop (HLDVT'2003)
Pdf | Referenz: pp. 123-128, San Francisco, 2003
Random Pattern Testability of Circuits Derived from BDDs
Autor: Junhao Shi, Göschwin Fey and Rolf Drechsler
Workshop: 4th Workshop on RTL and High Level Testing(WRTLT'03)
Pdf | Referenz: p.70-78,
Xi'an, 2003
Synthesizing Checkers for On-line Verification of System-on-Chip Designs
Autor: Rolf Drechsler
Workshop: GI/GMM/ITG Fachtagung Entwurf Integrierter Schaltungen (11. E.I.S.-Workshop)
Referenz: Erlangen, 2003, page 69, 2003
BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
Autor: Junhao Shi, Görschwin Fey and Rolf Drechsler
Workshop: IEEE European Test Workshop (ETW'03)
Pdf | Referenz: pp. 109-110, Maastricht, 2003, 2003
MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits
Autor: Rolf Drechsler
Workshop: 15th ITG/GMM/GI Workshop Test methods and Reliability of Circuits and Systems
Referenz: Timmendorfer Strand, 2003
BDD Circuit Optimization for Path Delay Fault-Testability
Autor: Görschwin Fey, Junhao Shi, Rolf Drechsler
Workshop: 15th ITG/GMM/GI Workshop Test methods and Reliability of Circuits and Systems
Referenz: Timmendorfer Strand, 2003
, 2003
A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization
Autor: Görschwin Fey, Rolf Drechsler
Workshop: 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2003)
Referenz: pp. 54-60, Hiroshima
, 2003
GAME-HDL: Implementation of Evolutionary Algorithms using Hardware Description Languages
Autor: Rolf Drechsler, Nicole Drechsler
Workshop: 5th European Workshop on Evolutionary Computation in Image Analysis and Signal Processing (EvoIASP2003)
Pdf | Referenz: LNCS 2611, pp. 378-387, Colchester, 2003
Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen
Autor: Daniel Große, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: pp. 229-238, Bremen, 2003
Cost-efficient Formal Block Verification for ASIC Design
Autor: K. Winkelmann, J. Trylus, D. Stoffel, Görschwin Fey
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: pp. 184-188, Bremen, 2003
Complete BDDs for Fast and Efficient Equivalence Checking, In Workshop on Computational Intelligence and Information Technologies
Autor: Rolf Drechsler
Workshop: XXXVII International Scientific Conference on Information Communication and Energy Systems and Technologies (ICEST 2002)
Referenz: pp. 741-744, Nis, 2002
Gatecomp: Equivalence Checking of Digital Circuits in an Industrial Environment
Autor: Rolf Drechsler, Stefan Höreth
Workshop: International Workshop on Boolean Problems
Pdf | Referenz: pp. 195-200, Freiberg, 2002
Minimizing the Number of Paths in BDDs
Autor: Görschwin Fey, Rolf Derchsler
Workshop: International Workshop on Boolean Problems
Pdf | Referenz: pp. 149 - 156, Freiberg, 2002
Low Power Optimization Technique for BDD Mapped Finite State Machines
Autor: M. Kerttu, P. Lindgren, Rolf Drechsler, M. Thornton
Workshop: International Workshop on Logic Synthesis (IWLS'2002)
Referenz: New Orleans, 2002
Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation
Autor: Rolf Drechsler, M. Kerttu, P. Lindgren, M. Thornton
Workshop: International Workshop on System-on-Chip for Real-Time Applications 2002
Referenz: Banff, 2002
Symbolic Simulation of Algorithms Specified in HDL
Autor: Klaus-Jürgen Englert, Bernd Becker, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: pp. 113 - 122, Tübingen, 2002
Implementation and Visualization of a BDD Package in JAVA
Autor: Rolf Drechsler, Jochen Römmler
Workshop: GI/ITG/GMM-Workshop 2002, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: pp. 219 - 228, Tübingen, 2002
