PLiM „HDL-based Synthesis and Verifcation for Programmable Logic-In-Memory Architecture“

The goal of the PLiM project "HDL-based synthesis and verification for programmable logic-in-memory architecture" is to find an HDL-based synthesis approach for a logic-in-memory architecture.

Contact: Prof. Dr. Rolf Drechsler, Saman Fröhlich

Resistive RAM (RRAM) is an emerging technology that, unlike conventional memories, allows Boolean operations to be performed - also known as in-memory computing. Along with the fact that RRAM has extremely low power consumption and scales well, this is one of the most promising new technologies for future computer generations. The aim of the PLiM project "HDL-based synthesis and verification for programmable logic-in-memory architecture" is to find an HDL-based synthesis approach for a RRAM-based logic-in-memory architecture. In addition, possibilities for the verification of programs for this architecture are to be developed. Through further optimization and parallelization of the programs, a powerful platform for in-memory computing is to be developed.