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Arbeitsgruppe Rechnerarchitektur / AGRA | Informatik | FB03 | Universität Bremen

Prof. Dr. Gerhard W. Dueck


In der Forschung befasse ich mich mit dem Problem der Logiksynthese. Der Schwerpunk liegt bei der Synthese und Minimierung von reversiblen Logik Funktionen. Diese sind von Wichtigkeit in der Entwicklung von Quanten Computern.

Gast

Ancilla-free synthesis of large reversible functions using binary decision diagrams
Autor: Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
Zeitschrift: Journal of Symbolic Computation
Details: DOI 10.48550/arXiv.1408.3955 (2015)

Debugging Reversible Circuits
Autor: Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Zeitschrift: INTEGRATION, the VLSI Journal
Details: DOI: 10.1016/j.vlsi.2010.08.002, Volume 44, Number 1, pp. 51-61, January (2011)

Exact Synthesis of Elementary Quantum Gate Circuits
Autor: Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Zeitschrift: Multiple-Valued Logic and Soft Computing
Details: DOI: 10.1109/ISMVL.2008.42, Volume 15, Number 4, pp. 283-300 (2009)

Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
Autor: Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2009.2017215, Volume 28, Number 5, pp. 703-715 (2009)

Integrated Synthesis of Linear Nearest Neighbor Ancilla-Free MCT Circuits
Autor: Md. Mazder Rahman, Gerhard W. Dueck, Anupam Chattopadhyay, Robert Wille
Konferenz: 46th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Sapporo, Japan, 2016

Reversible Circuit Rewriting with Simulated Annealing
Autor: Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, and Rolf Drechsler
Konferenz: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Pdf | Referenz: Daejeon, Korea, 2015

Dynamic Template Matching with Mixed-polarity Toffoli Gates
Autor: Md Mazder Rahman, Mathias Soeken, Gerhard W. Dueck
Konferenz: 45th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Waterloo, Canada, 2015

Synthesizing Multiplier in Reversible Logic
Autor: Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Konferenz: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 335-340, Vienna, 2010

Window Optimization of Reversible and Quantum Circuits
Autor: Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Konferenz: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 431-435, Vienna, 2010

Synthesizing Reversible Circuits for Irreversible Functions
Autor: D. Michael Miller, Robert Wille, Gerhard W. Dueck
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 749-756, Patras, 2009

Debugging of Toffoli Networks
Autor: Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1284-1289, Nice, 2009

Reversible Logic Synthesis with Output Permutation
Autor: Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Konferenz: 22nd International Conference on VLSI Design
Pdf | Referenz: pp. 189-194, New Delhi, 2009

RevLib: An Online Resource for Reversible Functions and Reversible Circuits
Autor: Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler
Konferenz: 38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Pdf | Referenz: pp. 220-225, Dallas
RevLib is available at www.revlib.org, 2008

Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don’t Cares
Autor: Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Konferenz: 38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Pdf | Referenz: pp. 214-219, Dallas
Received IEEE Young Researcher Award, 2008

Quantified Synthesis of Reversible Logic
Autor: Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große
Konferenz: Design, Automation, and Test in Europe (DATE)
Pdf | Referenz: pp. 1015-1020, Munich, 2008

Exact SAT-based Toffoli Network Synthesis
Autor: Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 96-101, Stresa, 2007

Self-Inverse Functions and Palindromic Circuits
Autor: Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller
Workshop: Reed-Muller Workshop
Referenz: Waterloo, Canada, pre-print available at arXiv:1502.05825, 2015

Synthesising Reversible Circuits from Irreversible Specifications using Reed-Muller Spectral Techniques
Autor: D. Michael Miller, Gerhard W. Dueck, Robert Wille
Workshop: Reed-Muller Workshop
Referenz: Naha, Okinawa, 2009

Reversible Logic Synthesis with Output Permutation
Autor: Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Workshop: International Workshop on Boolean Problems
Referenz: Freiberg, 2008

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