RISC-V
Open Source Tools and Publications
RISC-V Related Approaches

This website provides an overview on the RISC-V related open source tools and research approaches developed at the Group of Computer Architecture (AGRA) at the University of Bremen and the Cyber-Physical Systems (CPS) department of the German Research Center for Artificial Intelligence (DFKI). Our current research focus includes virtual prototyping and verification for RISC-V.

In the following we first present an overview on our open source tools where you can also find the respective GitHub links with further information, and then we present our RISC-V related approaches with corresponding publications categorized in different research directions.

For more information, please contact us at: riscv@informatik.uni-bremen.de.

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ABOUT THE CLIP: RISC-V VP demonstration with a virtual and physical model of the SiFive HiFive1 board interacting with a breadboard environment.
Overview
Currently we provide four RISC-V projects as open source at GitHub:

RISC-V VP

Website

RISC-V VP: A configurable and extensible platform to build virtual prototypes for RISC-V using C++/SystemC and TLM. Features include support for all standard RISC-V extension for the 32 and 64 bit architecture including the M/S/U privileged architecture, advanced software debugging capabilities using a GDB interface with an optional Eclipse GUI, a HiFive1 configuration and support for graphical environment models, and support for several operating systems including RIOT, Zephyr, FreeRTOS and Linux.

MicroRV32

Website

MicroRV32: A RISC-V register-transfer level platform written in SpinalHDL and tailored for education and research. It integrates several peripherals alongside a 32 bit RISC-V core interconnected with a generic bus system. Simulation and synthesis is supported through an accessible open source tool flow that is Linux compatible. MicroRV32 supports bare-metal software and also small operating systems such as FreeRTOS. A RISC-V VP configuration matching MicroRV32 is also available.

SymEx-VP

Website

SymEx-VP: Enables concolic testing for verification of RISC-V software at the assembly level. Technically SymEx-VP is build upon RISC-V VP and integrates a concolic testing engine that supports the 32 bit RISC-V instruction set architecture.

SymSysC

Website

SymSysC: An effective approach for verification of real-world SystemC TLM peripherals using modern C++ symbolic execution tools. It is a lightweight SystemC peripheral kernel that enables an efficient integration with the modern symbolic execution engine KLEE and acts as a drop-in replacement for the normal SystemC kernel on pre-processed TLM peripherals.


Eclipse-based debugging of RISC-V software executed on the RISC-V VP (using the GDB RSP interface).

Virtual environments (left side) can be integrated with the RISC-V VP simulation for early prototyping of the physical board (right side).
A multi-core Linux boot process on the RISC-V VP using the OpenSBI bootloader.
A demonstration of the MicroRV32 platform synthesized on a board with an iCE40 HX8K FPGA and running RISC-V software to interact with buttons and LEDs.
Publications
Using our open source tools as foundation we investigate several research directions around RISC-V:

VP Modeling and Simulation Techniques

Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences (DDECS 2024)

Symbolic Execution of Binary Code based on Formal ISA Semantics RISC-V Opt-VP: An Application Analysis Platform Using Bounded Execution Trees (RISC-V Summit Europe 2024)

Towards ML-based Performance Estimation of Embedded Software: A RISC-V Case Study (MBMV 2024)

Virtual-peripheral-in-the-loop: A hardware-in-the-loop strategy to bridge the VP/RTL design-gap (arXiv 2023)

Virtual Prototype and Open Source Hardware Design in Research and Education (Orconf 2023)

Expanding RISC-V Horizons: Streamlining Heterogeneous Systems Evaluation with Open Source RISC-V AMS VP Framework (RISC-V Summit Europe 2023)

Efficient ML-Based Performance Estimation Approach across Different Microarchitectures for RISC-V Processors (DSD 2023)

Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models (FDL 2023)

Virtual Prototype Driven Application Specific Hardware Optimization (FDL 2023)

Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype (2022)

Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions (DDECS 2022)

RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems (FDL 2021)

Adaptive Simulation with Virtual Prototypes in an Open-Source RISC-V Evaluation Platform (JSA 2021)

RISC-V based Virtual Prototype: An Extensible and Configurable Platform for the System-level (JSA 2020)

Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime (ICCD 2020)

Extensible and Configurable RISC-V based Virtual Prototype (FDL 2018)

VP Verification

Security Coverage Metrics for Information Flow at the System Level (ASP-DAC 2024)

Security Validation of VP-based Heterogeneous Systems: A Completeness-driven Perspective (MBMV 2023)

Early SoCs Information Flow Policies Validation using SystemC-based Virtual Prototypes at the ESL (TECS 2022)

Verifying SystemC TLM Peripherals using Modern C++ Symbolic Execution Tools (DAC 2022)

Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level (VLSI-SoC 2021)

Verifying Instruction Set Simulators using Coverage-guided Fuzzing (DATE 2019)

RISC-V Compliance Testing

Towards RISC-V CSR Compliance Testing (JSA 2021)

Mutation-based Compliance Testing for RISC-V (ASP-DAC 2021)

Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side (DAC 2020)

Towards Specification and Testing of RISC-V ISA Compliance (DATE 2020)

VP-based Security Evaluation

Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes (DAC 2020)

SW Verification

Accurate and Extensible Symbolic Execution of Binary Code based on Formal ISA Semantics (DATE 2025)

BinSym: Binary-Level Symbolic Execution using Formal Descriptions of Instruction Semantics (arXiv 2024)

Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT (JIOT 2023)

SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware (2022)

Automated Detection of Spatial Memory Safety Violations for Constrained Devices (ASP-DAC 2022)

In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes (FDL 2021)

Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing (DAC 2021)

An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes (DATE 2021)

RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms (ATVA 2020)

Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes (GLSVLSI 2020)

Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study (DAC 2019)

RTL Platform

Lower the RISC: Designing optical-probing-attack-resistant cores (MICPRO 2024)

Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core (COINS 2023)

Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study (NorCAS 2024)

The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research (2022)

MicroRV32: An Open Source RISC-V Cross-Level Platform for Education and Research (DESTION 2021)

Cross-Level Verification

Symbolic Execution of Unmodified SystemC Peripherals (MBMV 2025)

Cross-Level Verification of Hardware Peripherals (RISC-V Summit Europe 2025)

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation (Chips 2023)

Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging (DATE 2022)

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion (MBMV 2021)

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study (FDL 2020)

Acknowledgment
This work was supported in part by the German Federal Ministry of Education and Research (BMBF) within the project CONFIRM under contract no. 16ES0565 and within the project SATiSFy under contract no. 16KIS0821K and within the project VerSys under contract no. 01IW19001 and within the project Scale4Edge under contract no. 16ME0127 and within the project HEP under contract no. 16KIS1342, and by the University of Bremens graduate school SyDe, funded by the German Excellence Initiative.
Contact
For more information, please contact us at: riscv@informatik.uni-bremen.de
Prof. Dr. Rolf Drechsler
University of Bremen / DFKI GmbH
drechsler@uni-bremen.de