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Group of Computer Architecture / AGRA | Computer Science | Faculty 03 | University of Bremen

Fatemeh Shirinzadeh, M.Sc.


My field of research is HDL-based synthesis of in-memory computer architectures that process data in non-volatile memory devices. In my research, I work with Logic-in-Memory (LiM) architecture extensions to support analog and mixed-signal (A/MS) designs.

Research Staff

In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures
Author: Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta and Rolf Drechsler
Conference: International Conference on VLSI Design (VLSID)
Pdf | Reference: Kolkata, India, 2024

Verification of In-Memory Logic Design Using ReRAM Crossbars
Author: Kamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler
Conference: IEEE Interregional NEWCAS Conference (NEWCAS)
Pdf | Reference: Edinburgh, Scotland, 2023

An Evolutionary Approach to Reconfigurable Scan Network Design
Author: Payam Habiby, Fatemeh Shirinzadeh und Rolf Drechsler
Workshop: GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Darmstadt, Germany, 2024

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