I investigate the verification of embedded system in the scope of the Scale4Edge research project. Here, I especially consider the interface between hardware and software. Another one of my research interests is formal verification.
BDD Meets SAT: Binary Hybrid Diagrams for Efficient Generation of Multiple Solutions
Author: Rune Krauss, Luca Müller, Marius Marach and Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Reference: Schloß Rheinfels, St. Goar, Germany, 2025
Finding Optimal Implementations of Non-native CNOT Gates using SAT
Author: Philipp Niemann, Luca Müller, Rolf Drechsler
Conference: Reversible Computation (RC) Pdf | Reference: Nagoya, Japan, 2021
Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation
Author: Philipp Niemann, Luca Müller, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD) Pdf | Reference: Palermo, Sicily, Italy, 2021
