AGRA | Team Detail

I investigate the verification of embedded system in the scope of the Scale4Edge research project. Here, I especially consider the interface between hardware and software. Another one of my research interests is formal verification.

Research Staff

+49 421 218-59851

MZH 4194

lucam@uni-bremen.de

Journals

Advanced And-Inverter Graph Decomposition Technique for Reducing Circuit Complexity
Author: Mohamed Nadeem, Luca Müller, Chandan Kumar Jha, Rolf Drechsler
Jorunal: ACM Transactions on Design Automation of Electronic Systems
Details: Details: Accepted Jahr: 2025 (2025)

Polynomial formal verification parameterized by cutwidth properties of a circuit using Boolean satisfiability
Author: Luca Müller, Rolf Drechsler
Jorunal: Microprocessors and Microsystems (MICPRO)
Details: https://doi.org/10.1016/j.micpro.2025.105199 (2025 )

Conferences

BDD Meets SAT: Binary Hybrid Diagrams for Efficient Generation of Multiple Solutions
Author: Rune Krauss, Luca Müller, Marius Marach and Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Reference: Schloß Rheinfels, St. Goar, Germany
Best Paper Award, 2025

SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited Cutwidth
Author: Luca Müller, Rolf Drechsler
Conference: Euromicro Conference Series on Digital System Design (DSD)
Pdf | Reference: Paris, France, 2024

Finding Optimal Implementations of Non-native CNOT Gates using SAT
Author: Philipp Niemann, Luca Müller, Rolf Drechsler
Conference: Reversible Computation (RC)
Pdf | Reference: Nagoya, Japan, 2021

Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation
Author: Philipp Niemann, Luca Müller, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Palermo, Sicily, Italy, 2021

Luca Müller, M.Sc.

Journals

Conferences

Group

Research

Studies

Publications

Competences

Service