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Group of Computer Architecture / AGRA | Computer Science | Faculty 03 | University of Bremen

Mohamed Nadeem, M.Sc.

'As part of the Reinhart Koselleck Polyver project, I am working on polynomial formal verification of digital circuits. My approach involves employing dynamic programming techniques in conjunction with Answer Set Programming to have a polynomial-time upper bound for the verification process.

Research Staff

+49 421 218-63947

MZH 4250


Polynomial Formal Verification of Approximate Adders with Constant Cutwidth
Author: Mohamed Nadeem, Chandan Kumar Jha, Rolf Drechsler
Conference: IEEE European Test Symposium (ETS)
Pdf | Reference: The Hague, Netherlands, 2024

Polynomial Formal Verification of Multi-Valued Logic Circuits within Constant Cutwidth Architectures
Author: Mohamed Nadeem, Rolf Drechsler
Conference: IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Brno, Czech Republic, 2024

Polynomial Formal Verification exploiting Constant Cutwidth
Author: Mohamed Nadeem, Jan Kleinekathöfer, Rolf Drechsler
Workshop: International Workshop on Rapid System Prototyping (RSP)
Pdf | Reference: Hamburg, Germany, 2023

Polynomial Formal Verification of Adder Circuits Using Answer Set Programming
Author: Mohamed Nadeem, Jan Kleinekathöfer and Rolf Drechsler
Workshop: 2023 Reed-Muller Workshop (RM2023)
Pdf | Reference: Matsue, Shimane, Japan, 2023

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