'As part of the Reinhart Koselleck Polyver project, I am working on polynomial formal verification of digital circuits. My approach involves employing dynamic programming techniques in conjunction with Answer Set Programming to have a polynomial-time upper bound for the verification process.
Polynomial Debugging and Fault Correction of Combinational Circuits With Constant Cutwidth
Advanced And-Inverter Graph Decomposition Technique for Reducing Circuit Complexity
Polynomial Formal Verification of Multi-Valued Approximate Circuits within Constant Cutwidth
Linear Formal Verification of Multi-Valued Logic Circuits within Constant Cutwidth Architectures