Saeideh Nabipour, M.Sc.
Memristor-Based In-Memory Logic Design Styles for Neuromorphic and AI Computing
Autor: Saeideh Nabipour, Kamalika Datta, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler
Buchtitel: Handbook of Industrial Internet of Things | Herausgeber: Amlan Chakrabarti, Hadis Karimipour, Sangeet Saha
Verlag: Springer Nature
Format: (2026)
Approximated MAGIC-ReRAM Adder Circuits for Low-Latency In-Memory Computing
Autor: Saeideh Nabipour, Chandan Kumar Jha, Saeideh Shirinzadeh, Rolf Drechsler
Konferenz: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Referenz: Bratislava, Slovakia, 2026
MAC-based Mapping of Adder Architectures to RRAM Crossbars
Autor: Fatemeh Shirinzadeh, Saeideh Nabipour, Kamalika Datta, Chandan Kumar Jha, Saeideh Shirinzadeh, Rolf Drechsler
Konferenz: International Conference on Emerging Electronics (ICEE 2025)
Pdf | Referenz: Bengaluru, India, 2025
Performance Evaluation of MAGIC-ReRAM Arithmetic Circuits for Low-Latency In-Memory Computing
Autor: Saeideh Nabipour, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler
Konferenz: IEEE Nordic Circuits and Systems Conference (NorCAS)
Pdf | Referenz: Riga, Latvia, 2025
A Complete Synthesis and Verification Approach for MAGIC Based In-Memory Computing
Autor: Lennart Weingarten, Kamalika Datta, Abhoy Kole, Maya Ambalapat, Saeideh Nabipour, Indranil Sen Gupta, Rolf Drechsler
Konferenz: International Conference on Design, Test & Technology of Integrated Systems (DTTIS)
Referenz: Athens, Greece, 2025
Fast and Scalable MAGIC-Based Wallace Tree Multiplier for In-Memory Computing
Autor: Saeideh Nabipour, Kamalika Datta, Abhoy Kole, Saeideh Shirinzadeh and Rolf Drechsler
Konferenz: IEEE Cross-disciplinary Conference on Memory-Centric Computing (CCMCC)
Pdf | Referenz: Dresden, Germany , 2025
Multi-Input MAGIC Synthesis and Verification for In-Memory Computing Design
Autor: Saeideh Nabipour, Kamalika Datta, Lennart Weingarten, Abhoy Kole, Rolf Drechsler
Konferenz: IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Montreal, Quebec, Canada, 2025
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Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices