HOME | KONTAKT

Logo Universität Bremen
LOGO AGRA | AG Rechnerarchitektur



Arbeitsgruppe Rechnerarchitektur / AGRA | Informatik | FB03 | Universität Bremen

Dr. Daniel Tille


Meine bisherigen Forschungsinteressen lagen im SAT-Solving. Jetzt befasse ich mich in der AG Rechnerarchitektur hauptsächlich mit der Automatischen Testmustergenerierung -- mit dem Hauptziel, beide Techniken miteinander zu verbinden.

WiMi

Test Pattern Generation using Boolean Proof Engines
Autor: Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille
Verlag: Springer
Format: Hardcover (2009)

Incremental Solving Techniques for SAT-based ATPG
Autor: Daniel Tille, Stephan Eggersglüß, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2010.2044673, Volume 29, Number 7, pp. 1125-1130 (2010)

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
Autor: Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
Zeitschrift: it - information technology
Details: DOI: 10.1524/itit.2009.0529, Volume 51, Number 2, pp. 102-111, Pdf download (2009)

On Acceleration of SAT-based ATPG for Industrial Designs
Autor: Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2008.923107, Volume 27, Number 7, pp. 1329-1333 (2008)

A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin
Autor: Daniel Tille, Leon Klimasch, Sebastian Huhn
Konferenz: 41st IEEE VLSI Test Symposium (VTS)
Pdf | Referenz: San Diego, USA, 2023

A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems
Autor: Sebastian Huhn, Daniel Tille, Rolf Drechsler
Konferenz: International Test Conference in Asia (ITC-Asia)
Pdf | Referenz: Tokyo, Japan, 2019

Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns
Autor: Sebastian Huhn, Daniel Tille, Rolf Drechsler
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Baden Baden, Germany, 2019

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test
Autor: Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen
Konferenz: IEEE Asian Test Symposium (ATS)
Pdf | Referenz: Hiroshima, Japan, 2016

Automated Formal Verification of X Propagation with Respect to Testability Issues
Autor: Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß
Konferenz: IEEE International Design and Test Symposium 2014 (IDT)
Pdf | Referenz: pp. 106-111, Algiers, Algerien, 2014

Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs
Autor: Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler
Konferenz: 15th IEEE European Test Symposium (ETS)
Pdf | Referenz: pp. 176-181, Prag, 2010

Efficient Test Generation with Maximal Crosstalk-Induced Noise using Unconstrained Aggressor Excitation
Autor: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS)
Pdf | Referenz: pp. 649-652, Paris, 2010

Structural Heuristics for SAT-based ATPG
Autor: Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler
Konferenz: 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009)
Pdf | Referenz: pp. 77-82, Florianópolis, 2009

Speeding up SAT-based ATPG using Dynamic Clause Activation
Autor: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Konferenz: 18th Asian Test Symposium (ATS'09)
Pdf | Referenz: pp. 177-182, Taichung, 2009

A Fast Untestability Proof for SAT-based ATPG
Autor: Daniel Tille, Rolf Drechsler
Konferenz: 12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Pdf | Referenz: pp. 38-43, Liberec, 2009

Experimental Studies on SAT-based ATPG for Gate Delay Faults
Autor: Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Konferenz: 37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Pdf | Referenz: Oslo, 2007

A Two-Stage SAT-based ATPG Approach with Reduced Switching Activity
Autor: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Workshop: Second International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR) 2009
Pdf | Referenz: Sevilla, Spain, 2009

A Fast Untestability Proof for SAT-based ATPG
Autor: Daniel Tille, Rolf Drechsler
Workshop: 21. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2009
Pdf | Referenz: Bremen, 2009

Robust Tests for Transition Faults with Long Propagation Paths Using Boolean Satisfiability
Autor: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Workshop: IEEE European Test Symposium (ETS), Informal Digest of Papers
Pdf | Referenz: Lago Maggiore, 2008

Incremental SAT Instance Generation for SAT-based ATPG
Autor: Daniel Tille, Rolf Drechsler
Workshop: 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Pdf | Referenz: pp. 68-73, Bratislava, 2008

Improved Circuit-to-CNF Transformation for SAT-based ATPG
Autor: Daniel Tille, René Krenz-Bååth, Jürgen Schlöffel, Rolf Drechsler
Workshop: 20. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
Pdf | Referenz: Wien, 2008

Parallelisierung von SAT-basierter Testmustergenerierung
Autor: Daniel Tille, Robert Wille, Rolf Drechsler
Workshop: 21. Workshop der GI/ITG-Fachgruppe Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS 2007)
Referenz: pp. 213-217, Hamburg, 2007

Studies on Integrating SAT-based ATPG in an Industrial Environment
Autor: Daniel Tille, Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Workshop: 19. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
Pdf | Referenz: Erlangen, 2007

Instance Generation for SAT-based ATPG
Autor: Daniel Tille, Görschwin Fey, Rolf Drechsler
Workshop: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Pdf | Referenz: Krakau, 2007

« zurück


©2023 | AG Rechnerarchitektur | Kontakt | Impressum & Datenschutz