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Group of Computer Architecture / AGRA | Computer Science | Faculty 03 | University of Bremen

Lennart Weingarten, M.Sc.

As part of the DFG project "Reinhart Koselleck PolyVer" I work on Polynomial Formal Verification (PFV) of complex circuits with a focus on RISC-V processors. The central question is whether certain architectures have polynomial time and space upper bounds and if available to determine these exactly.

Research Staff

+49 421 218-59842

MZH 4250


Complete and Efficient Verification for a RISC-V Processor using Formal Verification
Author: Lennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Valencia, Spain, 2024

PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor
Author: Lennart Weingarten, Kamalika Datta, Rolf Drechsler
Conference: ACM International Symposium on Nanoscale Architectures (NANOARCH)
Reference: Dresden, Germany, 2023

Polynomial Formal Verification of a Processor: A RISC-V Case Study
Author: Lennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler
Conference: International Symposium on Quality Electronic Design (ISQED'23)
Pdf | Reference: San Francisco, USA, 2023

Polynomial Formal Verification of Arithmetic Circuits
Author: Rolf Drechsler, Alireza Mahzoon, Lennart Weingarten
Conference: International Conference on Computational Intelligence and Data Engineering (ICCIDE)
Pdf | Reference: Vijayawada, India, 2021

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