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Arbeitsgruppe Rechnerarchitektur / AGRA | Informatik | FB03 | Universität Bremen

Dr. Sören Tempel


Im Rahmen des Forschungsprojektes Scale4Edge beschäftige ich mich mit der Verifikation von eingebetteten Systemen auf Basis der offenen RISC-V Befehlssatzarchitektur. Der Fokus meiner Tätigkeit liegt dabei derzeit im Besonderen auf der Eigenschaftsprüfung und Fehlersuche mithilfe von symbolischen Ausführungstechniken.

WiMi

Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Zeitschrift: IEEE Internet of Things Journal
Details: DOI: 10.1109/JIOT.2023.3236694, Volume: 10 Issue: 11 (2023)

Towards Quantification and Visualization of the Effects of Concretization during Concolic Testing
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Zeitschrift: IEEE Embedded Systems Letters (ESL)
Details: DOI: 10.1109/LES.2022.3171603, Volume: 14 Issue: 4 (2022)

SymEx-VP: An Open Source Virtual Prototype for OS-Agnostic Concolic Testing of IoT Firmware
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Zeitschrift: Journal of Systems Architecture - Embedded Software Design (JSA)
Details: DOI: 10.1016/ j.sysarc.2022.102456, Volume 126 (2022)

Adaptive Simulation with Virtual Prototypes in an Open-Source RISC-V Evaluation Platform
Autor: Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
Zeitschrift: Journal of Systems Architecture - Embedded Software Design (JSA)
Details: DOI: 10.1016/j.sysarc.2021.102135, Volume 116 (2021)

Accurate and Extensible Symbolic Execution of Binary Code based on Formal ISA Semantics
Autor: Sören Tempel, Tobias Brandt, Christoph Lüth, Christian Dietrich and Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Lyon, France, 2025

Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models
Autor: Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Turin, Italy, 2023

Versatile and Flexible Modelling of the RISC-V Instruction Set Architecture
Autor: Sören Tempel, Tobias Brandt, Christoph Lüth
Konferenz: 24th International Symposium on Trends in Functional Programming (TFP)
Pdf | Referenz: UMass Boston, Boston, MA, USA, 2023

3D Visualization of Symbolic Execution Traces
Autor: Jan Zielasko, Sören Tempel, Vladimir Herdt, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Linz, Austria, 2022

SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification
Autor: Sören Tempel, Vladimir Herdt and Rolf Drechsler
Konferenz: Automated Technology for Verification and Analysis (ATVA)
Pdf | Referenz: Beijing, China, 2022

Automated Detection of Spatial Memory Safety Violations for Constrained Devices
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Taipei, Taiwan, 2022

In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Antibes, France, 2021

Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2021

An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Grenoble, France, 2021

Mutation-based Compliance Testing for RISC-V
Autor: Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Tokyo, Japan, 2021

Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime
Autor: Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
Konferenz: 38th IEEE International Conference on Computer Design (ICCD)
Pdf | Referenz: Hartford, USA, 2020

Symbolic Execution of Binary Code based on Formal ISA Semantics
Autor: Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler
Workshop: International KLEE Workshop on Symbolic Execution
Referenz: Lisbon, Portugal, 2024

Automated Testing of Stateful Network Protocol Implementations in the IoT
Autor: Sören Tempel, Rolf Drechsler
Workshop: RIOT Summit
Video | Referenz: Frankfurt, Germany, 2023

Towards Comprehensive Verification of Hardware and Software for RISC-V based Embedded Systems
Autor: Niklas Bruns, Sallar Ahmadi-Pour, Sören Tempel, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Referenz: Freiburg, Germany, 2023

Symbolic Execution for RISC-V Embedded Software Using SystemC Peripheral Models
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Workshop: 3rd International KLEE Workshop on Symbolic Execution
Video | Referenz: London, 2022

Automated Testing of RIOT modules using SymEx-VP
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Workshop: RIOT Summit
Video | Referenz: Hamburg, Germany, 2022

Verification of RISC-V Embedded Software by Integrating Concolic Testing with SystemC-based Virtual Prototypes
Autor: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Workshop: 4th Workshop on RISC-V Activities
Referenz: Virtual Conference, 2021

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