Marcel Merten, M.Sc.
SAT-Based Key Determination Attack for Improving the Quality Assessment of Logic Locking Mechanisms
Author: Marcel Merten, Mohammed E. Djeridane, Sebastian Huhn, Rolf Drechsler
Booktitle: Advanced Boolean Techniques | Editor: Rolf Drechsler, Sebastian Huhn (Eds.)
Publisher: Springer
Format: DOI 10.1007/978-3-031-28916-3 (2023)
Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences
Author: Jan Zielasko, Rune Krauss, Marcel Merten, Rolf Drechsler
Conference: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Kielce, Poland, 2024
Scalable Neuroevolution of Ensemble Learners
Author: Marcel Merten, Rune Krauss, Rolf Drechsler
Conference: The Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Reference: Lisbon, Portugal, 2023
Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques
Author: Marcel Merten, Muhammad Hassan, Rolf Drechsler
Conference: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Tallinn, Estonia, 2023
Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods
Author: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference: IEEE European Test Symposium (ETS)
Pdf | Reference: Venice, Italy, 2023
Design Enablement Flow for Circuits with Inherent
Obfuscation based on Reconfigurable Transistors
Author: Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed E. Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, Violetta Sessi, Maximilian Drescher, Sabine Kolodinski and Maciej Wiatr
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2023
Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods
Author: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference: IEEE European Test Symposium (ETS)
Pdf | Reference: Barcelona, Spain, 2022
A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection
Author: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference: 40th IEEE VLSI Test Symposium (VTS)
Pdf | Reference: San Diego, USA, 2022
A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks
Author: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference: 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Reference: Athens, Greece, 2021
ALF – A Fitness-Based Artificial Life Form for Evolving Large-Scale Neural Networks
Author: Rune Krauss, Marcel Merten, Mirco Bockholt, Rolf Drechsler
Conference: The Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Reference: Lille, France, 2021
Efficient Machine Learning through Evolving Combined
Deep Neural Networks
Author: Rune Krauss, Marcel Merten, Mirco Bockholt, Saman Fröhlich, Rolf Drechsler
Conference: Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Reference: Electronic-only, 2020
Enhancing Resilience against Sequential Attacks on Logic Locking using Evolutionary Strategies
Author: Marcel Merten, Mohammed E. Djeridane, Muhammad Hassan, Niladri Bhattacharjee, Jens Trommer, Thomas Mikolajick, Rolf Drechsler
Workshop: GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Darmstadt, Germany, 2024
SAT-based Key Determination Attack for Improving the Quality Assessment of Logic Locking Mechanisms
Author: Marcel Merten, Mohammed E. Djeridane, Sebastian Huhn, Rolf Drechsler
Workshop: 15th International Workshop on Boolean Problems (IWSBP)
Pdf | Reference: Bremen, Germany, 2022
Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods
Author: Marcel Merten, Sebastian Huhn and Rolf Drechsler
Workshop: 34. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Bremerhaven, Germany, 2022
A Codeword-based Compaction Technique for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks
Author: Sebastian Huhn, Marcel Merten, Stephan Eggersglüß and Rolf Drechsler
Workshop: 30. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Freiburg (Breisgau), Germany, 2018
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