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Group of Computer Architecture / AGRA | Computer Science | Faculty 03 | University of Bremen

Dr. Niklas Bruns


My research area is the verification of systems. My current research focus is coverage-guided verification as well as cross-level verification of embedded systems based on RISC-V.

Research Staff

Towards RISC-V CSR Compliance Testing
Author: Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
Jorunal: IEEE Embedded Systems Letters (ESL)
Details: DOI: 10.1109/LES.2021.3077368, Volume: 13 Issue: 4, pp. 202-205 (2021)

Processor Verification using Symbolic Execution: A RISC-V Case-Study
Author: Niklas Bruns, Vladimir Herdt, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2023

Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification
Author: Niklas Bruns, Vladimir Herdt, Rolf Drechsler
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: Linz, Austria, 2022

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
Author: Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: Irvine, CA, USA, 2022

Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
Author: Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2022

Early Verification of ISA Extension Specifications Using Deep Reinforcement Learning
Author: Niklas Bruns, Daniel Große, Rolf Drechsler
Conference: 30th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: Beijing, China, 2020

Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing
Author: Hoang M. Le, Daniel Große, Niklas Bruns, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Florence, Italy, 2019

Scale4Edge – Scaling RISC-V for Edge Applications
Author: Wolfgang Ecker, Milos Krstic, Markus Ulbricht, Andreas Mauderer, Eyck Jentzsch, Andreas Koch, Bastian Koppelmann, Wolfgang Mueller, Babak Sadiye, Niklas Bruns, Rolf Drechsler, Daniel Mueller-Gritschneder, Jan Schlamelcher, Kim Grüttner, Jörg Bormann, Wolfgang Kunz, Reinhold Heckmann, Gerhard Angst, Ralf Wimmer, Bernd Becker, Tobias Faller, Paul Palomero Bernardo, Oliver Bringmann, Johannes Partzsch, Christian Mayr
Workshop: RISC-V Summit Europe
Pdf | Reference: Barcelona, Spain, 2023

Towards Comprehensive Verification of Hardware and Software for RISC-V based Embedded Systems
Author: Niklas Bruns, Sallar Ahmadi-Pour, Sören Tempel, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Freiburg, Germany, 2023

RISC-V Processor Verification with Coverage-guided Aging
Author: Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Virtual, 2022

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