HOME | CONTACT

Logo Universtity of Bremen
LOGO AGRA | AG Rechnerarchitektur



Group of Computer Architecture / AGRA | Computer Science | Faculty 03 | University of Bremen

Martha Schnieber, M.Sc.


I am working on the formal verification of gate-level circuits, specifically of approximate circuits. Here, I prove that the formal verification of specific approximate circuits is feasible in polynomial time and space, by giving polynomial upper bounds for the verification complexity.

Research Staff

+49 421 218-63948

MZH 4300

martha1@uni-bremen.de

Polynomial Formal Verification of Approximate Functions
Author: Martha Schnieber
Pubisher: Springer
Format: DOI: 10.1007/978-3-658-41888-5 (2023)

Automated polynomial formal verification using generalized binary decision diagram patterns
Author: Martha Schnieber, Rolf Drechsler
Jorunal: Philosophical Transactions of the Royal Society A
Details: DOI: 10.1098/rsta.2023.0390 (2025)

Synthesis for Testability: Polynomial Test Pattern Generation for KFDD Circuits
Author: Martha Schnieber, Rolf Drechsler
Conference: Euromicro Conference Series on Digital System Design (DSD)
Pdf | Reference: Salerno, Italy, 2025

The Future is Hybrid: Next Generation Data Structures for Formal Verification
Author: Rolf Drechsler, Christina Plump, Martha Schnieber
Conference: IEEE Asian Test Symposium (ATS)
Pdf | Reference: Ahmedabad, India, 2024

Automated Polynomial Formal Verification: Human-Readable Proof Generation
Author: Rolf Drechsler, Martha Schnieber
Conference: IEEE International Symposium on Smart Electronic Systems (iSES)
Pdf | Reference: Ahmedabad, India, 2023

Polynomial Formal Verification of KFDD Circuits
Author: Martha Schnieber, Rolf Drechsler
Conference: International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Reference: Hamburg, Germany, 2023

Next-Generation Automatic Human-Readable Proofs Enabling Polynomial Formal Verification
Author: Rolf Drechsler, Martha Schnieber
Conference: International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Reference: Hamburg, Germany, 2023

Polynomial Formal Verification of Approximate Adders
Author: Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Gran Canaria, Spain, 2022

Polynomial Formal Verification of Approximate Functions
Author: Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Pafos, Cyprus, 2022

Depth Optimized Synthesis of Symmetric Boolean Functions
Author: Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Tampa, Florida, USA, 2021

Polynomial Formal Verification of KFDD Circuits
Author: Martha Schnieber, Rolf Drechsler
Workshop: 2023 Reed-Muller Workshop (RM2023)
Reference: Matsue, Shimane, Japan, 2023

Polynomial Formal Verification of Approximate Adders
Author: Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: Virtual Conference , 2022

« back


©2023 | Group of Computer Architecture | Contact | Legal & Data Privacy