Behaviour Driven Development for Hardware Design
Autor: Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler
Zeitschrift: IPSJ Transactions on System LSI Design Methodology
Details: DOI: 10.2197/ipsjtsldm.11.29, Vol. 11, pp. 29-45, PDF Download (2018)

Finite controlled invariants for sampled switched systems
Autor: Laurent Fribourg, Ulrich Kühne, Romain Soulat
Zeitschrift: Formal Methods in System Design
Details: DOI: 10.1007/s10703-014-0211-2 (2014)

Parametric Verification and Test Coverage for Hybrid Automata using the Inverse Method
Autor: Laurent Fribourg, Ulrich Kühne
Zeitschrift: International Journal of Foundations of Computer Science (IJFCS)
Details: DOI 10.1007/978-3-642-24288-5_17, Volume 24, Number 02, pp. 233-250 (2013)

Towards Fully Automatic Synthesis of Embedded Software
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Zeitschrift: IEEE Embedded Systems Letters
Details: DOI: 10.1109/LES.2010.2049983, Volume 2, Number 3, pp. 53-57 (2010)

Analyzing Functional Coverage in Bounded Model Checking
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2008.925790, Volume 27, Number 7, pp. 1305-1314 (2008)

Game-based Synthesis of Distributed Controllers for Sampled Switched Systems
Autor: Laurent Fribourg, Ulrich Kühne, Nicolas Markey
Workshop: International Workshop on Synthesis of Complex Parameters
Pdf | Referenz: London, 2015

Parametric Verification and Test Coverage for Hybrid Automata Using the Inverse Method
Autor: Laurent Fribourg, Ulrich Kühne
Workshop: 5th Workshop on Reachability Problems (RP)
Pdf | Referenz: Genua, 2011

Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines
Autor: Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler
Workshop: SORT 2011: 2nd IEEE Workshop on Self-Organizing Real-Time Systems
Referenz: pp. 181-188, Newport Beach, 2011

Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction
Autor: Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Workshop: 14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz: pp. 269-278, Oldenburg, 2011

Towards Automatic Property Generation for the Formal Verification of Bus Bridges
Autor: Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Workshop: 14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz: Oldenburg, 2011

Increasing the Accuracy of SAT-based Debugging
Autor: Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Workshop: 12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Pdf | Referenz: pp. 47-56, Berlin, 2009

Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Workshop: 9th International Workshop on Microprocessor Test and Verification (MTV)
Pdf | Referenz: pp. 88-93, Austin, Texas, 2008

Computing Bounds for Fault Tolerance using Formal Techniques
Autor: Andre Sülflow, Görschwin Fey, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Workshop: IEEE Workshop on Design for Reliability and Variability (DRV)
Pdf | Referenz: Santa Clara, USA, 2008

Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking
Autor: Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Workshop: 11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz: pp. 169-178, Freiburg, 2008

Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
Autor: Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler
Workshop: IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07)
Pdf | Referenz: pp. 31-36, Beijing, P.R.China, 2007

Complete Formal Verification of Multi Core Embedded Systems using Bounded Model Checking
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Workshop: Fifth IEEE Dallas Circuits and Systems Workshop
Referenz: pp. 147-150, Dallas, 2006

Finding Compact BDDs Using Genetic Programming
Autor: Ulrich Kühne, Nicole Drechsler
Workshop: 3rd European Workshop on Evolutionary Computation in Hardware Optimisation (EvoHOT)
Pdf | Referenz: LNCS 3907, pp. 308-319, Budapest, 2006

HW/SW Co-Verification of a RISC CPU using Bounded Model Checking
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Workshop: 6th International Workshop on Microprocessor Test and Verification (MTV'05)
Pdf | Referenz: pp. 133-137, Austin, 2005

Formale Verifikation des Befehlssatzes eines in SystemC modellierten Mikroprozessors
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Workshop: Entwurfsmethoden für Nanometer VLSI Design
Pdf | Referenz: pp. 308-312, Bonn, 2005

Modellierung eines Mikroprozessors in SystemC
Autor: Daniel Große, Ulrich Kühne, Christian Genz, Frank Schmiedle, Bernd Becker, Rolf Drechsler, Paul Molitor
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: München, 2005