Dr. Ulrich Kühne
Behaviour Driven Development for Hardware Design
Autor: Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler
Zeitschrift: IPSJ Transactions on System LSI Design Methodology
Details: DOI: 10.2197/ipsjtsldm.11.29, Vol. 11, pp. 29-45,
PDF Download
(2018)
Finite controlled invariants for sampled switched systems
Autor: Laurent Fribourg, Ulrich Kühne, Romain Soulat
Zeitschrift: Formal Methods in System Design
Details: DOI: 10.1007/s10703-014-0211-2 (2014)
Parametric Verification and Test Coverage for Hybrid Automata using the Inverse Method
Autor: Laurent Fribourg, Ulrich Kühne
Zeitschrift: International Journal of Foundations of Computer Science (IJFCS)
Details: DOI 10.1007/978-3-642-24288-5_17, Volume 24, Number 02, pp. 233-250 (2013)
Towards Fully Automatic Synthesis of Embedded Software
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Zeitschrift: IEEE Embedded Systems Letters
Details: DOI: 10.1109/LES.2010.2049983, Volume 2, Number 3, pp. 53-57 (2010)
Analyzing Functional Coverage in Bounded Model Checking
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2008.925790, Volume 27, Number 7, pp. 1305-1314 (2008)
Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction
Autor: Amr Sayed Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1048-1053, Dresden, Germany, 2016
Best Paper Candidate
Ensuring Safety and Reliability of IP-based System
Design – A Container Approach
Autor: Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, Rolf Drechsler
Konferenz: IEEE International Symposium on Rapid System Protoyping (RSP), 2015
Pdf | Referenz:
Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits
Autor: Amr Sayed Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015).
Pdf | Referenz: pp. 1-6, Montpellier, France, 2015.
A Generic Representation of CCSL Time Constraints for UML/MARTE Models
Autor: Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, 2015
Safe IP Integration Using Container Modules
Autor: Rolf Drechsler, Ulrich Kühne
Konferenz: International Symposium on Electronic System Design (ISED)
Pdf | Referenz: Mangalore, India, 2014
Automatic Refinement Checking for Formal System Models
Autor: Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Munich, Germany, 2014
Verifying Consistency between Activity Diagrams and Their Corresponding OCL Contracts
Autor: Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Munich, Germany, 2014
Behaviour Driven Development for Tests and Verification
Autor: Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Konferenz: 8th International Conference on Tests & Proofs (TAP)
Pdf | Referenz: pp. 61-77, York, 2014
Verification of the Decimal Floating-Point Square Root Operation,
Autor: Amr Sayed Ahmed, Hossam Fahmy, Ulrich Kühne
Konferenz: 19th IEEE European Test Symposium,
Pdf | Referenz: Paderborn, Germany, 2014.
SyDe - a New Graduate School for
System Design in an Excellent Setting
Autor: Ulrich Kühne, Rolf Drechsler
Konferenz: Informatics Europe (ECSS)
Referenz: Barcelona, 2012
Completeness-Driven Development
Autor: Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille
Konferenz: International Conference on Graph Transformation
Pdf | Referenz: pp. 38-50, Bremen, 2012
Parametric Analysis of Hybrid Systems Using HyMITATOR (Tool Presentation)
Autor: Étienne André, Ulrich Kühne
Konferenz: International Conference on Integrated Formal Methods (iFM)
Referenz: Pisa, Italy, 2012
IMITATOR 2.5: A Tool for Analyzing Robustness in Scheduling Problems (Tool Paper)
Autor: Étienne André, Laurent Fribourg, Ulrich Kühne, Romain Soulat
Konferenz: International Symposium on Formal Methods (FM)
Referenz: Paris, France, 2012
Automatic Property Generation for the Formal Verification of Bus Bridges
Autor: Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Konferenz: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 417-422, Cottbus, 2011
Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction
Autor: Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 223-228, Lausanne, 2011
Automated Formal Verification of Processors Based on Architectural Models
Autor: Ulrich Kühne, Sven Beyer, Jörg Bormann, John Barstow
Konferenz: Formal Methods in Computer Aided Design (FMCAD)
Referenz: Lugano, Switzerland, 2010
Generating an Efficient Instruction Set Simulator from a Complete Property Suite
Autor: Ulrich Kühne, Sven Beyer, Christian Pichler
Konferenz: IEEE/IFIP International Symposium on Rapid System Prototyping (RSP)
Pdf | Referenz: pp. 109-115, Paris, 2009
WoLFram - A Word Level Framework for Formal Verification
Autor: Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
Konferenz: IEEE/IFIP International Symposium on Rapid System Prototyping (RSP)
Pdf | Referenz: pp. 11-17, Paris, 2009
Contradictory Antecedent Debugging in Bounded Model Checking
Autor: Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 173-176, Boston, 2009
Property Analysis and Design Understanding
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1246-1249, Nice, 2009
Increasing the Accuracy of SAT-based Debugging
Autor: Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1326-1332, Nice, 2009
Formaler Nachweis der Fehlertoleranz von Schaltkreisen
Autor: Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Konferenz: GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008)
Pdf | Referenz: pp. 75-82, Ingolstadt, 2008
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Pdf | Referenz: pp. 165-170, Porto Alegre, 2007
Estimating Functional Coverage in Bounded Model Checking
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1176-1181, Nice, 2007
HW/SW Co-Verification of Embedded Systems using Bounded Model Checking
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 43-48, Philadelphia, 2006
Game-based Synthesis of Distributed Controllers for Sampled Switched Systems
Autor: Laurent Fribourg, Ulrich Kühne, Nicolas Markey
Workshop: International Workshop on Synthesis of Complex Parameters
Pdf | Referenz: London, 2015
Parametric Verification and Test Coverage for Hybrid Automata Using the Inverse Method
Autor: Laurent Fribourg, Ulrich Kühne
Workshop: 5th Workshop on Reachability Problems (RP)
Pdf | Referenz: Genua, 2011
Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines
Autor: Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler
Workshop: SORT 2011: 2nd IEEE Workshop on Self-Organizing Real-Time Systems
Referenz: pp. 181-188, Newport Beach, 2011
Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction
Autor: Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Workshop: 14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz: pp. 269-278, Oldenburg, 2011
Towards Automatic Property Generation for the Formal Verification of Bus Bridges
Autor: Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Workshop: 14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz: Oldenburg, 2011
Increasing the Accuracy of SAT-based Debugging
Autor: Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Workshop: 12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Pdf | Referenz: pp. 47-56, Berlin, 2009
Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Workshop: 9th International Workshop on Microprocessor Test and Verification (MTV)
Pdf | Referenz: pp. 88-93, Austin, Texas, 2008
Computing Bounds for Fault Tolerance using Formal Techniques
Autor: Andre Sülflow, Görschwin Fey, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Workshop: IEEE Workshop on Design for Reliability and Variability (DRV)
Pdf | Referenz: Santa Clara, USA, 2008
Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking
Autor: Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Workshop: 11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen
zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz: pp. 169-178, Freiburg, 2008
Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
Autor: Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler
Workshop: IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07)
Pdf | Referenz: pp. 31-36, Beijing, P.R.China, 2007
Complete Formal Verification of Multi Core Embedded Systems using Bounded Model Checking
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Workshop: Fifth IEEE Dallas Circuits and Systems Workshop
Referenz: pp. 147-150, Dallas, 2006
Finding Compact BDDs Using Genetic Programming
Autor: Ulrich Kühne, Nicole Drechsler
Workshop: 3rd European Workshop on Evolutionary Computation in Hardware Optimisation (EvoHOT)
Pdf | Referenz: LNCS 3907, pp. 308-319, Budapest, 2006
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Workshop: 6th International Workshop on Microprocessor Test and Verification (MTV'05)
Pdf | Referenz: pp. 133-137, Austin, 2005
Formale Verifikation des Befehlssatzes eines in SystemC modellierten Mikroprozessors
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Workshop: Entwurfsmethoden für Nanometer VLSI Design
Pdf | Referenz: pp. 308-312, Bonn, 2005
Modellierung eines Mikroprozessors in SystemC
Autor: Daniel Große, Ulrich Kühne, Christian Genz, Frank Schmiedle, Bernd Becker, Rolf Drechsler, Paul Molitor
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: München, 2005
« zurück
Formal Modeling and Verification of Cyber-Physical Systems
Advanced Automation in Formal Verification of Processors