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Finished Projects

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MANIAC: BDD Manipulation für Approximate Computing

Highly flexible material synthesis and microstructure adjustment through combined laser deposition welding and short-term heat treatment for high-throughput materials development

Identifying Additive Manufacturing Process Windows by Artificial Intelligence

FormalEST

NANOTEST

Collaborative Research Center 1320: EASE – Everyday Activity Science and Engineering

Collaborative Research Center 1232: High throughput exploration for evolutionary structural materials

CONFIRM: Automatic firmware design for application-specific electronic systems

Automated Test Generation for Multi-core Virtual Prototypes

Faster Formal Verification with Reverse Engineering

EffektiV: Efficient Fault Simulation using Virtual Prototypes for Qualification of Intelligent Motion-Control-Systems in Industrial Automation

Development of a Modular Framework for Automatic Validation and Verification of UML/OCL Models

Synthesis of Reversible Circuits using Probabilistic Methods

Utilizing Reversible Logic for Low Power Design

Fostering Competencies in Mathematical Modeling

High Quality Test Generation for Small Delay Defects

SolVerTec – Solution Verification Technologies

VisES: Visualization Technology for Complex System Descriptions aiming for the Improvement of the Safety and Robustness of Electronic Systems

RESCAR 2.0 - robust design of new electronic components for applications in the field of electromobility

Development of a Continuous Verification Flow for ESL

Synthesis and Optimization of Quantum Logic

Debugging Embedded Systems

DIAMOND - Diagnosis, Error Modelling and Correction for Reliable Systems Design

SANITAS

Quality-driven Synthesis of Large Functions in Reversible Logic

Quality-driven design of systems with reconfigurable components

Visualization of circuits and systems

Analysis Methods for the Design of Application-Robust Nanoelectronic Systems (URANOS)

Hierarchical and Sequential Information for Boolean Satisfiability in Computer Aided Design of Integrated Circuits

Reachbility Analysis based on Word Level Provers

Design Methodology for Embedded Systems

DeAR: Debugging of circuits using abstraction refinement

Efficient SAT Algorithms for the Generation of Test Patterns

Neue Methoden für den Massiv-Parallel-Test im Hochvolumen, Yield Learning und beste Testqualität (MAYA)

HERKULES: Hardware Design Techniques for Zero-Fault-Designs

Manipulation of Boolean Functions based on Hybrid Data Structures

Verisoft XT

Synthesis of reliable quantum circuits

Formal Robustness Checking

Formal Verification of Circuits using Inforamtion from High-Level Languages

Circuit- and System Verification using Word-Level Information

Debugging in the formal module verification

Implementing Modules and ECTS for Computer Studies

Efficient Methods for Debugging of Circuits and Systems

Test Synthesis of Circuits with small Delay

Pilot Implementation of ECTS

Verisoft

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