HOME | CONTACT

Logo Universtity of Bremen
LOGO AGRA | AG Rechnerarchitektur



Group of Computer Architecture / AGRA | Computer Science | Faculty 03 | University of Bremen

Dr. Jannis Stoppe


The main focus of my research activities is the analysis of description languages for hardware/software design. Major questions are how such hybrid systems can be visualized and what technical prerequisites need to be satisfied for this purpose.

Research Staff

MZH 4260

jstoppe@informatik.uni-bremen.de

Noerdman Comicbuch
Author: Rolf Drechsler, Jannis Stoppe
Pubisher: JR Blendermann Verlag
Format: ISBN: 978-3-910580-07-7, Taschenbuch (2023)

Noch analog oder lebst Du schon?
Mit Nœrdman durch die Welt von heute... und morgen
Author: Rolf Drechsler, Jannis Stoppe
Pubisher: Springer
Format: DOI: 10.1007/978-3-658-32413-1, Softcover, eBook (2021)

Computer: Wie funktionieren Smartphone, Tablet & Co.?
Author: Rolf Drechsler, Andrea Fink, Jannis Stoppe
Pubisher: Springer
Format: Taschenbuch (2017)

Automated Non-intrusive Analysis of Electronic System Level Designs
Author: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Jorunal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2018.2889665, Volume: 39, number: 2, pages: 492-505 (2020)

KI-Unterstützung im Systementwurf – Wenn Computer lernen, wie Computer arbeiten
Author: Jannis Stoppe, Rolf Drechsler
Jorunal: Industrie 4.0 Management
Details: 1/2015, Nr. 5104 (2015)

Analyzing SystemC Designs: SystemC Analysis Approaches for Varying Applications
Author: Jannis Stoppe, Rolf Drechsler
Jorunal: Sensors
Details: DOI: 10.3390/s150510399, Volume (issue) 15(5), pages 10399-10421 (2015)

Towards an Automated Debugging Approach for Fault Identification in Quantum Circuits
Author: Anton Maidl, Abhoy Kole, Kamalika Datta, Jannis Stoppe, Rolf Drechsler
Conference: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Lyon, France, 2025

Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques
Author: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference: IEEE International Symposium on Rapid System Prototyping (RSP), 2018
Pdf | Reference: Torino, Italy, 2018

Building Fast Multi-Agent Systems using Hardware Design Languages for High-Throughput Systems
Author: Jannis Stoppe, Christina Plump, Sebastian Huhn, Rolf Drechsler
Conference: 6th International Conference on Dynamics in Logistics (LDIC)
Pdf | Reference: Bremen, Germany, 2018

Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata
Author: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference: 35th IEEE International Conference on Computer Design (ICCD)
Pdf | Reference: Boston Area, Massachusetts, USA, 2017

Semi-Formal Cycle-Accurate Temporal Execution Traces Reconstruction
Author: Rehab Massoud, Jannis Stoppe, Daniel Große, Rolf Drechsler
Conference: 15th International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS)
Pdf | Reference: pp. 335-351, Berlin, Germany, 2017

BioViz: An Interactive Visualization Engine for Digital Microfluidic Biochips
Author: Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Bochum, Germany, 2017

Effects of Cell Shapes on the Routability of Digital Microfluidic Biochips
Author: Kevin Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Lausanne, Switzerland, 2017

Automatic Equivalence Checking for SystemC-TLM 2.0 Models Against their Formal Specifications
Author: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Lausanne, Switzerland, 2017

AIBA: an Automated Intra-Cycle Behavioral Analysis for SystemC-based Design Exploration
Author: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference: IEEE International Conference on Computer Design (ICCD)
Pdf | Reference: Phoenix, USA, 2016

Hardware/Software Co-Visualization on the Electronic System Level using SystemC
Author: Rolf Drechsler, Jannis Stoppe
Conference: International Conference on VLSI Design
Pdf | Reference: Kolkata, India, 2016

Verification-driven Design Across Abstraction Levels - A Case Study
Author: Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Funchal, Madeira, Portugal, 2015

Automated Feature Localization for Dynamically Generated SystemC Designs
Author: Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE'15)
Pdf | Reference: Grenoble, France, 2015

Validating SystemC Implementations Against Their Formal Specifications
Author: Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference: Symposium on Integrated Circuits and System Design (SBCCI)
Pdf | Reference: Aracaju, Brazil, 2014

RevVis: Visualization of Structures and Properties in Reversible Circuits
Author: Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler
Conference: Reversible Computation
Pdf | Reference: Kyoto, Japan, 2014

Cone of Influence Analysis at the Electronic System Level Using Machine Learning
Author: Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Santander, Spain, 2013

Data Extraction from SystemC Designs using Debug Symbols and the SystemC API
Author: Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Natal, Brazil, 2013

Time-stamps for Hardware Simulation Models Accurate Time-back Annotation
Author: Rehab Massoud, Jannis Stoppe, Karthik Maddikunta, Rolf Drechsler
Workshop: 5th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Dresden, Germany, 2018

Execution Environment for Dynamic Software Runtime Examination
Author: Kenneth Schmitz, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Workshop: 5th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Dresden, Germany, 2018

Making Waveforms Great Again
Author: Jannis Stoppe and Rolf Drechsler
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Lausanne, Switzerland, 2017

Verilog2GEXF - Dynamic Large Scale Circuit Visualization
Author: Kenneth Schmitz, Jannis Stoppe, Rolf Drechsler
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Lausanne, Switzerland, 2017

Der Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips
Author: Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: Bremen, Germany, 2017

SystemCDG - AI Based Coverage Driven Stimuli Generation for SystemC
Author: Jannis Stoppe, Arved Friedemann, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: Austin, TX, USA, 2016

Change Management for Hardware Designers
Author: Martin Ring, Jannis Stoppe, Christoph Lüth, Rolf Drechsler
Workshop: Workshop on Design Automation for Understanding Hardware Designs (DUHDE)
Reference: Dresden, Germany, 2016

Visualizing Microfluidic Biochips Interactively
Author: Jannis Stoppe, Oliver Keszöcze, Robert Wille, Rolf Drechsler
Workshop: Workshop on Design Automation for Understanding Hardware Designs (DUHDE)
Reference: Dresden, Germany, 2016

Ecore Model Generation from SystemC/C++ Implementations
Author: Jannis Stoppe, Rolf Drechsler
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Grenoble, France, 2015

Towards a Multi-dimensional and Dynamic Visualization for ESL Designs
Author: Jannis Stoppe, Marc Michael, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Reference: Dresden, Germany, 2014

« back


©2026 | Group of Computer Architecture | Contact | Legal & Data Privacy