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Arbeitsgruppe Rechnerarchitektur / AGRA | Informatik | FB03 | Universität Bremen

Dr. Jannis Stoppe


Mein Forschungsschwerpunkt liegt in der Untersuchung aktueller Beschreibungssprachen für den Hardware/Software-Entwurf. Zentrale Fragen sind dabei vor allem, wie solche hybriden Systeme visualisiert werden können und welche technischen Voraussetzungen dafür erfüllt werden müssen.

WiMi

MZH 4260

jstoppe@informatik.uni-bremen.de

Noch analog oder lebst Du schon?
Mit Nœrdman durch die Welt von heute... und morgen
Autor: Rolf Drechsler, Jannis Stoppe
Verlag: Springer
Format: Softcover, eBook (2021)

Computer: Wie funktionieren Smartphone, Tablet & Co.?
Autor: Rolf Drechsler, Andrea Fink, Jannis Stoppe
Verlag: Springer
Format: Taschenbuch (2017)

Automated Non-intrusive Analysis of Electronic System Level Designs
Autor: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Details: volume: 39, number: 2, pages: 492-505, URL: https://doi.org/10.1109/TCAD.2018.2889665, DOI: 10.1109/TCAD.2018.2889665, (2020)

Analyzing SystemC Designs: SystemC Analysis Approaches for Varying Applications
Autor: Jannis Stoppe, Rolf Drechsler
Zeitschrift: Sensors
Details: Volume (issue) 15(5), pages 10399-10421 (2015)

Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques
Autor: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Konferenz: IEEE International Symposium on Rapid System Prototyping (RSP), 2018
Pdf | Referenz: Torino, Italy, 2018

Building Fast Multi-Agent Systems using Hardware Design Languages for High-Throughput Systems
Autor: Jannis Stoppe, Christina Plump, Sebastian Huhn, Rolf Drechsler
Konferenz: 6th International Conference on Dynamics in Logistics (LDIC)
Pdf | Referenz: Bremen, Germany, 2018

Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata
Autor: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Konferenz: 35th IEEE International Conference on Computer Design (ICCD)
Pdf | Referenz: Boston Area, Massachusetts, USA, 2017

Semi-Formal Cycle-Accurate Temporal Execution Traces Reconstruction
Autor: Rehab Massoud, Jannis Stoppe, Daniel Große, Rolf Drechsler
Konferenz: 15th International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS)
Pdf | Referenz: pp. 335-351, Berlin, Germany, 2017

BioViz: An Interactive Visualization Engine for Digital Microfluidic Biochips
Autor: Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Bochum, Germany, 2017

Effects of Cell Shapes on the Routability of Digital Microfluidic Biochips
Autor: Kevin Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Lausanne, Switzerland, 2017

Automatic Equivalence Checking for SystemC-TLM 2.0 Models Against their Formal Specifications
Autor: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Lausanne, Switzerland, 2017

AIBA: an Automated Intra-Cycle Behavioral Analysis for SystemC-based Design Exploration
Autor: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Konferenz: IEEE International Conference on Computer Design (ICCD)
Pdf | Referenz: Phoenix, USA, 2016

Hardware/Software Co-Visualization on the Electronic System Level using SystemC
Autor: Rolf Drechsler, Jannis Stoppe
Konferenz: International Conference on VLSI Design
Pdf | Referenz: Kolkata, India, 2016

Verification-driven Design Across Abstraction Levels - A Case Study
Autor: Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Funchal, Madeira, Portugal, 2015

Automated Feature Localization for Dynamically Generated SystemC Designs
Autor: Jannis Stoppe, Robert Wille, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE'15)
Pdf | Referenz: Grenoble, France, 2015

Validating SystemC Implementations Against Their Formal Specifications
Autor: Jannis Stoppe, Robert Wille, Rolf Drechsler
Konferenz: Symposium on Integrated Circuits and System Design (SBCCI)
Pdf | Referenz: Aracaju, Brazil, 2014

RevVis: Visualization of Structures and Properties in Reversible Circuits
Autor: Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler
Konferenz: Reversible Computation
Pdf | Referenz: Kyoto, Japan, 2014

Cone of Influence Analysis at the Electronic System Level Using Machine Learning
Autor: Jannis Stoppe, Robert Wille, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Santander, Spain, 2013

Data Extraction from SystemC Designs using Debug Symbols and the SystemC API
Autor: Jannis Stoppe, Robert Wille, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Natal, Brazil, 2013

Time-stamps for Hardware Simulation Models Accurate Time-back Annotation
Autor: Rehab Massoud, Jannis Stoppe, Karthik Maddikunta, Rolf Drechsler
Workshop: 5th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Referenz: Dresden, Germany, 2018

Execution Environment for Dynamic Software Runtime Examination
Autor: Kenneth Schmitz, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Workshop: 5th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Referenz: Dresden, Germany, 2018

Making Waveforms Great Again
Autor: Jannis Stoppe and Rolf Drechsler
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Referenz: Lausanne, Switzerland, 2017

Verilog2GEXF - Dynamic Large Scale Circuit Visualization
Autor: Kenneth Schmitz, Jannis Stoppe, Rolf Drechsler
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Referenz: Lausanne, Switzerland, 2017

Der Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips
Autor: Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Referenz: Bremen, Germany, 2017

SystemCDG - AI Based Coverage Driven Stimuli Generation for SystemC
Autor: Jannis Stoppe, Arved Friedemann, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Referenz: Austin, TX, USA, 2016

Change Management for Hardware Designers
Autor: Martin Ring, Jannis Stoppe, Christoph Lüth, Rolf Drechsler
Workshop: Workshop on Design Automation for Understanding Hardware Designs (DUHDE)
Referenz: Dresden, Germany, 2016

Visualizing Microfluidic Biochips Interactively
Autor: Jannis Stoppe, Oliver Keszöcze, Robert Wille, Rolf Drechsler
Workshop: Workshop on Design Automation for Understanding Hardware Designs (DUHDE)
Referenz: Dresden, Germany, 2016

Ecore Model Generation from SystemC/C++ Implementations
Autor: Jannis Stoppe, Rolf Drechsler
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDe)
Referenz: Grenoble, France, 2015

Towards a Multi-dimensional and Dynamic Visualization for ESL Designs
Autor: Jannis Stoppe, Marc Michael, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Referenz: Dresden, Germany, 2014

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