Incorporating User Preferences in Many-Objective Optimization using Relation epsilon-Preferred
Autor: Nicole Drechsler, André Sülflow, Rolf Drechsler
Zeitschrift: Natural Computing
Details: DOI: 10.1007/s11047-014-9422-0, Volume 14, Issue 3, pp 469-483 (2015)

Latency Analysis for Sequential Circuits
Autor: Alexander Finder, André Sülflow, Görschwin Fey
Zeitschrift: IEEE Trans. on CAD of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2013.2292501, Volume 33, Number 4, pp. 643-647 (2014)

Automated Design Debugging in a Testbench-Based Verification Environment
Autor: Mehdi Dehbashi, André Sülflow, Görschwin Fey
Zeitschrift: Embedded Hardware Design - Microprocessors and Microsystems (MICPRO)
Details: DOI 10.1109/DSD.2011.67, Volume 37, Issue 2, pp. 206-217 (2013)

Effective Robustness Analysis using Bounded Model Checking Techniques
Autor: Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2011.2120950, Volume 30, Number 8, pp. 1239-1252 (2011)

Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen
Autor: Görschwin Fey, Andre Sülflow, Stefan Frehse, Rolf Drechsler
Zeitschrift: it-Information Technology
Details: DOI: 10.1524/itit.2010.0594, Volume 52, Number 4, pp. 216-223 (2010)

Latency Analysis for Sequential Circuits
Autor: Alexander Finder, André Sülflow, Görschwin Fey
Workshop: 23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2011
Pdf | Referenz: Passau, 2011

Towards Unifying Localization and Explanation for Automated Debugging
Autor: Görschwin Fey, André Sülflow, Rolf Drechsler
Workshop: 11th International Workshop on Microprocessor Test and Verification (MTV)
Pdf | Referenz: pp. 3-8, Austin, Texas, 2010

RobuCheck: A Robustness Checker for Digital Circuits
Autor: Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
Workshop: The First International Workshop on Dynamic Aspects in Dependability Models for Fault-Tolerant Systems (DYADEM-FTS)
Referenz: Valencia, 2010

VisSAT: Visualization of SAT Solver Internals
Autor: Robert Wille, Andre Sülflow, Christian Genz, Rolf Drechsler
Workshop: University Booth at Design, Automation and Test in Europe (DATE10)
Pdf | Referenz: Dresden, 2010

Using QBF to Increase the Accuracy of SAT-Based Debugging
Autor: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: International Workshop on Constraints in Formal Verification (CFV)
Pdf | Referenz: Grenoble, France, 2009

Model-Based Diagnosis for Programmable Logic Controllers
Autor: Andre Sülflow, Rolf Drechsler
Workshop: Gemeinsamer Workshop der Informatik-Graduiertenkollegs und Forschungskollegs
Referenz: Dagstuhl, 2009

Robustness Check for Multiple Faults using Formal Techniques
Autor: Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
Workshop: Constraints in Formal Verification (CFV)
Pdf | Referenz: Grenoble, France, 2009

FormED: A Formal Environment for Debugging
Autor: Andre Sülflow, Robert Wille, Christian Genz, Görschwin Fey, Rolf Drechsler
Workshop: University Booth at Design, Automation and Test in Europe (DATE09)
Pdf | Referenz: Nizza, 2009

Increasing the Accuracy of SAT-based Debugging
Autor: Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Workshop: 12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Pdf | Referenz: pp. 47-56, Berlin, 2009

Computing Bounds for Fault Tolerance using Formal Techniques
Autor: Andre Sülflow, Görschwin Fey, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Workshop: IEEE Workshop on Design for Reliability and Variability (DRV)
Pdf | Referenz: Santa Clara, USA, 2008

Experimental Studies on SMT-based Debugging
Autor: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: IEEE 9th Workshop on RTL and High Level Testing (WRTLT'08)
Pdf | Referenz: pp. 93-98, Japan, 2008

Debugging Design Errors by Using Unsatisfiable Cores
Autor: Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Workshop: 11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Pdf | Referenz: pp. 159-168, Freiburg, 2008

Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
Autor: Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler
Workshop: IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07)
Pdf | Referenz: pp. 31-36, Beijing, P.R.China, 2007

Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse
Autor: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: pp. 101-110, Erlangen, 2007