Lower the RISC: Designing optical-probing-attack-resistant cores
Author: Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler
Jorunal: Microprocessors and Microsystem
Details: DOI: 10.1016/j.micpro.2024.105121 (2024)

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation
Author: Sallar Ahmadi-Pour, Mathis Logemann, Vladimir Herdt, Rolf Drechsler
Jorunal: Chips
Details: DOI: 10.3390/chips2030012, Volume 2, Issue 3, pp. 195-208 (2023)

MARADIV: Library of MAGIC based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors
Author: Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler
Jorunal: IEEE Transactions on Circuits and Systems II: Express Briefs
Details: DOI: 10.1109/TCSII.2023.3242976, Volume: 70 Issue: 7 (2023)

The MicroRV32 framework: An Accessible and Configurable Open Source RISC-V Cross-Level Platform for Education and Research
Author: Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Jorunal: Journal of Systems Architecture - Embedded Software Design (JSA)
Details: DOI: 10.1016/j.sysarc.2022.102757, Volume 133, 2022 (2022)

MicroRV32, A RISC-V Platform for Education and Research
Author: Sallar Ahmadi-Pour, Rolf Drechsler
Workshop: Soft RISC-V Systems Workshop (SRvS Workshop)
Reference: Online Event, 2024

Cross-Level Verification of Hardware Peripherals
Author: Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Workshop: RISC-V Summit Europe
Pdf | Reference: Munich, Germany, 2024

LLM-Assisted High Quality Invariants Generation for Formal Verification
Author: Khushboo Qayyum, Sallar Ahmadi-Pour, Muhammad Hassan, Chandan Kumar Jha, Rolf Drechsler
Workshop: University Fair at Design, Automation and Test in Europe (DATE)
Reference: Valencia, Spain, 2024

Towards Completeness: Security Coverage for System Level IFT
Author: Ece Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Landau, Germany, 2024

Expanding RISC-V Horizons: Streamlining Heterogeneous Systems Evaluation with Open Source RISC-V AMS VP Framework
Author: Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Workshop: RISC-V Summit Europe
Pdf | Reference: Barcelona, Spain, 2023

Towards Comprehensive Verification of Hardware and Software for RISC-V based Embedded Systems
Author: Niklas Bruns, Sallar Ahmadi-Pour, Sören Tempel, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Freiburg, Germany, 2023

OPTI-RISK: Design of an Optical Probing Attack Hardened RISC-V Core with an Industrially Compatible CMOS Gate Library
Author: Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, and Rolf Drechsler
Workshop: 5th RISC-V Activity Workshop
Reference: Berlin, Germany, 2022

MicroRV32: An Open Source RISC-V Cross-Level Platform for Education and Research
Author: Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Workshop: Design Automation for CPS and IoT (DESTION)
Pdf | Reference: Nashville, USA, 2021

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
Author: Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: München, Germany, 2021

MicroRV32: A SpinalHDL based RISC-V Implementation for FPGAs
Author: Sallar Ahmadi-Pour, Vladimir Herdt and Rolf Drechsler
Workshop: University Booth at Design, Automation and Test in Europe (DATE)
Pdf | Reference: Grenoble, France, 2021