Within the Scale4Edge research project I am currently working on methods for verification and validation of embedded systems across layers of abstraction. A central aspect is the open standard instruction set architecture RISC-V which provides the interface between software and hardware.
LLM-assisted Bug Identification and Correction for Verilog HDL
LLM-assisted Bug Identification and Correction for Verilog HDL
FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits
MESSI: Task Mapping and Scheduling Strategy for FPGA-based Heterogeneous Real-Time Systems
Lower the RISC: Designing optical-probing-attack-resistant cores
Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation
MARADIV: Library of MAGIC based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors
The MicroRV32 framework: An Accessible and Configurable Open Source RISC-V Cross-Level Platform for Education and Research