HOME | CONTACT

Logo Universtity of Bremen
LOGO AGRA | AG Rechnerarchitektur



Group of Computer Architecture / AGRA | Computer Science | Faculty 03 | University of Bremen

Sallar Ahmadi-Pour, M.Sc.


Within the Scale4Edge research project I am currently working on methods for verification and validation of embedded systems across layers of abstraction. A central aspect is the open standard instruction set architecture RISC-V which provides the interface between software and hardware.

Research Staff

+49 421 218-63946

MZH 4290

sallar@uni-bremen.de

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation
Author: Sallar Ahmadi-Pour, Mathis Logemann, Vladimir Herdt, Rolf Drechsler
Jorunal: Chips
Details: DOI: 10.3390/chips2030012, Volume 2, Issue 3, pp. 195-208 (2023)

MARADIV: Library of MAGIC based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors
Author: Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler
Jorunal: IEEE Transactions on Circuits and Systems II: Express Briefs
Details: DOI: 10.1109/TCSII.2023.3242976, Volume: 70 Issue: 7 (2023)

The MicroRV32 framework: An Accessible and Configurable Open Source RISC-V Cross-Level Platform for Education and Research
Author: Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Jorunal: Journal of Systems Architecture - Embedded Software Design (JSA)
Details: DOI: 10.1016/j.sysarc.2022.102757, Volume 133, 2022 (2022)

Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study
Author: Mohammad Reza Heidari Iman, Sallar Ahmadi-Pour, Rolf Drechsler, Tara Ghasempouri
Conference: IEEE Nordic Circuits and Systems Conference (NorCAS)
Pdf | Reference: Lund, Sweden, 2024

From Bugs to Fixes: HDL Bug Identification and Patching using LLMs and RAG
Author: Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler
Conference: LLM-Aided Design, 2024 (LAD)
Pdf | Reference: San Jose, CA, USA, 2024

Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification
Author: Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2024

LLM-guided Formal Verification Coupled with Mutation Testing
Author: Muhammad Hassan, Sallar Ahmadi-Pour, Khushboo Qayyum, Chandan Kumar Jha, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Valencia, Spain, 2024

Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic
Author: Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler
Conference: International Conference on VLSI Design (VLSID)
Pdf | Reference: Kolkata, India, 2024

Security Coverage Metrics for Information Flow at the System Level
Author: Ece Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Incheon Songdo Convensia, South Korea, 2024

Virtual Prototypes and Open Source Hardware Design in Research and Education
Author: Sallar Ahmadi-Pour, Rolf Drechsler
Conference: The premier open source silicon conference (ORConf)
Reference: Munich, Germany, 2023

Hidden in Plain Sight: A Detailed Investigation of Selectively Increasing Local Density to Camouflage and Robustify Against Optical Probing Attacks
Author: Sajjad Parvin, Chandan Kumar Jha, Sallar Ahmadi-Pour, Frank Sill Torres, and Rolf Drechsler
Conference: IEEE International Test Conference India (ITC India)
Pdf | Reference: Bengaluru, India, 2023

Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core
Author: Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler
Conference: IEEE INTERNATIONAL CONFERENCE ON OMNI-LAYER INTELLIGENT SYSTEMS (IEEE COINS)
Pdf | Reference: Berlin, Germany, 2023

Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification
Author: Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: Turin, Italy, 2023

Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study
Author: Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler and Klaus McDonald-Maier
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Gran Canaria, Spain, 2022

RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems
Author: Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: Antibes, France, 2021

Cross-Level Verification of Hardware Peripherals
Author: Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Workshop: RISC-V Summit Europe
Pdf | Reference: Munich, Germany, 2024

LLM-Assisted High Quality Invariants Generation for Formal Verification
Author: Khushboo Qayyum, Sallar Ahmadi-Pour, Muhammad Hassan, Chandan Kumar Jha, Rolf Drechsler
Workshop: University Fair at Design, Automation and Test in Europe (DATE)
Reference: Valencia, Spain, 2024

Towards Completeness: Security Coverage for System Level IFT
Author: Ece Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Landau, Germany, 2024

Expanding RISC-V Horizons: Streamlining Heterogeneous Systems Evaluation with Open Source RISC-V AMS VP Framework
Author: Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Workshop: RISC-V Summit Europe
Pdf | Reference: Barcelona, Spain, 2023

Towards Comprehensive Verification of Hardware and Software for RISC-V based Embedded Systems
Author: Niklas Bruns, Sallar Ahmadi-Pour, Sören Tempel, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Freiburg, Germany, 2023

OPTI-RISK: Design of an Optical Probing Attack Hardened RISC-V Core with an Industrially Compatible CMOS Gate Library
Author: Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, and Rolf Drechsler
Workshop: 5th RISC-V Activity Workshop
Reference: Berlin, Germany, 2022

MicroRV32: An Open Source RISC-V Cross-Level Platform for Education and Research
Author: Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Workshop: Design Automation for CPS and IoT (DESTION)
Pdf | Reference: Nashville, USA, 2021

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
Author: Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: München, Germany, 2021

MicroRV32: A SpinalHDL based RISC-V Implementation for FPGAs
Author: Sallar Ahmadi-Pour, Vladimir Herdt and Rolf Drechsler
Workshop: University Booth at Design, Automation and Test in Europe (DATE)
Pdf | Reference: Grenoble, France, 2021

« back


©2023 | Group of Computer Architecture | Contact | Legal & Data Privacy