Im Kontext des Forschungsprojektes Scale4Edge arbeite ich an Methoden zur Verifikation und Validierung von eingebetteten Systemen zwischen verschiedenen Abstraktionebenen. Zentraler Aspekt ist die offene RISC-V Befehlssatzarchitektur, welche die Schnittstelle zwischen Software und Hardware bereitstellt.
Comparing Methods for the Cross-Level Verification of SystemC Peripherals with Symbolic Execution
LLM-assisted Bug Identification and Correction for Verilog HDL
FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits
MESSI: Task Mapping and Scheduling Strategy for FPGA-based Heterogeneous Real-Time Systems
Lower the RISC: Designing optical-probing-attack-resistant cores
Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation
MARADIV: Library of MAGIC based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors
The MicroRV32 framework: An Accessible and Configurable Open Source RISC-V Cross-Level Platform for Education and Research