Mein Forschungsgebiet umfasst im Großen und Ganzen den Entwurf, die Automatisierung und die Verifizierung von VLSI-Systemen. Ich arbeite an der Entwicklung effizienter CAD-Methoden für neue Technologien. Dazu gehören automatisierte Methoden für die Synthese, die formale Überprüfung und die Entwicklung von Benchmark-Schaltungen für neue Technologien. Derzeit beschäftige ich mich mit memristorbasierten Schaltungen und approximativem Rechnen.
Polynomial Debugging and Fault Correction of Combinational Circuits With Constant Cutwidth
Advanced And-Inverter Graph Decomposition Technique for Reducing Circuit Complexity
veriSiM: Formal Verification of Spice Netlists for MAGIC-Based Logic-in-Memory
LLM-assisted Bug Identification and Correction for Verilog HDL
FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits
Polynomial Formal Verification of Multi-Valued Approximate Circuits within Constant Cutwidth
Correct and Verify - CAV: Exploiting Binary Decision Diagrams to Enable Formal Verification of Approximate Adders with Correct Carry Bits
EnR: Extend and Reduce Methodology to Enable Formal Verification of Truncated Adders
Lower the RISC: Designing optical-probing-attack-resistant cores
veriSIMPLER : An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing
cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style
MARADIV: Library of MAGIC based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors
IMAGIN: Library of IMPLY and MAGIC NOR Based Approximate Adders for In-Memory Computing