My research focus is on ESL design, verification and (virtual) prototyping. The methodology enables the designer to efficiently, and cost-effectively optimize the design in comparison to RTL methodology. The main question I am trying to answer is if the software performs as expected (in terms of correctness and efficiency) on the target architecture, and if the architecture is capable to give the advertised functionality
Erweiterte virtuelle Prototypen für heterogene Systeme
Toward System-Level Assertions for Heterogeneous Systems
LLM-assisted Bug Identification and Correction for Verilog HDL
veriSiM: Formal Verification of Spice Netlists for MAGIC-Based Logic-in-Memory
LLM-assisted Bug Identification and Correction for Verilog HDL
Correct and Verify - CAV: Exploiting Binary Decision Diagrams to Enable Formal Verification of Approximate Adders with Correct Carry Bits
EnR: Extend and Reduce Methodology to Enable Formal Verification of Truncated Adders
cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits
ReSG: A Data Structure for Verification of Majority based In-Memory Computing on ReRAM Crossbars
Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits
Security Validation of VP-based SoCs Using Dynamic Information Flow Tracking