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Arbeitsgruppe Rechnerarchitektur / AGRA | Informatik | FB03 | Universität Bremen

Dr. Stephan Eggersglüß


Mein Tätigkeitsbereich ist das Erfüllbarkeitsproblem (SAT). Ein Schwerpunkt meiner Interessen ist das effiziente Lösen von SAT-Instanzen. Mein anderer Schwerpunkt liegt im Bereich 'Test Digitaler Schaltungen'. In diesem untersuche ich das Generieren von Testmustern für Dynamische Fehlermodelle auf Basis des Erfüllbarkeitsproblems.

WiMi

Test digitaler Schaltkreise
Autor: Stephan Eggersglüß, Görschwin Fey, Ilia Polian
Verlag: Oldenbourg
Format: Softcover (2014)

High Quality Test Pattern Generation and Boolean Satisfiability
Autor: Stephan Eggersglüß, Rolf Drechsler
Verlag: Springer
Format: Hardcover (2012)

Test Pattern Generation using Boolean Proof Engines
Autor: Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille
Verlag: Springer
Format: Hardcover (2009)

Robuste Erfüllbarkeitsalgorithmen für die Generierung hochwertiger Testmuster für digitale Schaltungen
Autor: Stephan Eggersglüß
Buchtitel: Ausgezeichnete Informatikdissertationen 2010 | Herausgeber: S. Hölldobler et al.
Verlag: GI
Format: Paperback (2011)

SWORD: A SAT like Prover Using Word Level Information
Autor: Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
Buchtitel: VLSI-SoC: Advanced Topics on Systems on a Chip: A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip | Herausgeber: Ricardo Reis, Vincent Mooney, Paul Hasler
Verlag: Springer
Format: Hardcover (2009)

On Optimization-based ATPG and its Application for Highly Compacted Test Sets
Autor: Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2016.2552822, Vol. 35(12), pp. 2104-2117 (2016)

Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets
Autor: Stephan Eggersglüß
Zeitschrift: Journal of Electronic Testing: Theory and Applications
Details: DOI: 10.1007/s10836-014-5472-6, Volume 30, Number 5, pp. 557-567 (2014)

An effective fault ordering heuristic for SAT-based dynamic test compaction techniques
Autor: Stephan Eggersglüß, Rolf Drechsler
Zeitschrift: it-Information Technology
Details: DOI: 10.1515/itit-2013-1041, Volume 56, Number 4, pp. 157-164 (2014)

A Highly Fault-Efficient SAT-Based ATPG Flow
Autor: Stephan Eggersglüß, Rolf Drechsler
Zeitschrift: IEEE Design & Test of Computers
Details: DOI: 10.1109/MDT.2012.2205479, Volume 29, Issue 4, pp. 63-70 (2012)

Efficient Data Structures and Methodologies for SAT-based ATPG providing High Fault Coverage in Industrial Application
Autor: Stephan Eggersglüß, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2011.2152450, Volume 30, Number 9, pp. 1411-1415 (2011)

Incremental Solving Techniques for SAT-based ATPG
Autor: Daniel Tille, Stephan Eggersglüß, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2010.2044673, Volume 29, Number 7, pp. 1125-1130 (2010)

MONSOON: SAT-based ATPG for Path Delay Faults Using Multiple-Valued Logics
Autor: Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Rolf Drechsler
Zeitschrift: Journal of Electronic Testing: Theory and Applications
Details: DOI: 10.1007/s10836-010-5146-y,Volume 26, Number 3, pp. 307-322, Pdf download (2010)

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
Autor: Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
Zeitschrift: it - information technology
Details: DOI: 10.1524/itit.2009.0529, Volume 51, Number 2, pp. 102-111, Pdf download (2009)

On Acceleration of SAT-based ATPG for Industrial Designs
Autor: Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2008.923107, Volume 27, Number 7, pp. 1329-1333 (2008)

Machine Learning-based Prediction of Test Power
Autor: Harshad Dhotre, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Baden Baden, Germany, 2019

Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements
Autor: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Konferenz: 20th IEEE Latin American Test Symposium (LATS)
Pdf | Referenz: Santiago, Chile, 2019

Constraint-based Pattern Retargeting for Reducing Localized Power Activity during Testing
Autor: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen
Konferenz: 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Budapest, Hungary, 2018

Approximation-aware Testing for Approximate Circuits
Autor: Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler
Konferenz: 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: pp. 239 - 244, Jeju, Korea, 2018

Revealing Properties of Structural Materials by Combining Regression-based Algorithms and Nano Indentation Measurements
Autor: Sebastian Huhn, Heike Sonnenberg, Stephan Eggersglüß, Brigitte Clausen, Rolf Drechsler
Konferenz: 10th IEEE Symposium Series on Computational Intelligence (SSCI)
Pdf | Referenz: Hawaii, USA, 2017

Identification of Efficient Clustering Techniques for Test Power Activity on the Layout
Autor: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Konferenz: 26th IEEE Asian Test Symposium (ATS)
Pdf | Referenz: Taipei, Taiwan, 2017

Reconfigurable TAP Controllers with Embedded Compression for Large Test Data Volume
Autor: Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler
Konferenz: 30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Referenz: Cambridge, UK, 2017

Machine Learning Based Test Pattern Analysis for Localizing Critical Power Activity Areas
Autor: Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler
Konferenz: 30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Referenz: Cambridge, UK, 2017

Optimization of Retargeting for IEEE 1149.1 TAP Controllers with Embedded Compression
Autor: Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Lausanne, Schweiz, 2017

Exploring Superior Structural Materials Using Multi-Objective Optimization and Formal Techniques
Autor: Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler
Konferenz: 6th IEEE International Symposium on Embedded Computing & System Design (ISED)
Pdf | Referenz: Indian Institute of Technology, Patna, India, 2016

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test
Autor: Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen
Konferenz: IEEE Asian Test Symposium (ATS)
Pdf | Referenz: Hiroshima, Japan, 2016

VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers
Autor: Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Amsterdam, Niederlande, 2016

SAT-Based Post-Processing for Regional Capture Power Reduction in At-Speed Scan Test Generation
Autor: Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Amsterdam, Niederlande, 2016

Compact Test Set Generation for Test Compression-based Designs
Autor: Stephan Eggersglüß
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Cluj-Napoca, Romania, 2015

Automated Formal Verification of X Propagation with Respect to Testability Issues
Autor: Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß
Konferenz: IEEE International Design and Test Symposium 2014 (IDT)
Pdf | Referenz: pp. 106-111, Algiers, Algerien, 2014

Recent Advances in SAT-based ATPG: Non-Standard Fault Models, Multi Constraints and Optimization
Autor: Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer
Konferenz: International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
Pdf | Referenz: pp. 1-10, Santorini, Greece, 2014

Optimization-based Multiple Target Test Generation for Highly Compacted Test Sets
Autor: Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Konferenz: 19th IEEE European Test Symposium (ETS)
Pdf | Referenz: Paderborn, Germany, 2014

Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill
Autor: Stephan Eggersglüß
Konferenz: 22nd IEEE Asian Test Symposium (ATS)
Pdf | Referenz: pp. 31-16, Yilan, Taiwan, 2013

Improved SAT-based ATPG: More Constraints, Better Compaction
Autor: Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Konferenz: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Pdf | Referenz: pp. 85-90, San Jose, USA, 2013

Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization
Autor: Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty
Konferenz: 21st IEEE Asian Test Symposium (ATS)
Pdf | Referenz: pp. 290-295, Niigata, Japan, 2012

A New SAT-based ATPG for Generating Highly Compacted Test Sets
Autor: Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
Konferenz: 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 230-235, Tallinn, Estonia, 2012

As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
Autor: Stephan Eggersglüß, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1291-1296, Grenoble, 2011

Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability
Autor: Stephan Eggersglüß, Rolf Drechsler
Konferenz: International Test Conference (ITC)
Pdf | Referenz: pp. 1-10, Austin, 2010

Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs
Autor: Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler
Konferenz: 15th IEEE European Test Symposium (ETS)
Pdf | Referenz: pp. 176-181, Prag, 2010

Efficient Test Generation with Maximal Crosstalk-Induced Noise using Unconstrained Aggressor Excitation
Autor: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS)
Pdf | Referenz: pp. 649-652, Paris, 2010

Timing Arc Based Logic Analysis for False Noise Reduction
Autor: Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler
Konferenz: IEEE/ACM International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: pp. 225-230, San Jose, 2009

Structural Heuristics for SAT-based ATPG
Autor: Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler
Konferenz: 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009)
Pdf | Referenz: pp. 77-82, Florianópolis, 2009

Speeding up SAT-based ATPG using Dynamic Clause Activation
Autor: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Konferenz: 18th Asian Test Symposium (ATS'09)
Pdf | Referenz: pp. 177-182, Taichung, 2009

Increasing Robustness of SAT-based Delay Test Generation using Efficient Dynamic Learning Techniques
Autor: Stephan Eggersglüß, Rolf Drechsler
Konferenz: 14th IEEE European Test Symposium (ETS)
Pdf | Referenz: pp. 81-86, Sevilla, 2009

On the Influence of Boolean Encodings in SAT-based ATPG for Path Delay Faults
Autor: Stephan Eggersglüß, Rolf Drechsler
Konferenz: 38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Pdf | Referenz: pp. 94-99, Dallas, 2008

SWORD: A SAT like Prover Using Word Level Information
Autor: Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
Konferenz: IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC)
Pdf | Referenz: pp. 88-93, Atlanta, 2007

Improving Test Pattern Compactness in SAT-based ATPG
Autor: Stephan Eggersglüß, Rolf Drechsler
Konferenz: 16th Asian Test Symposium (ATS’07)
Pdf | Referenz: pp. 445-450, Beijing, 2007

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Autor: Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel
Konferenz: Fifth ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2007)
Pdf | Referenz: pp. 181-187, Nice, 2007

Experimental Studies on SAT-based ATPG for Gate Delay Faults
Autor: Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Konferenz: 37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Pdf | Referenz: Oslo, 2007

SAT-based ATPG for Path Delay Faults in Sequential Circuits
Autor: Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'07)
Pdf | Referenz: pp. 3671-3674, New Orleans, 2007

Power-Layout-Aware Test Pattern Re-scheduling
Autor: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Workshop: 32. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2020)
Referenz: Stuttgart, Germany, 2020

Enhanced Embedded Test Compression Technique For Processing Incompressible Test Patterns
Autor: Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler
Workshop: 31. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Referenz: Prien am Chiemsee, Germany, 2019

IR-drop Prediction of Test Patterns Using Parasitic Elements
Autor: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Workshop: 31. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2019)
Referenz: Prien am Chiemsee, Germany, 2019

A Codeword-based Compaction Technique for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks
Autor: Sebastian Huhn, Marcel Merten, Stephan Eggersglüß and Rolf Drechsler
Workshop: 30. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Referenz: Freiburg (Breisgau), Germany, 2018

ATPG Constraint Analysis for Reducing Regional Power Activity
Autor: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen
Workshop: 30. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2018)
Referenz: Freiburg (Breisgau), Germany, 2018

A Lightweight Method for Transient Test Power Pattern Analysis for Pattern Selection
Autor: Harshad Dhotre, Stephan Eggersglüß
Workshop: 29. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2017)
Referenz: Lübeck, Germany, 2017

Leichtgewichtige Datenkompressions-Architektur für IEEE 1149.1-kompatible Testschnittstellen
Autor: Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler
Workshop: 28. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Referenz: Siegen, Germany, 2016

Eliminierung von energieunsicheren Tests in kompakten Testmengen
Autor: Stephan Eggersglüß
Workshop: 28. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Referenz: Siegen, Germany, 2016

Erzeugung diagnostischer Testmuster unter komplexen Constraints
Autor: Tobias Koal, Stephan Eggersglüß, Mario Schölzel
Workshop: GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Referenz: Bad Urach, 2015

Hohe Testmengenkompaktierung durch formale Optimierungstechniken
Autor: Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Workshop: Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Referenz: Bad Staffelstein, 2014

Using Optimization Techniques to Increase Test Compaction
Autor: Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Workshop: IEEE 14th Workshop on RTL and High Level Testing (WRTLT'13)
Referenz: Yilan, Taiwan, 2013

Towards Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints
Autor: Stephan Eggersglüß, Melanie Diepenbeck, Robert Wille, Rolf Drechsler
Workshop: IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12)
Pdf | Referenz: Niigata, Japan, 2012

Formal Analysis Techniques: A Basis for High-Quality Designs
Autor: Stephan Eggersglüß, Rolf Drechsler
Workshop: IEEE International Workshop on Processor Verification, Test and Debug
Pdf | Referenz: Invited Talk, Trondheim, 2011

On Timing-Aware ATPG using Pseudo-Boolean Optimization
Autor: Stephan Eggersglüß, Rolf Drechsler
Workshop: IEEE European Test Symposium (ETS), Informal Digest of Papers
Pdf | Referenz: Trondheim, 2011

As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
Autor: Stephan Eggersglüß, Rolf Drechsler
Workshop: 23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2011
Pdf | Referenz: Passau, 2011

A Two-Stage SAT-based ATPG Approach with Reduced Switching Activity
Autor: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Workshop: Second International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR) 2009
Pdf | Referenz: Sevilla, Spain, 2009

Robust Tests for Transition Faults with Long Propagation Paths Using Boolean Satisfiability
Autor: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Workshop: IEEE European Test Symposium (ETS), Informal Digest of Papers
Pdf | Referenz: Lago Maggiore, 2008

SAT-based ATPG for Path Delay Fault in Industrial Circuits
Autor: Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel
Workshop: IEEE European Test Symposium (ETS), Informal Digest of Papers
Referenz: Freiburg, 2007

Studies on Integrating SAT-based ATPG in an Industrial Environment
Autor: Daniel Tille, Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Workshop: 19. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
Pdf | Referenz: Erlangen, 2007

Formal Verification on the Word Level using SAT-like Proof Techniques
Autor: Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Referenz: pp. 165-173, Erlangen, 2007

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