Mein Interessenschwerpunkt liegt in der Verifikation von Systemen auf hoher Abstraktionsebene. Zurzeit befasse ich mich insbesondere mit vollautomatischen formalen Methoden zur Eigenschaftsprüfung sowie Fehlersuche in SystemC (TLM) Modellen. Die inherente Nebenläufigkeit der Modelle, sowie die große Menge an möglichen Eingaben, erfordern spezielle Beweistechniken.
Verbessertes virtuelles Prototyping
Enhanced Virtual Prototyping: Featuring RISC-V Case Studies
Complete Symbolic Simulation of SystemC Models: Efficient Formal Verification of Finite Non-Terminating Programs
Verbessertes Virtual Prototyping für den Entwurfsablauf
Extensible and Configurable RISC-V Based Virtual Prototype
Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach
On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-Based Error Effect Simulation: A Case Study
Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation
Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT
The MicroRV32 framework: An Accessible and Configurable Open Source RISC-V Cross-Level Platform for Education and Research
Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype
Towards Quantification and Visualization of the Effects of Concretization during Concolic Testing
SymEx-VP: An Open Source Virtual Prototype for OS-Agnostic Concolic Testing of IoT Firmware
Advanced Virtual Prototyping for Cyber-Physical Systems using RISC-V: Implementation, Verification and Challenges
Towards RISC-V CSR Compliance Testing
Adaptive Simulation with Virtual Prototypes in an Open-Source RISC-V Evaluation Platform
RISC-V based Virtual Prototype: An Extensible and Configurable Platform for the System-level
Combining Sequentialization-based Verification of Multi-Threaded C Programs with Symbolic Partial Order Reduction
Verifying SystemC using Intermediate Verification Language and Stateful Symbolic Simulation