metaSMT: Focus On Your Application And Not On Solver Integration
Autor: Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey
Zeitschrift: International Journal of Software Tools for Technology Transfer
Details: DOI 10.1007/s10009-016-0426-1, 19(5):605-621 (2017)

Debugging hardware designs using dynamic dependency graphs
Autor: Jan Malburg, Alexander Finder, Görschwin Fey
Zeitschrift: Microprocessors and Microsystems (MICPRO)
Details: DOI: 10.1016/j.micpro.2016.10.004 (2016)

Empirical Results on Parity-based Soft Error Detection with Software-based Retry
Autor: Gökçe Aydos, Görschwin Fey
Zeitschrift: Microprocessors and Microsystems (MICPRO)
Details: DOI: 10.1016/j.micpro.2016.09.009, Volume 48 (2016)

Transaction-based online debug for NoC-based multiprocessor SoCs
Autor: Mehdi Dehbashi, Görschwin Fey
Zeitschrift: Microprocessors and Microsystems (MICPRO)
Details: DOI: 10.1016/j.micpro.2015.03.003, 39(3): 157-166 (2015)

A Simulation Based Approach for Automated Feature Localization
Autor: Jan Malburg, Alexander Finder, Görschwin Fey
Zeitschrift: IEEE Trans. on CAD of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2014.2360462, Volume:33, Issue: 12, pp. 1886-1899 (2014)

Latency Analysis for Sequential Circuits
Autor: Alexander Finder, André Sülflow, Görschwin Fey
Zeitschrift: IEEE Trans. on CAD of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2013.2292501, Volume 33, Number 4, pp. 643-647 (2014)

Debug Automation for Logic Circuits Under Timing Variations
Autor: Mehdi Dehbashi, Görschwin Fey
Zeitschrift: IEEE Design & Test of Computers
Details: DOI 10.1109/MDAT.2013.2266393, Volume 30, Issue 6, pp. 60-69 (2013)

Automated Design Debugging in a Testbench-Based Verification Environment
Autor: Mehdi Dehbashi, André Sülflow, Görschwin Fey
Zeitschrift: Embedded Hardware Design - Microprocessors and Microsystems (MICPRO)
Details: DOI 10.1109/DSD.2011.67, Volume 37, Issue 2, pp. 206-217 (2013)

Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis
Autor: Daniel Große, Görschwin Fey, Rolf Drechsler
Zeitschrift: Electronic Communications of the EASST
Details: DOI 10.14279/tuj.eceasst.62.860, Volume 62, pp. 13 (2013)

Effective Robustness Analysis using Bounded Model Checking Techniques
Autor: Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2011.2120950, Volume 30, Number 8, pp. 1239-1252 (2011)

Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen
Autor: Görschwin Fey, Andre Sülflow, Stefan Frehse, Rolf Drechsler
Zeitschrift: it-Information Technology
Details: DOI: 10.1524/itit.2010.0594, Volume 52, Number 4, pp. 216-223 (2010)

MONSOON: SAT-based ATPG for Path Delay Faults Using Multiple-Valued Logics
Autor: Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Rolf Drechsler
Zeitschrift: Journal of Electronic Testing: Theory and Applications
Details: DOI: 10.1007/s10836-010-5146-y,Volume 26, Number 3, pp. 307-322, Pdf download (2010)

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
Autor: Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
Zeitschrift: it - information technology
Details: DOI: 10.1524/itit.2009.0529, Volume 51, Number 2, pp. 102-111, Pdf download (2009)

Advanced Verification by Automatic Property Generation
Autor: Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
Zeitschrift: IET Computers & Digital Techniques
Details: DOI: 10.1049/iet-cdt.2008.0110, Volume 3, Issue 4, pp. 338-353 (2009)

On Acceleration of SAT-based ATPG for Industrial Designs
Autor: Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2008.923107, Volume 27, Number 7, pp. 1329-1333 (2008)

On the Construction of Small Fully Testable Circuits with Low Depth
Autor: Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
Zeitschrift: Embedded Hardware Design - Microprocessors and Microsystems (MICPRO)
Details: DOI: 10.1016/j.micpro.2008.03.005, Special Issue, Volume 32, Issues 5-6, pp. 263-269 (2008)

Automatic Fault Localization for Property Checking
Autor: Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2008.923234, Volume 27, Number 6, pp. 1138-1149, June (2008)

Building Free Binary Decision Diagrams Using SAT Solvers
Autor: Robert Wille, Görschwin Fey, Rolf Drechsler
Zeitschrift: Facta Universitatis, Series: Electronics and Energetics
Details: DOI: 10.2298/FUEE0703381W, Volume 20, Number 3, pp. 381-394, (2007)

An Integrated Approach for Combining BDDs and SAT Provers
Autor: Rolf Drechsler, Görschwin Fey, Sebastian Kinder
Zeitschrift: Facta Universitatis, Series: Electronics and Energetics
Details: DOI: 10.2298/FUEE0703415D, Volume 20, Number 3, pp. 415-436 (2007)

Minimizing the Number of Paths in BDDs - Theory and Algorithm
Autor: Görschwin Fey, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2005.852662, Volume 25, Number 1, pp. 4-11 (2006)

Project-Based Learning in Student Teams in Computer Science Education
Autor: Andreas Breiter, Görschwin Fey, Rolf Drechsler
Zeitschrift: Facta Universitatis, Series: Electronics and Energetics
Details: DOI: 10.2298/FUEE0502165B, Volume 18, Number 2, pp. 165-180 (2005)

Synthesis of Fully Testable Circuits from BDDs
Autor: Rolf Drechsler, Junhao Shi, Görschwin Fey
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2004.823342, Volume 23, Number 3 (2004)

Computing Exact Fault Candidates Incrementally
Autor: Heinz Riener, Görschwin Fey
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Referenz: Lausanne, Switzerland, 2017

Mining Latency Guarantees for RT-level Designs
Autor: Jan Malburg, Heinz Riener, Görschwin Fey
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Referenz: Lausanne, Switzerland, 2017

Counterexample-Guided EF Synthesis of Boolean Functions
Autor: Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Referenz: Bremen, Germany, 2017

Counterexample-Guided Diagnosis
Autor: Heinz Riener, Görschwin Fey
Workshop: International Verification and Security Workshop (IVSW'16)
Pdf | Referenz: Sant Feliu de Guixols, Catalunya, Spain, 2016

Generating good properties from a small number of use cases
Autor: Jan Malburg, Tino Flenker, Görschwin Fey
Workshop: International Verification and Security Workshop (IVSW'16)
Referenz: Sant Feliu de Guixols, Catalunya, Spain, 2016

SMT-Based CPS Parameter Synthesis
Autor: Heinz Riener, Robert Könighofer, Görschwin Fey, Roderick Bloem
Workshop: Applied Verification for Continuous and Hybrid Systems (ARCH@CPSWeek'16)
Pdf | Referenz: pp. 126-133, Vienna, Austria, 2016

Matching Abstract and Concrete Hardware Models for Design Understanding
Autor: Tino Flenker, Görschwin Fey
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDE)
Pdf | Referenz: Dresden, Germany, 2016

A Hybrid Algorithm to Conservatively Check the Robustness of Circuits
Autor: Niels Thole, Lorena Anghel, Görschwin Fey
Workshop: 28. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Referenz: Siegen, Germany, 2016

Parity-based Soft Error Detection with Software-based Retry vs. Triplication-based Soft Error Correction - An Analytical Comparison on a Flash-based FPGA Architecture
Autor: Gökçe Aydos, Görschwin Fey
Workshop: Workshop Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen
Pdf | Referenz: Cottbus, Germany, 2015

Path-Based Program Repair
Autor: Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Workshop: 12th International Workshop on Formal Engineering approaches to Software Components and Architectures, Satellite event of ETAPS (FESCA'15)
Pdf | Referenz: pp. 22-32, London, United Kingdoms, 2015

Analyzing an SET at Gate Level using a Conservative Approach
Autor: Niels Thole, Görschwin Fey, Alberto Garcia-Ortiz
Workshop: GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Referenz: Bad Urach, 2015

Execution Tracing of C Code for Formal Analysis
Autor: Heinz Riener, Michael Kirkedal Thomsen, Görschwin Fey
Workshop: 18. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'15)
Referenz: Chemnitz, Germany, 2015

Towards analysing feature locations through testing traces with BUT4Reuse
Autor: Jabier Martinez, Jan Malburg, Tewfik Ziadi, Görschwin Fey
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDe)
Referenz: Grenoble, France, 2015

Mutation based Feature Localization
Autor: Jan Malburg, Emmanuelle Encrenaz-Tiphene, Görschwin Fey
Workshop: 15th International Workshop on Microprocessor Test and Verification
Pdf | Referenz: Austin, USA, 2014

Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques (Extended Abstract)
Autor: Jan Malburg, Niklas Krafczyk, Görschwin Fey
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Pdf | Referenz: page 30, Dresden, Germany, 2014

Mutation based Feature Localization
Autor: Jan Malburg, Emmanuelle Encrenaz-Tiphene, Görschwin Fey
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Referenz: pp. 55-60, Dresden, Germany, 2014

Equivalence Checking on System Level using Stepwise Induction
Autor: Niels Thole, Görschwin Fey
Workshop: 17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Pdf | Referenz: Böblingen, Germany, 2014

A Logic for Cardinality Constraints
Autor: Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey
Workshop: 17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Referenz: Böblingen, Germany, 2014

Debug Automatisierung für logische Schaltungen unter Zeitvariation mittels Waveforms
Autor: Mehdi Dehbashi, Görschwin Fey
Workshop: 26. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Referenz: Bad Staffelstein, Germany, 2014

Yet a Better Error Explanation Algorithm
Autor: Heinz Riener, Görschwin Fey
Workshop: 16. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'13)
Pdf | Referenz: pp.193-194, Rostock, Germany, 2013

Towards Debug Automation for Timing Bugs at RTL
Autor: Mehdi Dehbashi, Görschwin Fey
Workshop: 25. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Referenz: Dresden, Germany, 2013

Verification of Embedded Systems Using Modeling and Implementation Languages
Autor: Mathias Soeken, Heinz Riener, Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop: International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs'12)
Pdf | Referenz: pp. 67-72, Tampere, Finland, 2012

Model-Based Diagnosis versus Error Explanation
Autor: Heinz Riener, Görschwin Fey
Workshop: International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES'12) in conjunction with 49th Design Automation Conference (DAC'12)
Pdf | Referenz: San Francisco, USA, 2012

FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation
Autor: Heinz Riener, Görschwin Fey
Workshop: 19th International SPIN Workshop on Model Checking of Software (SPIN'12)
Pdf | Referenz: pp. 234-240, Oxford, United Kingdoms, 2012

Functional Analysis of Circuits Under Timing Variations
Autor: Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Workshop: edaWorkshop
Pdf | Referenz: Hannover, Germany, 2012

Automated Debugging from Pre-Silicon to Post-Silicon
Autor: Mehdi Dehbashi, Görschwin Fey
Workshop: 24. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Referenz: Cottbus, Germany, 2012

Automated Feature Localization for Hardware Designs using Coverage Metrics
Autor: Jan Malburg, Alexander Finder, Görschwin Fey
Workshop: 15. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Referenz: pp. 85-96, Kaiserslautern, Germany, 2012

metaSMT: Focus on Your Application not on Solver Integration
Autor: Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler
Workshop: DIFTS'11: 1st International workshop on design and implementation of formal tools and systems
Pdf | Referenz: pp. 22-29, Austin, USA, 2011

Test Case Generation from Mutants using Model Checking Techniques
Autor: Heinz Riener, Roderick Bloem, Görschwin Fey
Workshop: IEEE Fourth International Conference on Software Testing, Verification and Validation Workshops (ICSTW'11)
Pdf | Referenz: pp. 388-397, Berlin, Germany, 2011

Towards Automatic Property Generation for the Formal Verification of Bus Bridges
Autor: Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Workshop: 14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz: Oldenburg, 2011

Latency Analysis for Sequential Circuits
Autor: Alexander Finder, André Sülflow, Görschwin Fey
Workshop: 23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2011
Pdf | Referenz: Passau, 2011

Towards Unifying Localization and Explanation for Automated Debugging
Autor: Görschwin Fey, André Sülflow, Rolf Drechsler
Workshop: 11th International Workshop on Microprocessor Test and Verification (MTV)
Pdf | Referenz: pp. 3-8, Austin, Texas, 2010

Evaluating Debugging Algorithms from a Qualitative Perspective
Autor: Alexander Finder, Görschwin Fey
Workshop: International Workshop on Boolean Problems
Pdf | Referenz: Freiberg, 2010

RobuCheck: A Robustness Checker for Digital Circuits
Autor: Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
Workshop: The First International Workshop on Dynamic Aspects in Dependability Models for Fault-Tolerant Systems (DYADEM-FTS)
Referenz: Valencia, 2010

A Better-Than-Worst-Case Robustness Measure
Autor: Stefan Frehse, Görschwin Fey, Rolf Drechsler
Workshop: 22. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2010
Pdf | Referenz: Paderborn, 2010

Using QBF to Increase the Accuracy of SAT-Based Debugging
Autor: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: International Workshop on Constraints in Formal Verification (CFV)
Pdf | Referenz: Grenoble, France, 2009

Robustness Check for Multiple Faults using Formal Techniques
Autor: Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
Workshop: Constraints in Formal Verification (CFV)
Pdf | Referenz: Grenoble, France, 2009

FormED: A Formal Environment for Debugging
Autor: Andre Sülflow, Robert Wille, Christian Genz, Görschwin Fey, Rolf Drechsler
Workshop: University Booth at Design, Automation and Test in Europe (DATE09)
Pdf | Referenz: Nizza, 2009

Algorithms for ATPG under Leakage Constraints
Autor: Görschwin Fey
Workshop: 21. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2009
Pdf | Referenz: Bremen, 2009

Increasing the Accuracy of SAT-based Debugging
Autor: Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Workshop: 12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Pdf | Referenz: pp. 47-56, Berlin, 2009

Computing Bounds for Fault Tolerance using Formal Techniques
Autor: Andre Sülflow, Görschwin Fey, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Workshop: IEEE Workshop on Design for Reliability and Variability (DRV)
Pdf | Referenz: Santa Clara, USA, 2008

Experimental Studies on SMT-based Debugging
Autor: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: IEEE 9th Workshop on RTL and High Level Testing (WRTLT'08)
Pdf | Referenz: pp. 93-98, Japan, 2008

Effiziente automatische Generierung von Assertions für industrielle Hardware-Designs
Autor: Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
Workshop: Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
Referenz: Dresden, 2008

Targeting Leakage Constraints during ATPG
Autor: Görschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita
Workshop: IEEE International Workshop on Silicon Debug and Diagnosis
Pdf | Referenz: San Diego, 2008

Debugging Design Errors by Using Unsatisfiable Cores
Autor: Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Workshop: 11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Pdf | Referenz: pp. 159-168, Freiburg, 2008

Formal Robustness Checking
Autor: Görschwin Fey, Rolf Drechsler
Workshop: Workshop on Constraints in Formal Verification, 2007
Pdf | Referenz: Bremen, 2007

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
Autor: Rolf Drechsler, Görschwin Fey, Jürgen Schlöffel
Workshop: edaWorkshop 2007
Referenz: Hannover, 2007

Building Free Binary Decision Diagrams Using SAT Solvers
Autor: Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop: 8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007)
Referenz: Oslo, 2007

SAT-based ATPG for Path Delay Fault in Industrial Circuits
Autor: Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel
Workshop: IEEE European Test Symposium (ETS), Informal Digest of Papers
Referenz: Freiburg, 2007

Estimating the Quality of AND-EXOR Optimization Results
Autor: Sebastian Kinder, Görschwin Fey and Rolf Drechsler
Workshop: 8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007)
Referenz: Oslo, 2007

Studies on Integrating SAT-based ATPG in an Industrial Environment
Autor: Daniel Tille, Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Workshop: 19. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
Pdf | Referenz: Erlangen, 2007

Instance Generation for SAT-based ATPG
Autor: Daniel Tille, Görschwin Fey, Rolf Drechsler
Workshop: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Pdf | Referenz: Krakau, 2007

Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse
Autor: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: pp. 101-110, Erlangen, 2007

Formal Verification on the Word Level using SAT-like Proof Techniques
Autor: Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Referenz: pp. 165-173, Erlangen, 2007

Efficiency of Multi-Valued Encoding in SAT-based ATPG
Autor: Görschwin Fey, Junhao Shi , Rolf Drechsler
Workshop: 18. Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“
Referenz: Titisee, 2006

SAT-Based Calculation of Source Code Coverage for BMC
Autor: Görschwin Fey, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: Dresden, 2006

SyCE: An Integrated Environment for System Design in SystemC
Autor: Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große
Workshop: 16th IEEE International Workshop on Rapid System Prototyping (RSP)
Pdf | Referenz: pp. 258-260, Montreal, 2005

PASSAT: Efficient SAT-based Test Pattern Generation
Autor: Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Workshop: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Referenz: Sopron, 2005

Efficient Hierarchical System Debugging for Property Checking
Autor: Görschwin Fey, Rolf Drechsler
Workshop: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Sopron, 2005

ParSyC: An Efficient SystemC Parser
Autor: Görschwin Fey, Daniel Große, Tim Cassens, Christian Genz, Tim Warode, Rolf Drechsler
Workshop: 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004)
Pdf | Referenz: pp. 148-154, Kanazawa, 2004

Design Understanding by Automatic Property Generation
Autor: Rolf Drechsler, Görschwin Fey
Workshop: 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004)
Pdf | Referenz: pp.274-281, Kanazawa, 2004

Experimental Studies on Test Pattern Generation for BDD Circuits
Autor: Junhao Shi, Görschwin Fey, Rolf Drechsler
Workshop: International Workshop on Boolean Problems (IWSBP)
Pdf | Referenz: pp. 71-76, Freiberg, 2004

Visualization of Diagnosis Results for Design Debugging
Autor: Görschwin Fey, Rolf Drechsler
Workshop: 13th International Workshop on Post-Binary ULSI Systems
Referenz: pp. 1-2, Toronto, 2004

Disjoint Sum of Product Minimization by Evolutionary Algorithms
Autor: Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler
Workshop: 1st European Workshop on Hardware Optimisation Techniques (EvoHOT)
Pdf | Referenz: Applications of Evolutionary Computing: EvoWorkshops 2004, LNCS 3005, p. 198-207, Coimbra, 2004

An Approach to Formal Verification of Reconfigurable Systems
Autor: Görschwin Fey, Rolf Drechsler, Muazzam Ali
Workshop: 1st IFIP WG 10.5 Workshop on "Frontiers in Automotive Electronics"
Referenz: Darmstadt, 2003

BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
Autor: Junhao Shi, Görschwin Fey and Rolf Drechsler
Workshop: IEEE European Test Workshop (ETW'03)
Pdf | Referenz: pp. 109-110, Maastricht, 2003, 2003

BDD Circuit Optimization for Path Delay Fault-Testability
Autor: Görschwin Fey, Junhao Shi, Rolf Drechsler
Workshop: 15th ITG/GMM/GI Workshop Test methods and Reliability of Circuits and Systems
Referenz: Timmendorfer Strand, 2003 , 2003

A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization
Autor: Görschwin Fey, Rolf Drechsler
Workshop: 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2003)
Referenz: pp. 54-60, Hiroshima , 2003

Cost-efficient Formal Block Verification for ASIC Design
Autor: K. Winkelmann, J. Trylus, D. Stoffel, Görschwin Fey
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: pp. 184-188, Bremen, 2003

Minimizing the Number of Paths in BDDs
Autor: Görschwin Fey, Rolf Derchsler
Workshop: International Workshop on Boolean Problems
Pdf | Referenz: pp. 149 - 156, Freiberg, 2002