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Arbeitsgruppe Rechnerarchitektur / AGRA | Informatik | FB03 | Universität Bremen

Prof. Dr.-Ing. Görschwin Fey


Seit März 2012 leite ich die AG Zuverlässige Eingebettete Systeme, die im Rahmen einer Kooperationsprofessur mit der Abteilungsleitung der Abteilung Avioniksysteme im Institut für Raumfahrtsysteme des Deutschen Zentrums für Luft- und Raumfahrt (DLR) verknüpft ist.

Leitung

Debug Automation from Pre-Silicon to Post-Silicon
Autor: Mehdi Dehbashi, Görschwin Fey
Verlag: Springer
Format: eBook, Hardcover (2015)

Test digitaler Schaltkreise
Autor: Stephan Eggersglüß, Görschwin Fey, Ilia Polian
Verlag: Oldenbourg
Format: Softcover (2014)

Test Pattern Generation using Boolean Proof Engines
Autor: Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille
Verlag: Springer
Format: Hardcover (2009)

Robustness and Usability in Modern Design Flows
Autor: Görschwin Fey, Rolf Drechsler
Verlag: Springer
Format: Hardcover (2008)

SATRIX - Algorithmen für Boolesche Erfüllbarkeit
Autor: Daniel Große, Görschwin Fey, Rolf Drechsler (Hrsg.)
Verlag: Shaker Verlag
Format: Gebunden (2007)

Advanced BDD Optimization
Autor: Rüdiger Ebendt, Görschwin Fey, Rolf Drechsler
Verlag: Springer Verlag
Format: Hardcover (2005)

FunTaskIC - Eine integrierte Entwurfsumgebung für SystemC
Autor: Görschwin Fey, Rolf Drechsler (Hrsg.)
Verlag: Shaker Verlag
Format: Gebunden (2005)

Evaluating Debugging Algorithms from a Qualitative Perspective
Autor: Alexander Finder, Görschwin Fey
Buchtitel: System Specification and Design Languages: Selected Contributions from FDL 2010 | Herausgeber: Tom J. Kazmierski, Adam Morawiec
Verlag: Springer
Format: Hardcover (2012)

Assessing System Vulnerability Using Formal Verification Techniques
Autor: Görschwin Fey
Buchtitel: Mathematical and Engineering Methods in Computer Science | Herausgeber: Zdeněk Kotásek, Jan Bouda, Ivana Černá, Lukáš Sekanina, Tomáš Vojnar, David Antoš
Verlag: Springer
Format: Hardcover (2012)

Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis
Autor: Daniel Große, Görschwin Fey, Rolf Drechsler
Buchtitel: Design and Test Technology for Dependable Systems-on-Chip | Herausgeber: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus
Verlag: Information Science Reference
Format: Hardcover (2011)

SWORD: A SAT like Prover Using Word Level Information
Autor: Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
Buchtitel: VLSI-SoC: Advanced Topics on Systems on a Chip: A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip | Herausgeber: Ricardo Reis, Vincent Mooney, Paul Hasler
Verlag: Springer
Format: Hardcover (2009)

Automatic Test Pattern Generation
Autor: Rolf Drechsler, Görschwin Fey
Buchtitel: Formal Methods for Hardware Verification, LNCS 3965 | Herausgeber: Marco Bernardo, Alessandro Cimatti
Verlag: Springer
Format: gebunden (2006)

metaSMT: Focus On Your Application And Not On Solver Integration
Autor: Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey
Zeitschrift: International Journal of Software Tools for Technology Transfer
Details: DOI 10.1007/s10009-016-0426-1, 19(5):605-621 (2017)

Debugging hardware designs using dynamic dependency graphs
Autor: Jan Malburg, Alexander Finder, Görschwin Fey
Zeitschrift: Microprocessors and Microsystems (MICPRO)
Details: DOI: 10.1016/j.micpro.2016.10.004 (2016)

Empirical Results on Parity-based Soft Error Detection with Software-based Retry
Autor: Gökçe Aydos, Görschwin Fey
Zeitschrift: Microprocessors and Microsystems (MICPRO)
Details: DOI: 10.1016/j.micpro.2016.09.009, Volume 48 (2016)

Transaction-based online debug for NoC-based multiprocessor SoCs
Autor: Mehdi Dehbashi, Görschwin Fey
Zeitschrift: Microprocessors and Microsystems (MICPRO)
Details: DOI: 10.1016/j.micpro.2015.03.003, 39(3): 157-166 (2015)

A Simulation Based Approach for Automated Feature Localization
Autor: Jan Malburg, Alexander Finder, Görschwin Fey
Zeitschrift: IEEE Trans. on CAD of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2014.2360462, Volume:33, Issue: 12, pp. 1886-1899 (2014)

Latency Analysis for Sequential Circuits
Autor: Alexander Finder, André Sülflow, Görschwin Fey
Zeitschrift: IEEE Trans. on CAD of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2013.2292501, Volume 33, Number 4, pp. 643-647 (2014)

Debug Automation for Logic Circuits Under Timing Variations
Autor: Mehdi Dehbashi, Görschwin Fey
Zeitschrift: IEEE Design & Test of Computers
Details: DOI 10.1109/MDAT.2013.2266393, Volume 30, Issue 6, pp. 60-69 (2013)

Automated Design Debugging in a Testbench-Based Verification Environment
Autor: Mehdi Dehbashi, André Sülflow, Görschwin Fey
Zeitschrift: Embedded Hardware Design - Microprocessors and Microsystems (MICPRO)
Details: DOI 10.1109/DSD.2011.67, Volume 37, Issue 2, pp. 206-217 (2013)

Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis
Autor: Daniel Große, Görschwin Fey, Rolf Drechsler
Zeitschrift: Electronic Communications of the EASST
Details: DOI 10.14279/tuj.eceasst.62.860, Volume 62, pp. 13 (2013)

Effective Robustness Analysis using Bounded Model Checking Techniques
Autor: Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2011.2120950, Volume 30, Number 8, pp. 1239-1252 (2011)

Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen
Autor: Görschwin Fey, Andre Sülflow, Stefan Frehse, Rolf Drechsler
Zeitschrift: it-Information Technology
Details: DOI: 10.1524/itit.2010.0594, Volume 52, Number 4, pp. 216-223 (2010)

MONSOON: SAT-based ATPG for Path Delay Faults Using Multiple-Valued Logics
Autor: Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Rolf Drechsler
Zeitschrift: Journal of Electronic Testing: Theory and Applications
Details: DOI: 10.1007/s10836-010-5146-y,Volume 26, Number 3, pp. 307-322, Pdf download (2010)

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
Autor: Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
Zeitschrift: it - information technology
Details: DOI: 10.1524/itit.2009.0529, Volume 51, Number 2, pp. 102-111, Pdf download (2009)

Advanced Verification by Automatic Property Generation
Autor: Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
Zeitschrift: IET Computers & Digital Techniques
Details: DOI: 10.1049/iet-cdt.2008.0110, Volume 3, Issue 4, pp. 338-353 (2009)

On Acceleration of SAT-based ATPG for Industrial Designs
Autor: Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2008.923107, Volume 27, Number 7, pp. 1329-1333 (2008)

On the Construction of Small Fully Testable Circuits with Low Depth
Autor: Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
Zeitschrift: Embedded Hardware Design - Microprocessors and Microsystems (MICPRO)
Details: DOI: 10.1016/j.micpro.2008.03.005, Special Issue, Volume 32, Issues 5-6, pp. 263-269 (2008)

Automatic Fault Localization for Property Checking
Autor: Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2008.923234, Volume 27, Number 6, pp. 1138-1149, June (2008)

Building Free Binary Decision Diagrams Using SAT Solvers
Autor: Robert Wille, Görschwin Fey, Rolf Drechsler
Zeitschrift: Facta Universitatis, Series: Electronics and Energetics
Details: DOI: 10.2298/FUEE0703381W, Volume 20, Number 3, pp. 381-394, (2007)

An Integrated Approach for Combining BDDs and SAT Provers
Autor: Rolf Drechsler, Görschwin Fey, Sebastian Kinder
Zeitschrift: Facta Universitatis, Series: Electronics and Energetics
Details: DOI: 10.2298/FUEE0703415D, Volume 20, Number 3, pp. 415-436 (2007)

Minimizing the Number of Paths in BDDs - Theory and Algorithm
Autor: Görschwin Fey, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2005.852662, Volume 25, Number 1, pp. 4-11 (2006)

Project-Based Learning in Student Teams in Computer Science Education
Autor: Andreas Breiter, Görschwin Fey, Rolf Drechsler
Zeitschrift: Facta Universitatis, Series: Electronics and Energetics
Details: DOI: 10.2298/FUEE0502165B, Volume 18, Number 2, pp. 165-180 (2005)

Synthesis of Fully Testable Circuits from BDDs
Autor: Rolf Drechsler, Junhao Shi, Görschwin Fey
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2004.823342, Volume 23, Number 3 (2004)

Augmenting All Solution SAT Solving for Circuits with Structural Information
Autor: Abraham Temesgen Tibebu, Görschwin Fey
Konferenz: 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Referenz: Budapest, Hungary, 2018

Mapping Abstract and Concrete Hardware Models for Design Understanding
Autor: Tino Flenker, Görschwin Fey
Konferenz: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Dresden, Germany, 2017

CEGAR-based EF Synthesis of Boolean Functions with an Application to Circuit Rectification
Autor: Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Konferenz: 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: pp. 251-256, Chiba/Tokyo, Japan, 2017

A Hybrid Algorithm to Conservatively Check the Robustness of Circuits
Autor: Niels Thole, Lorena Anghel, Görschwin Fey
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Referenz: Pittsburgh, USA, 2016

Designing Reliable Cyber-Physical Systems
Autor: Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon Ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Bremen, Germany, 2016

Equivalence Checking on ESL Utilizing A Priori Knowledge
Autor: Niels Thole, Heinz Riener, Görschwin Fey
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Bremen, Germany, 2016

WCET Overapproximation for Software in the Context of Cyber-Physical Systems
Autor: Niklas Krafczyk, Heinz Riener, Görschwin Fey
Konferenz: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Pdf | Referenz: Tallinn, Estonia, 2016

Exact Diagnosis Using Boolean Satisfiability
Autor: Heinz Riener, Görschwin Fey
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: Austin, USA, 2016

Exploiting Error Detection Latency for Parity-based Soft Error Detection
Autor: Gökçe Aydos, Görschwin Fey
Konferenz: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Košice, Slovakia, 2016

A Hybrid Algorithm to Conservatively Check the Robustness of Circuits
Autor: Niels Thole, Lorena Anghel, Görschwin Fey
Konferenz: IEEE European Test Symposium (ETS)
Pdf | Referenz: Amsterdam, Niederlande, 2016

Empirical Results on Parity-based Soft Error Detection with Software-based Retry
Autor: Gökçe Aydos, Görschwin Fey
Konferenz: IEEE Nordic Circuits and Systems Conference (NORCAS)
Pdf | Referenz: Oslo, Norway, 2015

Diagnostic Tests and Diagnosis for Delay Faults using Path Segmentation
Autor: Tino Flenker, André Sülflow, Görschwin Fey
Konferenz: 24th IEEE Asian Test Symposium (ATS)
Pdf | Referenz: Mumbai, India, 2015

Conservatively Analyzing Transient Faults
Autor: Niels Thole, Görschwin Fey, Alberto Garcia-Ortiz
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Montpelier, France, 2015

Equivalence Checking on System Level using A Priori Knowledge
Autor: Niels Thole, Heinz Riener, Görschwin Fey
Konferenz: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Pdf | Referenz: Belgrade, Serbia, 2015

metaSMT: A Unified Interface to SMT-LIB2
Autor: Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL'14)
Pdf | Referenz: pp. 1-6, Munich, Germany, 2014

Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques
Autor: Jan Malburg Niklas Krafczyk Görschwin Fey
Konferenz: IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 21-26, Warschau, Polen, 2014

SAT-Based Speedpath Debugging Using Waveforms
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 19th IEEE European Test Symposium (ETS)
Referenz: Paderborn, Germany, 2014

Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 22nd Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP)
Pdf | Referenz: Turin, Italy, 2014

Debug Automation for Synchronization Bugs at RTL
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 27th International Conference on VLSI Design
Pdf | Referenz: pp. 44-49, Mumbai, India, 2014

Analyse dynamischer Abhängigkeitsgraphen zum Debugging von Hardwaredesigns
Autor: Jan Malburg Alexander Finder Görschwin Fey
Konferenz: 7. ITG/GMM/GI-Fachtagung Zuverlässigkeit und Entwurf (ZuE2013)
Pdf | Referenz: pp. 59-66, Dresden, Germany, 2013

Debugging HDL Designs Based on Functional Equivalences with High-Level Specifications
Autor: Alexander Finder, Jan-Philipp Witte, Görschwin Fey
Konferenz: 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Karlovy Vary, Czech Republic, 2013

Efficient Automated Speedpath Debugging
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 48-53, Karlovy Vary, Czech Republic, 2013

Reliability Analysis Reloaded: How Will We Survive?
Autor: Robert Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda
Konferenz: Design, Automation and Test in Europe (DATE'13)
Pdf | Referenz: Grenoble, France, 2013

Tuning Dynamic Data Flow Analysis to Support Design Understanding
Autor: Jan Malburg, Alexander Finder, Görschwin Fey
Konferenz: Design, Automation and Test in Europe (DATE'13)
Pdf | Referenz: pp. 1179-1184, Grenoble, France, 2013

Improving Fault Tolerance Utilizing Hardware-Software-Co-Synthesis
Autor: Heinz Riener, Stefan Frehse, Görschwin Fey
Konferenz: Design, Automation and Test in Europe (DATE'13)
Pdf | Referenz: pp. 939-943, Grenoble, France, 2013

FoREnSiC - An Automatic Debugging Environment for C Programs
Autor: Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
Konferenz: Haifa Verification Conference (HVC)
Pdf | Referenz: Haifa, 2012

Automated Post-Silicon Debugging of Failing Speedpaths
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 21st IEEE Asian Test Symposium (ATS)
Pdf | Referenz: pp. 13-18, Niigata, Japan, 2012

Complete and Effective Robustness Checking by Means of Interpolation
Autor: Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav and Rolf Drechsler
Konferenz: Formal Methods in Computer-Aided Design (FMCAD'12)
Pdf | Referenz: Cambridge, UK, 2012, page 82-90

Hardware-Software-Co-Synthese zur Verbesserung der Fehlertoleranz
Autor: Stefan Frehse, Heinz Riener, Görschwin Fey
Konferenz: 6. GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZuE'12)
Pdf | Referenz: pp. 90-96, Bremen, Germany, 2012

Application of Timing Variation Modeling to Speedpath Diagnosis
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 4th International Conference on System, Software, SoC and Silicon Debug (S4D)
Pdf | Referenz: pp. 34-37, Vienna, Austria, 2012

Model-Based Diagnosis versus Error Explanation
Autor: Heinz Riener, Görschwin Fey
Konferenz: 10th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'12)
Pdf | Referenz: pp. 43-52, Arlington, Virginia, USA, 2012

On Modeling and Evaluation of Logic Circuits Under Timing Variations
Autor: Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Konferenz: 15th Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 431-436, Izmir, Turkey, 2012

Automated Debugging from Pre-Silicon to Post-Silicon
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 324-329, Tallinn, Estonia, 2012

Automated Feature Localization for Hardware Designs using Coverage Metrics
Autor: Jan Malburg, Alexander Finder, Görschwin Fey
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: pp. 941-946, San Francisco, 2012

Functional Analysis of Circuits Under Timing Variations
Autor: Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Konferenz: 17th IEEE European Test Symposium (ETS)
Pdf | Referenz: pp. 177, Annecy, France, 2012

Automated Post-Silicon Debugging of Design Bugs
Autor: Mehdi Dehbashi, Görschwin Fey
Konferenz: 3rd International Conference on System, Software, SoC and Silicon Debug (S4D)
Pdf | Referenz: pp. 67-71, Munich, Germany, 2011

Hochoptimierter Ablauf zur Robustheitsprüfung
Autor: Stefan Frehse, Finn Haedicke, Melanie Diepenbeck, Görschwin Fey, Rolf Drechsler
Konferenz: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)
Pdf | Referenz: Hamburg-Harburg, 2011

Automated Design Debugging in a Testbench-Based Verification Environment
Autor: Mehdi Dehbashi, André Sülflow, Görschwin Fey
Konferenz: 14th Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 479-486, Oulu, Finland, 2011
Best Paper Candidate

Orchestrated Multi-level Information Flow Analysis to Understand SoCs
Autor: Görschwin Fey
Konferenz: 48th Design Automation Conference (DAC)
Pdf | Referenz: San Diego, USA, 2011
Promotion video on YouTube

Latency Analysis for Sequential Circuits
Autor: Alexander Finder, André Sülflow, Görschwin Fey
Konferenz: 16th IEEE European Test Symposium (ETS)
Pdf | Referenz: pp. 129-134, Trondheim, 2011

Automatic Property Generation for the Formal Verification of Bus Bridges
Autor: Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Konferenz: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 417-422, Cottbus, 2011

Polynomial Datapath Optimization using Constraint Solving and Formal Modelling
Autor: Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler
Konferenz: IEEE/ACM International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: San Jose, 2010

Evaluating Debugging Algorithms from a Qualitative Perspective
Autor: Alexander Finder, Görschwin Fey
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: pp. 37-42, Southampton, 2010

Kompositionelle Formale Robustheitsprüfung
Autor: Stefan Frehse, Görschwin Fey
Konferenz: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)
Referenz: Wildbad Kreuth, 2010

RobuCheck: A Robustness Checker for Digital Circuits
Autor: Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 226-231, Lille, 2010

A Better-Than-Worst-Case Robustness Measure
Autor: Stefan Frehse, Görschwin Fey, Rolf Drechsler
Konferenz: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 78-83, Vienna, 2010

Using QBF to Increase Accuracy of SAT-Based Debugging
Autor: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS)
Pdf | Referenz: pp.641-644, Paris, 2010

Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen
Autor: Andre Sülflow, Stefan Frehse, Görschwin Fey, Rolf Drechsler
Konferenz: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)
Pdf | Referenz: pp. 45-52, Stuttgart, 2009

Deterministc Algorithms for ATPG under Leakage Constraints
Autor: Görschwin Fey
Konferenz: 18th Asian Test Symposium (ATS'09)
Pdf | Referenz: Taichung, 2009

SAT-Based ATPG Testing of Inter- and Intra-Gate Bridging Faults
Autor: Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada
Konferenz: European Conference on Circuit Theory and Design
Referenz: Antalya, 2009

Robustness Check for Multiple Faults using Formal Techniques
Autor: Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 85-90, Patras, 2009

Computing Bounds for Fault Tolerance using Formal Techniques
Autor: Görschwin Fey, Andre Sülflow, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: pp. 190-195, San Francisco, USA, 2009

WoLFram - A Word Level Framework for Formal Verification
Autor: Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
Konferenz: IEEE/IFIP International Symposium on Rapid System Prototyping (RSP)
Pdf | Referenz: pp. 11-17, Paris, 2009

Evaluation of Cardinality Constraints on SMT-based Debugging
Autor: Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler
Konferenz: 39th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 298-303, Naha, Okinawa, 2009

Increasing the Accuracy of SAT-based Debugging
Autor: Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1326-1332, Nice, 2009

Formaler Nachweis der Fehlertoleranz von Schaltkreisen
Autor: Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Konferenz: GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008)
Pdf | Referenz: pp. 75-82, Ingolstadt, 2008

Targeting Leakage Constraints during ATPG
Autor: Görschwin Fey, Sathoshi Komatsu, Yasuo Furukawa, Masahiro Fujita
Konferenz: Asian Test Symposium (ATS)
Pdf | Referenz: pp. 225-230, 2008

Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking
Autor: Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 542-549, Parma, 2008

Using Unsatisfiable Cores to Debug Multiple Design Errors
Autor: Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Konferenz: IEEE Great Lakes Symposium on VLSI (GLSVLSI'08)
Pdf | Referenz: pp. 77-82, Orlando, 2008

A Basis for Formal Robustness Checking
Autor: Görschwin Fey, Rolf Drechsler
Konferenz: International Symposium on Quality of Electronic Design (ISQED)
Pdf | Referenz: San Jose, 2008

Automatic Generation of Complex Properties for Hardware Designs
Autor: Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler Steffen Rülke
Konferenz: Design, Automation, and Test in Europe (DATE)
Pdf | Referenz: Munich, 2008

SWORD: A SAT like Prover Using Word Level Information
Autor: Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
Konferenz: IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC)
Pdf | Referenz: pp. 88-93, Atlanta, 2007

On the Construction of Small Fully Testable Circuits with Low Depth
Autor: Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools

Pdf | Referenz: Lübeck, 2007

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Autor: Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel
Konferenz: Fifth ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2007)
Pdf | Referenz: pp. 181-187, Nice, 2007

Experimental Studies on SAT-based ATPG for Gate Delay Faults
Autor: Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Konferenz: 37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Pdf | Referenz: Oslo, 2007

SAT-based ATPG for Path Delay Faults in Sequential Circuits
Autor: Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'07)
Pdf | Referenz: pp. 3671-3674, New Orleans, 2007

Reusing Learned Information in SAT-based ATPG
Autor: Görschwin Fey, Tim Warode, Rolf Drechsler
Konferenz: 20th International Conference on VLSI Design
Pdf | Referenz: Bangalore, 2007

Automatic Fault Localization for Property Checking
Autor: Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Konferenz: Haifa Verification Conference
Pdf | Referenz: Haifa, 2006

Efficiency of Multiple-Valued Encoding in SAT-based ATPG
Autor: Görschwin Fey, Junhao Shi, Rolf Drechsler
Konferenz: IEEE International Symposium on Multiple-Valued Logic (ISMVL '06)
Pdf | Referenz: Singapore, 2006

On the Relation Between Simulation-based and SAT-based Diagnosis
Autor: Görschwin Fey, Sean Safarpour, Andreas Veneris, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1139-1144, Munich, 2006

Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks
Autor: Görschwin Fey, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1225-1226, Munich, 2006

An Integrated Approach for Combining BDD and SAT Provers
Autor: Rolf Drechsler, Görschwin Fey, Sebastian Kinder
Konferenz: International Conference on VLSI Design
Pdf | Referenz: Hyderabad, 2006

Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits
Autor: Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
Konferenz: International Conference on ASIC (ASICON 2005)
Pdf | Referenz: pp. 967-970, Shanghai, 2005

PASSAT: Efficient SAT-based Test Pattern Generation
Autor: Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Konferenz: IEEE Annual Symposium on VLSI (ISVLSI '05)
Referenz: pp.212-217, Tampa, Florida, 2005

Controlling the Memory During Manipulation of Word-Level Decision Diagrams
Autor: Sebastian Kinder, Görschwin Fey, Rolf Drechsler
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL 2005)
Referenz: pp. 250-255, Calgary, 2005

Utilizing Don't Care States in SAT-based Bounded Sequential Problems
Autor: Sean Safarpour, Görschwin Fey, Andreas Veneris, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI'05)
Pdf | Referenz: Chicago, 2005

Bridging Fault Testability of BDD Circuits
Autor: Junhao Shi, Görschwin Fey, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005)
Pdf | Referenz: pp. 188-191 Shanghai, 2005

BDD Circuit Optimization for Path Delay Fault Testability
Autor: Görschwin Fey, Junhao Shi, Rolf Drechsler
Konferenz: Euromicro Symposium on Digital System Design (DSD'2004)
Referenz: pp. 168-172, Rennes, 2004

Algorithms for Taylor Expansion Diagrams
Autor: Görschwin Fey, Rolf Drechsler, Maciej Ciesielski
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL'2004)
Referenz: pp. 235-240, Toronto, 2004

Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
Autor: Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey
Konferenz: IEEE Design, Automation and Test in Europe
Pdf | Referenz: Vol. I, pp. 162-167, Paris, 2004

Improving Simulation-Based Verification by Means of Formal Methods
Autor: Görschwin Fey, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
Pdf | Referenz: pp. 640-643, Yokohama, 2004

BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
Autor: Junhao Shi, Görschwin Fey, Rolf Drechsler
Konferenz: Twelfth Asian Test Symposium (ATS03)
Referenz: pp. 290-293, Xi'an, 2003

Finding Good Counter-Examples to Aid Design Verification
Autor: Görschwin Fey, Rolf Drechsler
Konferenz: First ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2003)
Pdf | Referenz: pp. 51-52, Mont Saint-Michel, 2003

MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits
Autor: Rolf Drechsler, Junhao Shi and Görschwin Fey
Konferenz: IEEE Great Lakes Symposium on VLSI (GLSV'03)
Pdf | Referenz: p. 80-83, Washington, 2003

Modeling Multi-Valued Circuits in SystemC
Autor: Daniel Große, Görschwin Fey and Rolf Drechsler
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Pdf | Referenz: pp. 281-286, Tokyo, 2003

Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques
Autor: Görschwin Fey, Sebastian Kinder and Rolf Drechsler
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Referenz: pp. 361-366, Tokyo, 2003

SPIHT implemented in a XC4000 device
Autor: Jörg Ritter, Görschwin Fey and Paul Molitor
Konferenz: IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002)
Pdf | Referenz: volume I, pp. 239-242, Tulsa, 2002

Utilizing BDDs for disjoint SOP minimization
Autor: Görschwin Fey and Rolf Drechsler
Konferenz: IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002)
Referenz: volume II, pp. 306-309, Tulsa, 2002

Minimizing the Number of Paths in BDDs
Autor: Görschwin Fey and Rolf Drechsler
Konferenz: 15th Symposium on Integrated Circuits and System Design
Pdf | Referenz: pp. 359-364, Porto Alegre, 2002

Computing Exact Fault Candidates Incrementally
Autor: Heinz Riener, Görschwin Fey
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Referenz: Lausanne, Switzerland, 2017

Mining Latency Guarantees for RT-level Designs
Autor: Jan Malburg, Heinz Riener, Görschwin Fey
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Referenz: Lausanne, Switzerland, 2017

Counterexample-Guided EF Synthesis of Boolean Functions
Autor: Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Referenz: Bremen, Germany, 2017

Counterexample-Guided Diagnosis
Autor: Heinz Riener, Görschwin Fey
Workshop: International Verification and Security Workshop (IVSW'16)
Pdf | Referenz: Sant Feliu de Guixols, Catalunya, Spain, 2016

Generating good properties from a small number of use cases
Autor: Jan Malburg, Tino Flenker, Görschwin Fey
Workshop: International Verification and Security Workshop (IVSW'16)
Referenz: Sant Feliu de Guixols, Catalunya, Spain, 2016

SMT-Based CPS Parameter Synthesis
Autor: Heinz Riener, Robert Könighofer, Görschwin Fey, Roderick Bloem
Workshop: Applied Verification for Continuous and Hybrid Systems (ARCH@CPSWeek'16)
Pdf | Referenz: pp. 126-133, Vienna, Austria, 2016

Matching Abstract and Concrete Hardware Models for Design Understanding
Autor: Tino Flenker, Görschwin Fey
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDE)
Pdf | Referenz: Dresden, Germany, 2016

A Hybrid Algorithm to Conservatively Check the Robustness of Circuits
Autor: Niels Thole, Lorena Anghel, Görschwin Fey
Workshop: 28. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Referenz: Siegen, Germany, 2016

Parity-based Soft Error Detection with Software-based Retry vs. Triplication-based Soft Error Correction - An Analytical Comparison on a Flash-based FPGA Architecture
Autor: Gökçe Aydos, Görschwin Fey
Workshop: Workshop Fehlertolerante und energieeffiziente eingebettete Systeme: Methoden und Anwendungen
Pdf | Referenz: Cottbus, Germany, 2015

Path-Based Program Repair
Autor: Heinz Riener, Rüdiger Ehlers, Görschwin Fey
Workshop: 12th International Workshop on Formal Engineering approaches to Software Components and Architectures, Satellite event of ETAPS (FESCA'15)
Pdf | Referenz: pp. 22-32, London, United Kingdoms, 2015

Analyzing an SET at Gate Level using a Conservative Approach
Autor: Niels Thole, Görschwin Fey, Alberto Garcia-Ortiz
Workshop: GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Referenz: Bad Urach, 2015

Execution Tracing of C Code for Formal Analysis
Autor: Heinz Riener, Michael Kirkedal Thomsen, Görschwin Fey
Workshop: 18. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'15)
Referenz: Chemnitz, Germany, 2015

Towards analysing feature locations through testing traces with BUT4Reuse
Autor: Jabier Martinez, Jan Malburg, Tewfik Ziadi, Görschwin Fey
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDe)
Referenz: Grenoble, France, 2015

Mutation based Feature Localization
Autor: Jan Malburg, Emmanuelle Encrenaz-Tiphene, Görschwin Fey
Workshop: 15th International Workshop on Microprocessor Test and Verification
Pdf | Referenz: Austin, USA, 2014

Automatically Connecting Hardware Blocks via Light-Weight Matching Techniques (Extended Abstract)
Autor: Jan Malburg, Niklas Krafczyk, Görschwin Fey
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Pdf | Referenz: page 30, Dresden, Germany, 2014

Mutation based Feature Localization
Autor: Jan Malburg, Emmanuelle Encrenaz-Tiphene, Görschwin Fey
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Referenz: pp. 55-60, Dresden, Germany, 2014

Equivalence Checking on System Level using Stepwise Induction
Autor: Niels Thole, Görschwin Fey
Workshop: 17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Pdf | Referenz: Böblingen, Germany, 2014

A Logic for Cardinality Constraints
Autor: Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey
Workshop: 17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Referenz: Böblingen, Germany, 2014

Debug Automatisierung für logische Schaltungen unter Zeitvariation mittels Waveforms
Autor: Mehdi Dehbashi, Görschwin Fey
Workshop: 26. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Referenz: Bad Staffelstein, Germany, 2014

Yet a Better Error Explanation Algorithm
Autor: Heinz Riener, Görschwin Fey
Workshop: 16. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'13)
Pdf | Referenz: pp.193-194, Rostock, Germany, 2013

Towards Debug Automation for Timing Bugs at RTL
Autor: Mehdi Dehbashi, Görschwin Fey
Workshop: 25. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Referenz: Dresden, Germany, 2013

Verification of Embedded Systems Using Modeling and Implementation Languages
Autor: Mathias Soeken, Heinz Riener, Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop: International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs'12)
Pdf | Referenz: pp. 67-72, Tampere, Finland, 2012

Model-Based Diagnosis versus Error Explanation
Autor: Heinz Riener, Görschwin Fey
Workshop: International Workshop on System Level-Design of Automotive Electronics/Software (SLDAES'12) in conjunction with 49th Design Automation Conference (DAC'12)
Pdf | Referenz: San Francisco, USA, 2012

FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation
Autor: Heinz Riener, Görschwin Fey
Workshop: 19th International SPIN Workshop on Model Checking of Software (SPIN'12)
Pdf | Referenz: pp. 234-240, Oxford, United Kingdoms, 2012

Functional Analysis of Circuits Under Timing Variations
Autor: Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan
Workshop: edaWorkshop
Pdf | Referenz: Hannover, Germany, 2012

Automated Debugging from Pre-Silicon to Post-Silicon
Autor: Mehdi Dehbashi, Görschwin Fey
Workshop: 24. GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Referenz: Cottbus, Germany, 2012

Automated Feature Localization for Hardware Designs using Coverage Metrics
Autor: Jan Malburg, Alexander Finder, Görschwin Fey
Workshop: 15. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Referenz: pp. 85-96, Kaiserslautern, Germany, 2012

metaSMT: Focus on Your Application not on Solver Integration
Autor: Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler
Workshop: DIFTS'11: 1st International workshop on design and implementation of formal tools and systems
Pdf | Referenz: pp. 22-29, Austin, USA, 2011

Test Case Generation from Mutants using Model Checking Techniques
Autor: Heinz Riener, Roderick Bloem, Görschwin Fey
Workshop: IEEE Fourth International Conference on Software Testing, Verification and Validation Workshops (ICSTW'11)
Pdf | Referenz: pp. 388-397, Berlin, Germany, 2011

Towards Automatic Property Generation for the Formal Verification of Bus Bridges
Autor: Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Workshop: 14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz: Oldenburg, 2011

Latency Analysis for Sequential Circuits
Autor: Alexander Finder, André Sülflow, Görschwin Fey
Workshop: 23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2011
Pdf | Referenz: Passau, 2011

Towards Unifying Localization and Explanation for Automated Debugging
Autor: Görschwin Fey, André Sülflow, Rolf Drechsler
Workshop: 11th International Workshop on Microprocessor Test and Verification (MTV)
Pdf | Referenz: pp. 3-8, Austin, Texas, 2010

Evaluating Debugging Algorithms from a Qualitative Perspective
Autor: Alexander Finder, Görschwin Fey
Workshop: International Workshop on Boolean Problems
Pdf | Referenz: Freiberg, 2010

RobuCheck: A Robustness Checker for Digital Circuits
Autor: Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
Workshop: The First International Workshop on Dynamic Aspects in Dependability Models for Fault-Tolerant Systems (DYADEM-FTS)
Referenz: Valencia, 2010

A Better-Than-Worst-Case Robustness Measure
Autor: Stefan Frehse, Görschwin Fey, Rolf Drechsler
Workshop: 22. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2010
Pdf | Referenz: Paderborn, 2010

Using QBF to Increase the Accuracy of SAT-Based Debugging
Autor: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: International Workshop on Constraints in Formal Verification (CFV)
Pdf | Referenz: Grenoble, France, 2009

Robustness Check for Multiple Faults using Formal Techniques
Autor: Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
Workshop: Constraints in Formal Verification (CFV)
Pdf | Referenz: Grenoble, France, 2009

FormED: A Formal Environment for Debugging
Autor: Andre Sülflow, Robert Wille, Christian Genz, Görschwin Fey, Rolf Drechsler
Workshop: University Booth at Design, Automation and Test in Europe (DATE09)
Pdf | Referenz: Nizza, 2009

Algorithms for ATPG under Leakage Constraints
Autor: Görschwin Fey
Workshop: 21. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2009
Pdf | Referenz: Bremen, 2009

Increasing the Accuracy of SAT-based Debugging
Autor: Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Workshop: 12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Pdf | Referenz: pp. 47-56, Berlin, 2009

Computing Bounds for Fault Tolerance using Formal Techniques
Autor: Andre Sülflow, Görschwin Fey, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Workshop: IEEE Workshop on Design for Reliability and Variability (DRV)
Pdf | Referenz: Santa Clara, USA, 2008

Experimental Studies on SMT-based Debugging
Autor: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: IEEE 9th Workshop on RTL and High Level Testing (WRTLT'08)
Pdf | Referenz: pp. 93-98, Japan, 2008

Effiziente automatische Generierung von Assertions für industrielle Hardware-Designs
Autor: Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
Workshop: Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
Referenz: Dresden, 2008

Targeting Leakage Constraints during ATPG
Autor: Görschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita
Workshop: IEEE International Workshop on Silicon Debug and Diagnosis
Pdf | Referenz: San Diego, 2008

Debugging Design Errors by Using Unsatisfiable Cores
Autor: Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Workshop: 11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Pdf | Referenz: pp. 159-168, Freiburg, 2008

Formal Robustness Checking
Autor: Görschwin Fey, Rolf Drechsler
Workshop: Workshop on Constraints in Formal Verification, 2007
Pdf | Referenz: Bremen, 2007

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
Autor: Rolf Drechsler, Görschwin Fey, Jürgen Schlöffel
Workshop: edaWorkshop 2007
Referenz: Hannover, 2007

Building Free Binary Decision Diagrams Using SAT Solvers
Autor: Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop: 8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007)
Referenz: Oslo, 2007

SAT-based ATPG for Path Delay Fault in Industrial Circuits
Autor: Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel
Workshop: IEEE European Test Symposium (ETS), Informal Digest of Papers
Referenz: Freiburg, 2007

Estimating the Quality of AND-EXOR Optimization Results
Autor: Sebastian Kinder, Görschwin Fey and Rolf Drechsler
Workshop: 8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007)
Referenz: Oslo, 2007

Studies on Integrating SAT-based ATPG in an Industrial Environment
Autor: Daniel Tille, Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Workshop: 19. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
Pdf | Referenz: Erlangen, 2007

Instance Generation for SAT-based ATPG
Autor: Daniel Tille, Görschwin Fey, Rolf Drechsler
Workshop: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Pdf | Referenz: Krakau, 2007

Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse
Autor: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: pp. 101-110, Erlangen, 2007

Formal Verification on the Word Level using SAT-like Proof Techniques
Autor: Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Referenz: pp. 165-173, Erlangen, 2007

Efficiency of Multi-Valued Encoding in SAT-based ATPG
Autor: Görschwin Fey, Junhao Shi , Rolf Drechsler
Workshop: 18. Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“
Referenz: Titisee, 2006

SAT-Based Calculation of Source Code Coverage for BMC
Autor: Görschwin Fey, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: Dresden, 2006

SyCE: An Integrated Environment for System Design in SystemC
Autor: Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große
Workshop: 16th IEEE International Workshop on Rapid System Prototyping (RSP)
Pdf | Referenz: pp. 258-260, Montreal, 2005

PASSAT: Efficient SAT-based Test Pattern Generation
Autor: Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Workshop: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Referenz: Sopron, 2005

Efficient Hierarchical System Debugging for Property Checking
Autor: Görschwin Fey, Rolf Drechsler
Workshop: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Sopron, 2005

ParSyC: An Efficient SystemC Parser
Autor: Görschwin Fey, Daniel Große, Tim Cassens, Christian Genz, Tim Warode, Rolf Drechsler
Workshop: 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004)
Pdf | Referenz: pp. 148-154, Kanazawa, 2004

Design Understanding by Automatic Property Generation
Autor: Rolf Drechsler, Görschwin Fey
Workshop: 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004)
Pdf | Referenz: pp.274-281, Kanazawa, 2004

Experimental Studies on Test Pattern Generation for BDD Circuits
Autor: Junhao Shi, Görschwin Fey, Rolf Drechsler
Workshop: International Workshop on Boolean Problems (IWSBP)
Pdf | Referenz: pp. 71-76, Freiberg, 2004

Visualization of Diagnosis Results for Design Debugging
Autor: Görschwin Fey, Rolf Drechsler
Workshop: 13th International Workshop on Post-Binary ULSI Systems
Referenz: pp. 1-2, Toronto, 2004

Disjoint Sum of Product Minimization by Evolutionary Algorithms
Autor: Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler
Workshop: 1st European Workshop on Hardware Optimisation Techniques (EvoHOT)
Pdf | Referenz: Applications of Evolutionary Computing: EvoWorkshops 2004, LNCS 3005, p. 198-207, Coimbra, 2004

An Approach to Formal Verification of Reconfigurable Systems
Autor: Görschwin Fey, Rolf Drechsler, Muazzam Ali
Workshop: 1st IFIP WG 10.5 Workshop on "Frontiers in Automotive Electronics"
Referenz: Darmstadt, 2003

BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
Autor: Junhao Shi, Görschwin Fey and Rolf Drechsler
Workshop: IEEE European Test Workshop (ETW'03)
Pdf | Referenz: pp. 109-110, Maastricht, 2003, 2003

BDD Circuit Optimization for Path Delay Fault-Testability
Autor: Görschwin Fey, Junhao Shi, Rolf Drechsler
Workshop: 15th ITG/GMM/GI Workshop Test methods and Reliability of Circuits and Systems
Referenz: Timmendorfer Strand, 2003 , 2003

A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization
Autor: Görschwin Fey, Rolf Drechsler
Workshop: 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2003)
Referenz: pp. 54-60, Hiroshima , 2003

Cost-efficient Formal Block Verification for ASIC Design
Autor: K. Winkelmann, J. Trylus, D. Stoffel, Görschwin Fey
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: pp. 184-188, Bremen, 2003

Minimizing the Number of Paths in BDDs
Autor: Görschwin Fey, Rolf Derchsler
Workshop: International Workshop on Boolean Problems
Pdf | Referenz: pp. 149 - 156, Freiberg, 2002

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