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Arbeitsgruppe Rechnerarchitektur / AGRA | Informatik | FB03 | Universität Bremen

Dr. Daniel Große


Mein Forschungsinteresse liegt in der Formalen Verifikation von Schaltkreisen. Ziel der Formalen Verifikation ist es (anders als bei simulationsbasierten Verfahren, deren Grenzen z.B. durch den Pentium Bug aufgezeigt wurden) die Korrektheit von Schaltkreisen zu beweisen.
Vor allem untersuche ich genauer, wie Hochspracheninformationen im Verifikationsprozess Gewinn bringend eingesetzt werden können. Dabei spielt die Systembeschreibungssprache SystemC eine wichtige Rolle.

WiMi

Erweiterte virtuelle Prototypen für heterogene Systeme
Autor: Muhammad Hassan, Daniel Große , Rolf Drechsler
Verlag: Springer
Format: DOI: 10.1007/978-3-031-53152-1, gebunden (2024)

Formal Verification of Structurally Complex Multipliers
Autor: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Verlag: Springer
Format: DOI: 10.1007/978-3-031-24571-8 (2023)

Verbessertes virtuelles Prototyping
Mit RISC-V-Fallstudien
Autor: Vladimir Herdt, Daniel Große, Rolf Drechsler
Verlag: Springer
Format: DOI: 10.1007/978-3-031-18174-0, Hardcover, eBook (2023)

Recent Findings in Boolean Techniques
Autor: Rolf Drechsler, Daniel Große
Verlag: Springer
Format: DOI: 10.1007/978-3-030-68071-8, Gebunden und eBook (2021)

Enhanced Virtual Prototyping: Featuring RISC-V Case Studies
Autor: Vladimir Herdt, Daniel Große, Rolf Drechsler
Verlag: Springer
Format: DOI: 10.1007/978-3-030-54828-5, Hardcover (2020)

Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2018
Autor: Tom J. Kazmierski, Sebastian Steinhorst, Daniel Große (Eds.)
Verlag: Springer
Format: DOI: 10.1007/978-3-030-31585-6, Hardcover (2020)

Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017
Autor: Daniel Große, Sara Vinco, Hiren Patel (Hrsg.)
Verlag: Springer
Format: DOI: 10.1007/978-3-030-02215-0, Hardcover (2019)

Design Automation Techniques for Approximation Circuits
Autor: Arun Chandrasekharan, Daniel Große, Rolf Drechsler
Verlag: Springer
Format: gebunden (2018)

Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Autor: Daniel Große, Rolf Drechsler
Verlag: Shaker Verlag
Format: Gebunden (2017)

Quality-Driven SystemC Design
Autor: Daniel Große, Rolf Drechsler
Verlag: Springer
Format: Hardcover (2010)

EXplayN - Strategieoptimierung und Analyse ausgewählter Spielprobleme
Autor: Daniel Große, Andre Sülflow, Nicole Drechsler (Hrsg.)
Verlag: Shaker Verlag
Format: gebunden (2008)

SATRIX - Algorithmen für Boolesche Erfüllbarkeit
Autor: Daniel Große, Görschwin Fey, Rolf Drechsler (Hrsg.)
Verlag: Shaker Verlag
Format: Gebunden (2007)

Toward System-Level Assertions for Heterogeneous Systems
Autor: Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große
Buchtitel: Advanced Boolean Techniques | Herausgeber: Rolf Drechsler, Sebastian Huhn (Eds.)
Verlag: Springer
Format: DOI 10.1007/978-3-031-28916-3 (2023)

Automatic Design of Microfluidic Devices: An Overview of Platforms and Corresponding Design Tasks
Autor: Robert Wille, Bing Li, Rolf Drechsler, and Ulf Schlichtmann
Buchtitel: Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2018 | Herausgeber: Tom J. Kazmierski, Sebastian Steinhorst, Daniel Große
Verlag: Springer
Format: Hardcover (2020)

Extensible and Configurable RISC-V Based Virtual Prototype
Autor: Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
Buchtitel: Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2018 | Herausgeber: Tom J. Kazmierski, Sebastian Steinhorst, Daniel Große
Verlag: Springer
Format: Hardcover (2020)

Approximate Memory: Data Storage in the Context of Approximate Computing
Autor: Saman Fröhlich, Daniel Große, Rolf Drechsler
Buchtitel: Information Storage | Herausgeber: Cornelia S. Große, Rolf Drechsler
Verlag: Springer
Format: Hardcover (2019)

Approximate Hardware Generation Using Formal Techniques
Autor: Saman Fröhlich, Daniel Große, Rolf Drechsler
Buchtitel: Approximate Circuits: Methodologies and CAD | Herausgeber: Sherief Reda, Muhammad Shafique
Verlag: Springer
Format: Hardcover (2019)

Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Buchtitel: Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2017 | Herausgeber: Daniel Große, Sara Vinco, Hiren Patel
Verlag: Springer
Format: Hardcover (2019)

On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-Based Error Effect Simulation: A Case Study
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Buchtitel: Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2016 | Herausgeber: Franco Fummi, Robert Wille
Verlag: Springer
Format: Hardcover (2018)

Formal Verification of SystemC-based Cyber Components
Autor: Daniel Große, Hoang M. Le, Rolf Drechsler
Buchtitel: Industrial Internet of Things: Cybermanufacturing Systems | Herausgeber: Sabina Jeschke, Christian Brecher, Houbing Song, Danda B. Rawat
Verlag: Springer
Format: Hardcover (2016)

Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis
Autor: Daniel Große, Görschwin Fey, Rolf Drechsler
Buchtitel: Design and Test Technology for Dependable Systems-on-Chip | Herausgeber: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus
Verlag: Information Science Reference
Format: Hardcover (2011)

SMT-based Stimuli Generation in the SystemC Verification Library
Autor: Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
Buchtitel: Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009 | Herausgeber: Dominique Borrione
Verlag: Springer
Format: Hardcover (2010)

Debugging Contradictory Constraints in Constraint-based Random Simulation
Autor: Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Buchtitel: Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08 | Herausgeber: Martin Radetzki
Verlag: Springer
Format: gebunden (2009)

SWORD: A SAT like Prover Using Word Level Information
Autor: Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
Buchtitel: VLSI-SoC: Advanced Topics on Systems on a Chip: A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip | Herausgeber: Ricardo Reis, Vincent Mooney, Paul Hasler
Verlag: Springer
Format: Hardcover (2009)

Qualitätsorientierter Entwurfs- und Verifikationsablauf für digitale Systeme
Autor: Daniel Große
Buchtitel: Ausgezeichnete Informatikdissertationen 2008 | Herausgeber: Dorothea Wagner
Verlag: GI
Format: Paperback (2009)

Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques
Autor: Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
Buchtitel: Embedded Systems Specification and Design Languages: Selected contributions from FDL'07 | Herausgeber: Eugenio Villar
Verlag: Springer
Format: gebunden (2008)

Processor Verification
Autor: Daniel Große, Robert Siegmund, Rolf Drechsler
Buchtitel: Customizable Embedded Processors | Herausgeber: Paolo Ienne, Rainer Leupers
Verlag: Elsevier
Format: gebunden (2006)

System-level validation using formal techniques
Autor: Rolf Drechsler, Daniel Große
Buchtitel: System-on-Chip: Next Generation Electronics | Herausgeber: Bashir M. Al-Hashimi
Verlag: The IEE
Format: gebunden (2006)

RevSCA-2.0: SCA-based Formal Verification of Non-trivial Multipliers using Reverse Engineering and Local Vanishing Removal
Autor: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Details: DOI: 10.1109/TCAD.2021.3083682, Volume: 41 Issue: 5, pp.1573-1586 (2021)

Towards RISC-V CSR Compliance Testing
Autor: Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
Zeitschrift: IEEE Embedded Systems Letters (ESL)
Details: DOI: 10.1109/LES.2021.3077368, Volume: 13 Issue: 4, pp. 202-205 (2021)

Adaptive Simulation with Virtual Prototypes in an Open-Source RISC-V Evaluation Platform
Autor: Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
Zeitschrift: Journal of Systems Architecture - Embedded Software Design (JSA)
Details: DOI: 10.1016/j.sysarc.2021.102135, Volume 116 (2021)

ReCoFused partial reconfiguration for secure moving-target countermeasures on FPGAs
Autor: Buse Ustaoğlu, Kenneth Schmitz, Daniel Große, Rolf Drechsler
Zeitschrift: SN Applied Sciences | Springer Nature
Details: DOI 10.1007/s42452-020-3003-x, Article number: 1363 (2020) (2020)

On the Impact of the Synchronization Constraint and Interconnections in Quantum-dot Cellular Automata
Autor: Frank Sill Torres, Pedro A. Silva, Geraldo Fontes, Marcel Walter, José Augusto M. Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Robert Wille, Philipp Niemann, Daniel Große, Rolf Drechsler
Zeitschrift: Microprocessors and Microsystems (MICPRO)
Details: DOI: 10.1016/j.micpro.2020.103109, Volume 76, July 2020 (2020)

RISC-V based Virtual Prototype: An Extensible and Configurable Platform for the System-level
Autor: Vladimir Herdt, Daniel Große, Pascal Pieper, Rolf Drechsler
Zeitschrift: Journal of Systems Architecture - Embedded Software Design (JSA)
Details: DOI: 10.1016/j.sysarc.2020.101756, Volume 109 (2020)

Placement & Routing for Tile-based Field-coupled Nanocomputing Circuits is NP-complete
Autor: Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
Zeitschrift: Journal on Emerging Technologies in Computing Systems (JETC)
Details: DOI: 10.1145/3312661, Volume 15, Issue 3, Number 29 (2019)

Combining Sequentialization-based Verification of Multi-Threaded C Programs with Symbolic Partial Order Reduction
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Zeitschrift: International Journal of Software Tools for Technology Transfer (STTT)
Details: DOI: 10.1007/s10009-019-00507-5, 21(5):545-565 (2019)

Security Validation of VP-based SoCs Using Dynamic Information Flow Tracking
Autor: Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
Zeitschrift: it-Information Technology
Details: DOI: 10.1515/itit-2018-0027 (2019)

Verifying SystemC using Intermediate Verification Language and Stateful Symbolic Simulation
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)
Details: DOI: 10.1109/TCAD.2018.2846638, 38(7):1359-1372 (2018)

Behaviour Driven Development for Hardware Design
Autor: Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler
Zeitschrift: IPSJ Transactions on System LSI Design Methodology
Details: DOI: 10.2197/ipsjtsldm.11.29, Vol. 11, pp. 29-45, PDF Download (2018)

metaSMT: Focus On Your Application And Not On Solver Integration
Autor: Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey
Zeitschrift: International Journal of Software Tools for Technology Transfer
Details: DOI 10.1007/s10009-016-0426-1, 19(5):605-621 (2017)

Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis
Autor: Daniel Große, Görschwin Fey, Rolf Drechsler
Zeitschrift: Electronic Communications of the EASST
Details: DOI 10.14279/tuj.eceasst.62.860, Volume 62, pp. 13 (2013)

Automatic TLM Fault Localization for SystemC
Autor: Hoang M. Le, Daniel Große, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2012.2188800 , Volume 31, Number 8, pp. 1249-1262 (2012)

Debugging Reversible Circuits
Autor: Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Zeitschrift: INTEGRATION, the VLSI Journal
Details: DOI: 10.1016/j.vlsi.2010.08.002, Volume 44, Number 1, pp. 51-61, January (2011)

Towards Fully Automatic Synthesis of Embedded Software
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Zeitschrift: IEEE Embedded Systems Letters
Details: DOI: 10.1109/LES.2010.2049983, Volume 2, Number 3, pp. 53-57 (2010)

Exact Synthesis of Elementary Quantum Gate Circuits
Autor: Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Zeitschrift: Multiple-Valued Logic and Soft Computing
Details: DOI: 10.1109/ISMVL.2008.42, Volume 15, Number 4, pp. 283-300 (2009)

Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
Autor: Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2009.2017215, Volume 28, Number 5, pp. 703-715 (2009)

Analyzing Functional Coverage in Bounded Model Checking
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Zeitschrift: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2008.925790, Volume 27, Number 7, pp. 1305-1314 (2008)

BDD-based Verification of Scalable Designs
Autor: Daniel Große, Rolf Drechsler
Zeitschrift: Facta Universitatis, Series: Electronics and Energetics
Details: DOI: 10.2298/FUEE0703367G, Volume 20, Number 3, pp. 367-379 (2007)

System Level Validation Using Formal Techniques
Autor: Rolf Drechsler, Daniel Große
Zeitschrift: IEE Proceedings Computer & Digital Techniques, Special Issue on Embedded Microelectronic Systems: Status and Trends
Details: DOI: 10.1049/ip-cdt:20045073, Volume 152, Number 3, pp. 393-406 (2005)

Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC
Autor: Daniel Große, Rolf Drechsler
Zeitschrift: it - information technology
Details: DOI: 10.1524/itit.45.4.219.22731, Number 4, pp. 219-226 (2003)

Heuristic Learning based on Genetic Programming
Autor: Frank Schmiedle, Nicole Drechsler, Daniel Große and Rolf Drechsler
Zeitschrift: Genetic Programming and Evolvable Machines
Details: DOI: 10.1023/A:1020988925923, Volume 3, pp. 363-388 (2002)

A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS
Autor: Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große
Konferenz: Design and Verification Conference in Europe (DVCon Europe)
Pdf | Referenz: Munich, Germany, 2022

Divider Verification Using Symbolic Computer Algebra and Delayed Don’t Care Optimization
Autor: Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler
Konferenz: Formal Methods in Computer-Aided Design (FMCAD)
Pdf | Referenz: Trento, Italy, 2022

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
Autor: Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: Irvine, CA, USA, 2022

Formal Verification of Modular Multipliers using Symbolic Computer Algebra and Boolean Satisfiability
Autor: Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2022

Verifying SystemC TLM Peripherals using Modern C++ Symbolic Execution Tools
Autor: Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2022

Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level
Autor: Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Pdf | Referenz: Virtual Conference, Singapore, 2021

XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding
Autor: Lucas Klemmer, Saman Fröhlich, Rolf Drechsler, Daniel Große
Konferenz: IEEE International Symposium on Circuits & Systems (ISCAS)
Pdf | Referenz: Daegu, Korea, 2021

Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization
Autor: Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Grenoble, France, 2021

System Level verification of Phase-Locked Loop using Metamorphic Relations
Autor: Muhammad Hassan, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe Conference (DATE)
Pdf | Referenz: Grenoble, France, 2021

System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations
Autor: Muhammad Hassan, Daniel Große, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Tokyo, Japan, 2021

Mutation-based Compliance Testing for RISC-V
Autor: Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Tokyo, Japan, 2021

Clustering-Guided SMT(LRA) Learning
Autor: Tim Meywerk, Marcel Walter, Daniel Große, Rolf Drechsler
Konferenz: International Conference on integrated Formal Methods (iFM)
Pdf | Referenz: Lugano, Switzerland, 2020

Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime
Autor: Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
Konferenz: 38th IEEE International Conference on Computer Design (ICCD)
Pdf | Referenz: Hartford, USA, 2020

Verifying Safety Properties of Robotic Plans operating in Real-World Environments via Logic-based Environment Modeling
Autor: Tim Meywerk, Marcel Walter, Vladimir Herdt, Jan Kleinekathöfer, Daniel Große, Rolf Drechsler
Konferenz: 9th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation (ISoLA)
Pdf | Referenz: Rhodes, Greece, 2020

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
Autor: Vladimir Herdt, Daniel Große, Eyck Jentzsch, Rolf Drechsler
Konferenz: Forum on Specification & Design Languages (FDL)
Pdf | Referenz: Kiel, Germany, 2020
Best Paper Award

RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms
Autor: Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Automated Technology for Verification and Analysis (ATVA)
Pdf | Referenz: Hanoi, Vietnam, 2020

Towards Generation of a Programmable Power Management Unit at the Electronic System Level
Autor: David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
Konferenz: 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: Novi Sad, Serbia, 2020

Early Verification of ISA Extension Specifications Using Deep Reinforcement Learning
Autor: Niklas Bruns, Daniel Große, Rolf Drechsler
Konferenz: 30th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: Beijing, China, 2020

Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes
Autor: Vladimir Herdt, Daniel Große, Jonas Wloka, Tim Güneysu, Rolf Drechsler
Konferenz: 30th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: Beijing, China, 2020

Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side
Autor: Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2020

Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes
Autor: Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2020

Verification for Field-coupled Nanocomputing Circuits
Autor: Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: San Francisco, USA, 2020

ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks
Autor: Saman Fröhlich, Lucas Klemmer, Daniel Große, Rolf Drechsler
Konferenz: 50th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: Miyazaki, Japan, 2020

Towards Specification and Testing of RISC-V ISA Compliance
Autor: Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Grenoble, France, 2020

Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes
Autor: Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Grenoble, France, 2020

Towards Formal Verification of Optimized and Industrial Multipliers
Autor: Alireza Mahzoon, Daniel Große, Christoph Scholl, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Grenoble, France, 2020

Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems
Autor: Rolf Drechsler, Daniel Große
Konferenz: Asian Test Symposium (ATS)
Pdf | Referenz: Kolkata, India, 2019

Functional Coverage-Driven Characterization of RF Amplifiers
Autor: Muhammad Hassan, Daniel Große, Thilo Vörtler, Karsten Einwich and Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Southampton, United Kingdom, 2019
Best Paper Candidate

Systematic RISC-V based Firmware Design
Autor: Vladimir Herdt, Daniel Große, Rolf Drechsler, Christoph Gerum, Alexander Jung, Joscha-Joel Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Southampton, United Kingdom, 2019

SAT-Hard: A Learning-based Hardware SAT-Solver
Autor: Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Große and Rolf Drechsler
Konferenz: EUROMICRO Digital System Design Conference (DSD)
Pdf | Referenz: Kallithea - Chalkidiki, Greece, 2019

Towards Formal Verification of Plans for Cognition-enabled Autonomous Robotic Agents
Autor: Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: EUROMICRO Digital System Design Conference (DSD)
Pdf | Referenz: Kallithea - Chalkidiki, Greece, 2019

RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers
Autor: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: Las Vegas, USA, 2019

Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study
Autor: Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: Las Vegas, USA, 2019

Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-coupled Nanotechnologies
Autor: Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: Miami, Florida, USA, 2019

Automated Analysis of Virtual Prototypes at Electronic System Level
Autor: Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
Konferenz: 29th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: Washington, D.C., USA, 2019

(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-based Countermeasures on FPGAs
Autor: Kenneth Schmitz, Buse Ustaoglu, Daniel Große, Rolf Drechsler
Konferenz: International Symposium on Applied Reconfigurable Computing (ARC)
Pdf | Referenz: Darmstadt, Germany, 2019

One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing
Autor: Saman Fröhlich, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Florence, Italy, 2019

Verifying Instruction Set Simulators using Coverage-guided Fuzzing
Autor: Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Florence, Italy, 2019

Data Flow Testing for SystemC-AMS Timed Data Flow Models
Autor: Muhammad Hassan, Daniel Große, Hoang M. Le, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Florence, Italy, 2019

Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing
Autor: Hoang M. Le, Daniel Große, Niklas Bruns, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Florence, Italy, 2019

Scalable Design for Field-coupled Nanocomputing Circuits
Autor: Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Tokyo, Japan, 2019

Maximizing Power State Cross Coverage in Firmware-based Power Management
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: 24th Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Tokyo, Japan, 2019

PolyCleaner: Clean your Polynomials before Backward Rewriting to Verify Million-gate Multipliers
Autor: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: San Diego, USA, 2018
Best Paper Award

Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters
Autor: David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
Konferenz: IEEE Nordic Circuits and Systems Conference (NORCAS)
Pdf | Referenz: Tallinn, Estonia, 2018

Using Constraints for SystemC AMS Design and Verification
Autor: Thilo Vörtler, Karsten Einwich, Muhammad Hassan, Daniel Große
Konferenz: Design and Verification Conference and Exhibition Europe (DVCon Europe)
Pdf | Referenz: Munich, Germany, 2018
Best Paper Award

Extensible and Configurable RISC-V based Virtual Prototype
Autor: Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Munich, Germany, 2018

Towards Reversed Approximate Hardware Design
Autor: Saman Fröhlich, Daniel Große, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Prague, Czech Republic, 2018

Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata
Autor: Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Große, Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: pp. 649-656, Prague, Czech Republic, 2018

Synchronization of Clocked Field-Coupled Circuits
Autor: Frank Sill Torres, Marcel Walter, Robert Wille, Daniel Große, Rolf Drechsler
Konferenz: IEEE International Conference on Nanotechnology (Nano)
Pdf | Referenz: Cork, Ireland, 2018

Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers
Autor: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: pp. 351-356, Hong Kong SAR, China, 2018

Towards Dynamic Execution Environment for System Security Protection against Hardware Flaws
Autor: Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: pp. 557-562, Hong Kong SAR, China, 2018

Natural Language based Power Domain Partitioning
Autor: David Lemma, Daniel Große, Rolf Drechsler
Konferenz: 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 101-106, Budapest, Hungary, 2018

SAT-Lancer: A Hardware SAT-Solver for Self-Verification
Autor: Buse Ustaoglu, Sebastian Huhn, Daniel Große, Rolf Drechsler
Konferenz: 28th ACM Great Lakes Symposium on VLSI (GLVLSI)
Pdf | Referenz: pp. 479-482, Chicago, Illinois, USA, 2018
Received Best Poster Award

Resiliency Evaluation via Symbolic Fault Injection on Intermediate Code
Autor: Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 845-850, Dresden, Germany, 2018

Towards Fully Automated TLM-to-RTL Property Refinement
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1508-1511, Dresden, Germany, 2018

Testbench Qualification for SystemC-AMS Timed Data Flow Models
Autor: Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 857-860, Dresden, Germany, 2018

Approximate Hardware Generation using Symbolic Computer Algebra employing Gröbner Basis
Autor: Saman Fröhlich, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 889-892, Dresden, Germany, 2018

An Exact Method for Design Exploration of Quantum-dot Cellular Automata
Autor: Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 503-508, Dresden, Germany, 2018

Approximation-aware Testing for Approximate Circuits
Autor: Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler
Konferenz: 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: pp. 239 - 244, Jeju, Korea, 2018

Verifying Next Generation Electronic Systems
Autor: Rolf Drechsler, Daniel Große
Konferenz: International Conference on Infocom Technologies and Unmanned Systems (ICTUS)
Pdf | Referenz: pp. 6 - 10, Dubai, United Arab Emirates, 2017

Yise - A novel Framework for Boolean Networks using Y-Inverter Graphs
Autor: Arun Chandrasekharan, Daniel Große, Rolf Drechsler
Konferenz: 15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Referenz: pp. 114-117, Vienna, Austria, 2017

Towards Early Validation of Firmware-Based Power Management using Virtual Prototypes: A Constrained Random Approach
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: pp. 1-8, Verona, Italy, 2017
Best Paper Candidate

Semi-Formal Cycle-Accurate Temporal Execution Traces Reconstruction
Autor: Rehab Massoud, Jannis Stoppe, Daniel Große, Rolf Drechsler
Konferenz: 15th International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS)
Pdf | Referenz: pp. 335-351, Berlin, Germany, 2017

Early SoC Security Validation by VP-based Static Information Flow Analysis
Autor: Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: pp. 400-407, Irvine, USA, 2017

An Adaptive Prioritized ε-Preferred Evolutionary Algorithm for Approximate BDD Optimization
Autor: Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
Konferenz: Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Referenz: Berlin, Germany, 2017

ProACt: A Processor for High Performance On-demand Approximate Computing
Autor: Arun Chandrasekharan, Daniel Große, Rolf Drechsler
Konferenz: 27th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 463-466, Banff, Alberta, Canada, 2017

Error Bounded Exact BDD Minimization in Approximate Computing
Autor: Saman Fröhlich, Daniel Große, Rolf Drechsler
Konferenz: 47th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 254-259, Novi Sad, Serbia, 2017

Data Flow Testing for Virtual Prototypes
Autor: Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Lausanne, Switzerland, 2017

Trust is good, Control is better: Hardware-based Instruction-Replacement for Reliable Processor-IPs
Autor: Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler
Konferenz: 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: Chiba/Tokyo, Japan, 2017

Guided Lightweight Software Test Qualification for IP Integration using Virtual Prototypes
Autor: Daniel Große, Hoang M. Le, Muhammad Hassan, Rolf Drechsler
Konferenz: IEEE International Conference on Computer Design (ICCD)
Pdf | Referenz: Phoenix, USA, 2016

Equivalence Checking Using Gröbner Bases
Autor: Amr Sayed Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler
Konferenz: Formal Methods in Computer Aided Design (FMCAD)
Pdf | Referenz: Mountain View, USA, 2016

On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-based Error Effect Simulation - A Case Study
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Bremen, Germany, 2016
Best Paper Candidate

Approximation-aware Rewriting of AIGs for Error Tolerant Applications
Autor: Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: Austin, USA, 2016

Compiled Symbolic Simulation for SystemC
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: Austin, USA, 2016

ParCoSS: Efficient Parallelized Compiled Symbolic Simulation
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: International Conference on Computer Aided Verification (CAV)
Pdf | Referenz: Toronto, Canada, 2016

Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm
Autor: Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
Konferenz: Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Referenz: Denver, USA, 2016

Precise Error Determination of Approximated Components in Sequential Circuits with Model Checking
Autor: Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: Austin, USA, 2016

Quantitative Timing Analysis of UML Activity Diagrams Using Statistical Model Checking
Autor: Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 780-785, Dresden, Germany, 2016

Towards Formal Verification of Real-World SystemC TLM Peripheral Models - A Case Study
Autor: Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1160-1163, Dresden, Germany, 2016

Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction
Autor: Amr Sayed Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1048-1053, Dresden, Germany, 2016
Best Paper Candidate

BDD Minimization for Approximate Computing
Autor: Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: pp. 474-479, Macao, China, 2016

Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits
Autor: Amr Sayed Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015).
Pdf | Referenz: pp. 1-6, Montpellier, France, 2015.

Constraint-based Platform Variants Specification for Early System Verification
Autor: Andreas Burger, Alexander Viehl, Andreas Braun, Finn Haedicke, Daniel Große, Oliver Bringmann, Wolgang Rosenstiel
Konferenz: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Referenz: pp. 800-805, Singapore, 2014

Minimal Stimuli Generation in Simulation-based Verification
Autor: Shuo Yang, Robert Wille, Daniel Große and Rolf Drechsler
Konferenz: Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Santander, Spain, 2013

Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation
Autor: Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
Konferenz: Design Automation Conference (DAC)
Pdf | Referenz: pp. 116:1-6 Austin, Texas, 2013

Synchronized Debugging across Different Abstraction Levels in System Design
Autor: Rolf Drechsler, Daniel Große, Hoang M. Le, André Sülflow
Konferenz: embedded world Conference 2013
Pdf | Referenz: Nürnberg, 2013

Scalable Fault Localization for SystemC TLM Designs
Autor: Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE'13)
Pdf | Referenz: pp. 35-38, Grenoble, France, 2013

From Requirements and Scenarios to ESL Design in SystemC
Autor: Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: International Symposium on Electronic System Design (ISED)
Pdf | Referenz: pp. 183-187, Kolkata, WB, India, 2012

The System Verification Methodology for Advanced TLM Verification
Autor: Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, Volkan Esen
Konferenz: International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
Pdf | Referenz: pp. 313-322, Tampere, 2012

Completeness-Driven Development
Autor: Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille
Konferenz: International Conference on Graph Transformation
Pdf | Referenz: pp. 38-50, Bremen, 2012

CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC
Autor: Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler
Konferenz: International Symposium on System-on-Chip (SoC)
Pdf | Referenz: pp. 1-7, Tampere, 2012

Localizing Features of ESL Models for Design Understanding
Autor: Marc Michael, Daniel Große, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: Vienna, 2012

Coverage-driven Stimuli Generation
Autor: Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler
Konferenz: 15th Euromicro Conference on Digital System Design (DSD)
Pdf | Referenz: Izmir, Turkey, 2012

A Guiding Coverage Metric for Formal Verification
Autor: Finn Haedicke, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: Dresden, 2012

Analyzing Dependability Measures at the Electronic System Level
Autor: Marc Michael, Daniel Große, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: pp. 1-8, Oldenburg, 2011

TLM Protocol Compliance Checking at the Electronic System Level
Autor: Mohamed Bawadekji, Daniel Große, Rolf Drechsler
Konferenz: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Referenz: pp. 435-440, Cottbus, 2011

Designing a RISC CPU in Reversible Logic
Autor: Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Konferenz: 41st International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 170-175, Tuusula, 2011

Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction
Autor: Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 223-228, Lausanne, 2011

Proving Transaction and System-level Properties of Untimed SystemC TLM Designs
Autor: Daniel Große, Hoang M. Le, Rolf Drechsler
Konferenz: International Conference on Formal Methods and Models for Codesign (MEMOCODE)
Pdf | Referenz: pp. 113-122, Grenoble, 2010

SMT-based Stimuli Generation in the SystemC Verification Library
Autor: Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: pp. 1-6, Sophia Antipolis, 2009

WoLFram - A Word Level Framework for Formal Verification
Autor: Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
Konferenz: IEEE/IFIP International Symposium on Rapid System Prototyping (RSP)
Pdf | Referenz: pp. 11-17, Paris, 2009

Contradictory Antecedent Debugging in Bounded Model Checking
Autor: Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 173-176, Boston, 2009

Equivalence Checking of Reversible Circuits
Autor: Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Konferenz: 39th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Referenz: pp. 324-330, Naha, Okinawa, 2009

Property Analysis and Design Understanding
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1246-1249, Nice, 2009

Debugging of Toffoli Networks
Autor: Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1284-1289, Nice, 2009

Reversible Logic Synthesis with Output Permutation
Autor: Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Konferenz: 22nd International Conference on VLSI Design
Pdf | Referenz: pp. 189-194, New Delhi, 2009

Contradiction Analysis for Constraint-based Random Simulation
Autor: Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: pp. 130-135, Stuttgart, 2008

Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
Autor: Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Referenz: pp. 411-416, Montpellier, 2008

RevLib: An Online Resource for Reversible Functions and Reversible Circuits
Autor: Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler
Konferenz: 38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Pdf | Referenz: pp. 220-225, Dallas
RevLib is available at www.revlib.org, 2008

Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don’t Cares
Autor: Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Konferenz: 38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Pdf | Referenz: pp. 214-219, Dallas
Received IEEE Young Researcher Award, 2008

Quantified Synthesis of Reversible Logic
Autor: Robert Wille, Hoang M. Le, Gerhard W. Dueck, Daniel Große
Konferenz: Design, Automation, and Test in Europe (DATE)
Pdf | Referenz: pp. 1015-1020, Munich, 2008

Fast Exact Toffoli Network Synthesis of Reversible Logic
Autor: Robert Wille, Daniel Große
Konferenz: IEEE International Conference on Computer Aided Design (ICCAD)
Pdf | Referenz: pp. 60-64, San Jose, 2007

SWORD: A SAT like Prover Using Word Level Information
Autor: Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
Konferenz: IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC)
Pdf | Referenz: pp. 88-93, Atlanta, 2007

Measuring the Quality of a SystemC Testbench by using Code Coverage Technqiues
Autor: Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
Konferenz: Forum on specification & Design Languages (FDL)
Pdf | Referenz: pp. 146-151, Barcelona
Received Best Paper Award, 2007

Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Konferenz: IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Pdf | Referenz: pp. 165-170, Porto Alegre, 2007

Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
Autor: Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler
Konferenz: 37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Pdf | Referenz: Oslo, 2007

Improvements for Constraint Solving in the SystemC Verification Library
Autor: Daniel Große, Rüdiger Ebendt, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 493-496, Stresa, 2007

Exact SAT-based Toffoli Network Synthesis
Autor: Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 96-101, Stresa, 2007

Estimating Functional Coverage in Bounded Model Checking
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1176-1181, Nice, 2007

HW/SW Co-Verification of Embedded Systems using Bounded Model Checking
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Konferenz: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Referenz: pp. 43-48, Philadelphia, 2006

Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks
Autor: Görschwin Fey, Daniel Große, Rolf Drechsler
Konferenz: Design, Automation and Test in Europe (DATE)
Pdf | Referenz: pp. 1225-1226, Munich, 2006

Acceleration of SAT-based Iterative Property Checking
Autor: Daniel Große, Rolf Drechsler
Konferenz: Correct Hardware Design and Verification Methods (CHARME)
Pdf | Referenz: pp. 349-353, Saarbrücken, 2005

CheckSyC: An Efficient Property Checker for RTL SystemC Designs
Autor: Daniel Große, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'05)
Pdf | Referenz: pp. 4167-4170, Kobe, 2005

Automated Verification For Train Control Systems
Autor: Jan Peleska, Daniel Große, Anne E. Haxthausen, Rolf Drechsler
Konferenz: Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2004)
Pdf | Referenz: pp. 252-265, Braunschweig, 2004

Checkers for SystemC Designs
Autor: Daniel Große, Rolf Drechsler
Konferenz: Second ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2004)
Pdf | Referenz: pp. 171-178, San Diego, 2004

Efficient Automatic Visualization of SystemC Designs
Autor: Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst
Konferenz: Forum on Specification & Design Languages (FDL'03)
Pdf | Referenz: pp. 646-657, Frankfurt, 2003

Modeling Multi-Valued Circuits in SystemC
Autor: Daniel Große, Görschwin Fey and Rolf Drechsler
Konferenz: IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Pdf | Referenz: pp. 281-286, Tokyo, 2003

Formal Verification of LTL Formulas for SystemC Designs
Autor: Daniel Große, Rolf Drechsler
Konferenz: IEEE International Symposium on Circuits and Systems (ISCAS'03)
Pdf | Referenz: pp. V:245-V:248, Bangkok, 2003

Reachability Analysis for Formal Verification of SystemC
Autor: Rolf Drechsler and Daniel Große
Konferenz: Euromicro Symposium on Digital System Design (DSD'2002)
Pdf | Referenz: pp. 337-340, Dortmund, 2002

Towards Non-Intrusive SystemC Checkpointing for Digital Virtual Prototypes
Autor: Deepak Ravibabu, Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler and Daniel Große
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Referenz: Rostock, Germany, 2025

Divider Verification Using Symbolic Computer Algebra and Delayed Don’t Care Optimization
Autor: Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Referenz: Freiburg, Germany, 2023

GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools
Autor: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Referenz: München, Germany, 2021

VP-based DIFT for Embedded Binaries: A RISC-V Case Study
Autor: Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Referenz: München, Germany, 2021

Fuzz-Testing RISC-V Simulators
Autor: Vladimir Herdt, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Referenz: Stuttgart, Germany, 2020

Coverage-Directed Stimuli Generation for Characterization of RF Amplifiers
Autor: Muhammad Hassan, Daniel Große, Ahmad Asghar, Rolf Drechsler
Workshop: 32. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2020)
Pdf | Referenz: Stuttgart, Germany, 2020

GenMul: Generating architecturally complex multipliers to challenge formal verification tools
Autor: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Referenz: Lausanne, Switzerland, 2019

fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits
Autor: Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Referenz: Lausanne, Switzerland, 2019

Evaluation of Power State Cross Coverage in Firmware-Based Power Management
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: Embedded Software for Industrial IoTs (ESIIT)
Referenz: Dresden, Germany, 2018

Towards Automated Refinement of TLM Properties to RTL
Autor: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Referenz: Tübingen, Germany, 2018

Revisiting Symbolic Software-implemented Fault Injection
Autor: Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Workshop: 2nd International Workshop on Resiliency in Embedded Electronic Systems (REES)
Referenz: Lausanne, Switzerland, 2017

Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing
Autor: Saman Fröhlich, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Referenz: pp. 27-38, Bremen, Germany, 2017

Using Lightweight Containers in Hardware/Software Co-Design for Security
Autor: Daniel Große, Kenneth Schmitz, Rolf Drechsler
Workshop: Workshop on Computer-Aided Design and Implementation for Cryptography and Security (CADICS)
Referenz: Austin, USA, 2016

Symbolic Error Metric Determination for Approximate Computing
Autor: Arun Chandrasekharan, Daniel Große, Mathias Soeken, Rolf Drechsler
Workshop: 19. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'16)
Referenz: Freiburg, Germany, 2016

Towards Generating Test Suites with High Functional Coverage for Error Effect Simulation
Autor: Aljoscha Windhorst, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 1st International ESWEEK Workshop on Resiliency in Embedded Electronic Systems
Referenz: Amsterdam, The Netherlands, 2015

Funktionale Abdeckungsanalyse von C-Programmen
Autor: Aljoscha Windhorst, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Referenz: pp. 201-204, Böblingen, Germany, 2014

Towards Automatic Scenario Generation from Coverage Information
Autor: Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
Workshop: 8th International Workshop on Automation of Software Test (AST)
Pdf | Referenz: pp. 82-88, San Francisco, 2013

SystemC Verifikation mittels symbolischer Simulation einer Zwischensprache
Autor: Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
Workshop: edaWorkshop
Pdf | Referenz: pp. 53-58, Dresden, Germany, 2013

Behavior Driven Development for Circuit Design and Verification
Autor: Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
Workshop: IEEE International Workshop on High-Level Design Validation and Test (HLDVT)
Pdf | Referenz: pp. 9-16, Huntington Beach, USA, 2012

Design Understanding by Feature Localization on ESL
Autor: Marc Michael, Daniel Große, Rolf Drechsler
Workshop: 9. GMM/ITG/GI-Workshop Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS)
Referenz: pp. 19-24, Dresden, 2012

Compilation of Methodologies to Speed up the Verification Process at System Level
Autor: Stephan Radke, Steffen Rülke, Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Müller, Wolfgang Ecker, Volkan Esen, Simon Hufnagel, Nico Bannow, Helmut Brazdrum, Peter Janssen, Hoang M. Le, Daniel Große, Rolf Drechsler, Erhard Fehlauer, Gernot Koch, Andreas Burger, Oliver Bringmann, Wolfgang Rosenstiel, Finn Haedicke, Ralph Görgen, Jan-Hendrik Oetjens
Workshop: edaWorkshop
Referenz: pp. 57-62, Hannover, 2012

SystemC-based ESL Verification Flow Integrating Property Checking and Automatic Debugging
Autor: Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: DATE Friday Workshop: OSCI and Accellera Core Technologies for the Next Generation of System-Level Design
Referenz: Dresden, 2012

CRAVE: An Advanced Constrained Random Verification Environment for SystemC
Autor: Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 15. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Referenz: pp. 37-48, Kaiserslautern
Software and benchmarks available at www.systemc-verification.org, 2012

Towards Proving TLM Properties with Local Variables
Autor: Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 7th International Workshop on Constraints in Formal Verification (CFV)
Pdf | Referenz: San Jose, 2011

metaSMT: Focus on Your Application not on Solver Integration
Autor: Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler
Workshop: DIFTS'11: 1st International workshop on design and implementation of formal tools and systems
Pdf | Referenz: pp. 22-29, Austin, USA, 2011

Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines
Autor: Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler
Workshop: SORT 2011: 2nd IEEE Workshop on Self-Organizing Real-Time Systems
Referenz: pp. 181-188, Newport Beach, 2011

Protocol Compliance Checking of SystemC TLM Models
Autor: Mohamed Bawadekji, Daniel Große, Rolf Drechsler
Workshop: 8. GMM/ITG/GI-Workshop Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS)
Referenz: pp. 27-32, Bremen, 2011

Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction
Autor: Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Workshop: 14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz: pp. 269-278, Oldenburg, 2011

Designing a RISC CPU in Reversible Logic
Autor: Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Workshop: 14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz: pp. 249-258, Oldenburg, 2011

Automatic Fault Localization for SystemC TLM Designs
Autor: Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 11th International Workshop on Microprocessor Test and Verification (MTV)
Pdf | Referenz: pp. 35-40, Austin, Texas, 2010

Towards Analyzing Functional Coverage in SystemC TLM Property Checking
Autor: Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: IEEE International Workshop on High-Level Design Validation and Test (HLDVT)
Pdf | Referenz: pp. 67-74, Anaheim, 2010

Induction-based Formal Verification of SystemC TLM Designs
Autor: Daniel Große, Hoang M. Le, Rolf Drechsler
Workshop: 10th International Workshop on Microprocessor Test and Verification (MTV)
Referenz: pp. 101-106, Austin, Texas, 2009

Equivalence Checking of Reversible Circuits
Autor: Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Workshop: 12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz: Berlin, 2009

Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Workshop: 9th International Workshop on Microprocessor Test and Verification (MTV)
Pdf | Referenz: pp. 88-93, Austin, Texas, 2008

Reversible Logic Synthesis with Output Permutation
Autor: Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Workshop: International Workshop on Boolean Problems
Referenz: Freiberg, 2008

Contradiction Analysis for Constraint-based Random Simulation
Autor: Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Workshop: Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
Referenz: pp. 25-30, Dresden, 2008

Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking
Autor: Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Workshop: 11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Referenz: pp. 169-178, Freiburg, 2008

Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
Autor: Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler
Workshop: IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07)
Pdf | Referenz: pp. 31-36, Beijing, P.R.China, 2007

Formal Verification on the Word Level using SAT-like Proof Techniques
Autor: Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Referenz: pp. 165-173, Erlangen, 2007

Exact Toffoli Network Synthesis of Reversible Logic using Boolean Satisfiability
Autor: Daniel Große, Xiaobo Chen, Rolf Drechsler
Workshop: Fifth IEEE Dallas Circuits and Systems Workshop
Referenz: pp. 51-54, Dallas, 2006

Complete Formal Verification of Multi Core Embedded Systems using Bounded Model Checking
Autor: Ulrich Kühne, Daniel Große, Rolf Drechsler
Workshop: Fifth IEEE Dallas Circuits and Systems Workshop
Referenz: pp. 147-150, Dallas, 2006

HW/SW Co-Verification of a RISC CPU using Bounded Model Checking
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Workshop: 6th International Workshop on Microprocessor Test and Verification (MTV'05)
Pdf | Referenz: pp. 133-137, Austin, 2005

Bounded Model Checking of Tram Control Systems
Autor: Sebastian Kinder, Daniel Große, Jan Peleska, Rolf Drechsler
Workshop: TRain Workshop @ SEFM2005
Referenz: Koblenz, 2005

Formale Verifikation des Befehlssatzes eines in SystemC modellierten Mikroprozessors
Autor: Daniel Große, Ulrich Kühne, Rolf Drechsler
Workshop: Entwurfsmethoden für Nanometer VLSI Design
Pdf | Referenz: pp. 308-312, Bonn, 2005

Acceleration of SAT-based Iterative Property Checking
Autor: Daniel Große, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: München, 2005

Modellierung eines Mikroprozessors in SystemC
Autor: Daniel Große, Ulrich Kühne, Christian Genz, Frank Schmiedle, Bernd Becker, Rolf Drechsler, Paul Molitor
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: München, 2005

SyCE: An Integrated Environment for System Design in SystemC
Autor: Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große
Workshop: 16th IEEE International Workshop on Rapid System Prototyping (RSP)
Pdf | Referenz: pp. 258-260, Montreal, 2005

ParSyC: An Efficient SystemC Parser
Autor: Görschwin Fey, Daniel Große, Tim Cassens, Christian Genz, Tim Warode, Rolf Drechsler
Workshop: 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004)
Pdf | Referenz: pp. 148-154, Kanazawa, 2004

BDD-Based Verification of Scalable Designs
Autor: Daniel Große, Rolf Drechsler
Workshop: IEEE International High Level Design Validation and Test Workshop (HLDVT'2003)
Pdf | Referenz: pp. 123-128, San Francisco, 2003

Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen
Autor: Daniel Große, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Referenz: pp. 229-238, Bremen, 2003

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