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Group of Computer Architecture / AGRA | Computer Science | Faculty 03 | University of Bremen

Prof. Dr. Rolf Drechsler


I am the head of the group of computer architecture. The main focus of the group is the development and application of CAD tools in circuit design. The research areas range from system descriptions in SystemC over test and verification down to synthesis. For further information see www.rolfdrechsler.de

Head of the Group

+49 421 218-63932

MZH 4330

drechsler@uni-bremen.de

Formal and Practical Techniques for the Complex System Design Process using Virtual Prototypes
Author: Pascal Pieper, Rolf Drechsler
Pubisher: Springer
Format: gebunden (2024)

Design für Testbarkeit, Fehlersuche und Zuverlässigkeit
Maßnahmen der nächsten Generation unter Verwendung formaler Techniken

Author: Sebastian Huhn, Rolf Drechsler
Pubisher: Springer
Format: DOI: 10.1007/978-3-031-45319-9, Gebunden (2023)

Noerdman Comicbuch
Author: Rolf Drechsler, Jannis Stoppe
Pubisher: JR Blendermann Verlag
Format: ISBN: 978-3-910580-07-7, Taschenbuch (2023)

Automatisierte Analyse von virtuellen Prototypen auf der Ebene elektronischer Systeme | Design, Verständnis und Anwendungen
Author: Mehran Goli, Rolf Drechsler
Pubisher: Springer
Format: DOI: 10.1007/978-3-031-36997-1, Hardcover, eBook (2023)

Advanced Boolean Techniques
Author: Rolf Drechsler, Sebastian Huhn (Eds.)
Pubisher: Springer
Format: DOI 10.1007/978-3-031-28916-3 (2023)

In-Memory-Computing
Synthese und Optimierung

Author: Saeideh Shirinzadeh, Rolf Drechsler
Pubisher: Springer
Format: DOI: 10.1007/978-3-031-22879-7, Hardcover, eBook (2023)

Formal Verification of Structurally Complex Multipliers
Author: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Pubisher: Springer
Format: DOI: 10.1007/978-3-031-24571-8 (2023)

Verbessertes virtuelles Prototyping
Mit RISC-V-Fallstudien

Author: Vladimir Herdt, Daniel Große, Rolf Drechsler
Pubisher: Springer
Format: DOI: 10.1007/978-3-031-18174-0, Hardcover, eBook (2023)

Design Automation for Field-coupled Nanotechnologies
Author: Marcel Walter, Robert Wille, Frank Sill Torres, Rolf Drechsler
Pubisher: Springer
Format: DOI: 10.1007/978-3-030-89952-3 (2022)

Design for Testability, Debug and Reliability: Next Generation Measures Using Formal Techniques
Author: Sebastian Huhn, Rolf Drechsler
Pubisher: Springer
Format: DOI: 10.1007/978-3-030-69209-4, Gebunden und eBook (2021)

Recent Findings in Boolean Techniques
Author: Rolf Drechsler, Daniel Große
Pubisher: Springer
Format: DOI: 10.1007/978-3-030-68071-8, Gebunden und eBook (2021)

Natural Language Processing for Electronic Design Automation
Author: Mathias Soeken, Rolf Drechsler (Eds.)
Pubisher: Springer
Format: DOI: 10.1007/978-3-030-52273-5, Hardcover (2020)

Noch analog oder lebst Du schon?
Mit Nœrdman durch die Welt von heute... und morgen

Author: Rolf Drechsler, Jannis Stoppe
Pubisher: Springer
Format: DOI: 10.1007/978-3-658-32413-1, Softcover, eBook (2021)

Enhanced Virtual Prototyping: Featuring RISC-V Case Studies
Author: Vladimir Herdt, Daniel Große, Rolf Drechsler
Pubisher: Springer
Format: DOI: 10.1007/978-3-030-54828-5, Hardcover (2020)

Automated Analysis of Virtual Prototypes at the Electronic System Level – Design Understanding and Applications
Author: Mehran Goli, Rolf Drechsler
Pubisher: Springer
Format: Hardcover (DOI: 10.1007/978-3-030-44282-8, 2020)

Advanced Boolean Techniques
Author: Rolf Drechsler, Mathias Soeken (Hrsg.)
Pubisher: Springer International Publishing
Format: DOI: 10.1007/978-3-031-28916-3, Hardcover (2020)

In-Memory Computing - Synthesis and Optimization
Author: Saeideh Shirinzadeh, Rolf Drechsler
Pubisher: Springer
Format: DOI: 10.1007/978-3-030-18026-3, Hardcover (2020)

Information Storage - A Multidisciplinary Perspective
Author: Cornelia S. Große, Rolf Drechsler (Eds.)
Pubisher: Springer
Format: DOI: 10.1007/978-3-030-19262-4, Hardcover (2019)

Design Automation Techniques for Approximation Circuits
Author: Arun Chandrasekharan, Daniel Große, Rolf Drechsler
Pubisher: Springer
Format: gebunden (2018)

Exact Design of Digital Microfluidic Biochips
Author: Oliver Keszöcze, Robert Wille, Rolf Drechsler
Pubisher: Springer
Format: Gebunden (2018)

Advanced Logic Synthesis
Author: André Inácio Reis, Rolf Drechsler
Pubisher: Springer
Format: eBook (2017)

Formal System Verification State-of the-Art and Future Trends
Author: Rolf Drechsler
Pubisher: Springer Verlag
Format: Hardcover, eBook (2017)

Computer: Wie funktionieren Smartphone, Tablet & Co.?
Author: Rolf Drechsler, Andrea Fink, Jannis Stoppe
Pubisher: Springer
Format: Taschenbuch (2017)

Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Author: Daniel Große, Rolf Drechsler
Pubisher: Shaker Verlag
Format: Gebunden (2017)

Automatic Methods for the Refinement of System Models
Author: Julia Seiter, Robert Wille, Rolf Drechsler
Pubisher: Springer International Publishing
Format: Taschenbuch (2016)

Reversible and Quantum Circuits
Author: Nabila Abdessaied, Rolf Drechsler
Pubisher: Springer
Format: eBook, Hardcover (2016)

Languages, Design Methods, and Tools for Electronic System Design
Author: Rolf Drechsler, Robert Wille (Hrsg.)
Pubisher: Springer International Publishing (Verlag)
Format: Buch | Hardcover (2016)

Synthese- und Optimierungsverfahren für zukünftige Computerparadigmen
Author: Robert Wille, Oliver Keszöcze, Rolf Drechsler (Hrsg.)
Pubisher: Shaker Verlag
Format: gebunden (2015)

Formal Modeling and Verification of Cyber-Physical Systems
Author: Rolf Drechsler, Ulrich Kühne (Hrsg.)
Pubisher: Springer
Format: eBook, Softcover (2015)

Formal Specification Level
Author: Mathias Soeken, Rolf Drechsler
Pubisher: Springer
Format: eBook, Hardcover (2014)

Aspekte der Technischen Informatik
Author: Rolf Drechsler (Hrsg.)
Pubisher: MV-Wissenschaft
Format: Softcover (2014)

Auf dem Weg zum Quantencomputer - Entwurf reversibler Logik
Author: Rolf Drechsler, Mathias Soeken, Robert Wille (Hrsg.)
Pubisher: Shaker Verlag
Format: gebunden (2012)

High Quality Test Pattern Generation and Boolean Satisfiability
Author: Stephan Eggersglüß, Rolf Drechsler
Pubisher: Springer
Format: Hardcover (2012)

Applications of Evolutionary Computation
Author: Cecilia Di Chio, Anthony Brabazon, Gianni A. Di Caro, Rolf Drechsler, Muddassar Farooq, Jörn Grahl, Gary Greenfield, Christian Prins, Juan Romero und Giovanni Squillero, et al.
Pubisher: Springer
Format: Gebunden (2011)

Towards a Design Flow for Reversible Logic
Author: Robert Wille, Rolf Drechsler
Pubisher: Springer
Format: Gebunden (2010)

Debugging at the Electronic System Level
Author: Frank Rogin, Rolf Drechsler
Pubisher: Springer
Format: Gebunden (2010)

Quality-Driven SystemC Design
Author: Daniel Große, Rolf Drechsler
Pubisher: Springer
Format: Hardcover (2010)

Test Pattern Generation using Boolean Proof Engines
Author: Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille
Pubisher: Springer
Format: Hardcover (2009)

Robustness and Usability in Modern Design Flows
Author: Görschwin Fey, Rolf Drechsler
Pubisher: Springer
Format: Hardcover (2008)

Applications of Evolutionary Computing
Author: M. Giacobini, A. Brabazon, S. Cagnoni, G. A. DiCaro, Rolf Drechsler, A. Ekart, A. I. Esparcia-Alcazar, M. Farooq, A. Fink, J. McCormack, M. O'Neill, J. Romero, F. Rothlauf, G. Squillero, S. Uyar, S. Yang
Pubisher: Springer
Format: Gebunden (2008)

Applications of Evolutionary Computing
Author: M. Giacobini, A. Brabazon, S. Cagoni, G.A. Di Caro, Rolf Drechsler, M. Farooq, A. Fink, E. Lutton, P. Machado, S. Minner, M. O'Neill, J. Romero, F. Rothlauf, G. Squillero, H. Takagi, A.S. Uyar, S. Yang
Pubisher: Springer
Format: Gebunden (2007)

SATRIX - Algorithmen für Boolesche Erfüllbarkeit
Author: Daniel Große, Görschwin Fey, Rolf Drechsler (Hrsg.)
Pubisher: Shaker Verlag
Format: Gebunden (2007)

Applications of Evolutionary Computing
Author: F. Rothlauf, J. Branke, S. Cagnoni, E. Costa, C. Cotta, Rolf Drechsler, E. Lutton, P. Machado, J.H. Moore, J. Romero, G.D. Smith, G. Squillero, H. Takagi (Eds.)
Pubisher: Springer
Format: Gebunden (2006)

Advanced BDD Optimization
Author: Rüdiger Ebendt, Görschwin Fey, Rolf Drechsler
Pubisher: Springer Verlag
Format: Hardcover (2005)

Technische Informatik - Eine Einführung
Author: Bernd Becker, Rolf Drechsler, Paul Molitor
Pubisher: Pearson Studium
Format: Gebunden (2005)

Applications of Evolutionary Computing
Author: Franz Rothlauf, Jürgen Branke, Stefano Cagnoni, David W. Corne, Rolf Drechsler, Yaochu Jin, Penousal Machado, Elena Marchiori, Juan Romero, George D. Smith, Giovanni Squillero
Pubisher: Springer
Format: Gebunden (2005)

FunTaskIC - Eine integrierte Entwurfsumgebung für SystemC
Author: Görschwin Fey, Rolf Drechsler (Hrsg.)
Pubisher: Shaker Verlag
Format: Gebunden (2005)

Applications of Evolutionary Computing
Author: G.R. Raidl, S. Cagnoni, J. Branke, D.W. Corne, Rolf Drechsler, Y. Jin, C.G. Johnson, P. Machado, E. Marchiori,F. Rothlauf, G.D. Smith, G. Squillero
Pubisher: Springer
Format: Gebunden (2004)

Advanced Formal Verification
Author: Rolf Drechsler
Pubisher: Kluwer Academic Publishers
Format: Gebunden (2004)

Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Author: Rolf Drechsler
Pubisher: Shaker Verlag
Format: Gebunden (2003)

Evolutionary Algorithms for Embedded System Design
Author: Rolf Drechsler, Nicole Drechsler
Pubisher: Kluwer Academic Publishers
Format: Gebunden (2002)

Software-Engineering und Hardware-Design
Author: Axel Sikora, Rolf Drechsler
Pubisher: Carl Hanser Verlag
Format: Gebunden (2002)

Towards One-Pass Synthesis
Author: Rolf Drechsler, Wolfgang Günther
Pubisher: Kluwer Academic Publishers
Format: Hardcover (2002)

Spectral Techniques in VLSI CAD
Author: Mitchell A. Thornton, Rolf Drechsler, D. Michel Miller
Pubisher: Kluwer Academic Publishers
Format: Hardcover (2001)

Formal Verification of Circuits
Author: Rolf Drechsler
Pubisher: Kluwer Academic Publishers
Format: Hardcover (2000)

Evolutionary Algorithms for VLSI CAD
Author: Rolf Drechsler
Pubisher: Kluwer Academic Publishers
Format: Hardcover (1998)

Binary Decision Diagrams: Theory and Implementations
Author: Rolf Drechsler, Bernd Becker
Pubisher: Kluwer Academic Publisher
Format: Hardcover (1998)

Graphenbasierte Funktionsdarstellung
Author: Rolf Drechsler, Bernd Becker
Pubisher: B.G. Teubner
Format: Gebunden (1998)

Functional Decision Diagrams und ihre Anwendung
Author: Rolf Drechsler
Pubisher: Modell Verlag
Format: Gebunden (1996)

Modulares und rekonfigurierbares Systemdesign für Unterwasserfahrzeuge
Author: Marc Hildebrandt, Kenneth Schmitz, Rolf Drechsler
Booktitle: KI-Technologie für Unterwasserroboter | Editor: Frank Kirchner, Sirko Straube, Daniel Kühn, Nina Hoyer
Publisher: Springer
Format: DOI:10.1007/978-3-031-42369-7 (2023)

Verifizierung für autonome Unterwassersysteme
Author: Christoph Lüth, Nicole Megow, Rolf Drechsler, Udo Frese
Booktitle: KI-Technologie für Unterwasserroboter | Editor: Frank Kirchner, Sirko Straube, Daniel Kühn, Nina Hoyer
Publisher: Springer
Format: DOI:10.1007/978-3-031-42369-7 (2023)

AQuCiDe: Architecture Aware Decomposition of Quantum Circuits
Author: Soumya Sengupta, Abhoy Kole, Kamalika Datta, Indranil Sengupta, Rolf Drechsler
Booktitle: Quantum Computing: Circuits, Systems, Automation and Applications | Editor: Himanshu Thapliyal, Travis Humble
Publisher: Springer
Format: DOI:10.1007/978-3-031-37966-6 (2024)

Polynomial Formal Verification of Carry Look-Ahead Adders
Author: Alireza Mahzoon, Rolf Drechsler
Booktitle: Advances in the Boolean Domain | Editor: Bernd Steinbach
Publisher: Cambridge Scholars Publishing
Format: ISBN: 1-5275-8872-6 (2023)

Start Small But Dream Big: On Choosing a Static Variable Order for Multiplier BDDs
Author: Khushboo Qayyum, Alireza Mahzoon, Rolf Drechsler
Booktitle: Advanced Boolean Techniques | Editor: Rolf Drechsler, Sebastian Huhn (Eds.)
Publisher: Springer
Format: DOI 10.1007/978-3-031-28916-3 (2023)

SAT-Based Key Determination Attack for Improving the Quality Assessment of Logic Locking Mechanisms
Author: Marcel Merten, Mohammed E. Djeridane, Sebastian Huhn, Rolf Drechsler
Booktitle: Advanced Boolean Techniques | Editor: Rolf Drechsler, Sebastian Huhn (Eds.)
Publisher: Springer
Format: DOI 10.1007/978-3-031-28916-3 (2023)

Toward System-Level Assertions for Heterogeneous Systems
Author: Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große
Booktitle: Advanced Boolean Techniques | Editor: Rolf Drechsler, Sebastian Huhn (Eds.)
Publisher: Springer
Format: DOI 10.1007/978-3-031-28916-3 (2023)

Empowering the Design of Reversible and Quantum Logic with Decision Diagrams
Author: Robert Wille, Philipp Niemann, Alwin Zulehner and Rolf Drechsler
Booktitle: Emerging Computing: From Devices to Systems | Editor: Mohamed M. Sabry Aly, Anupam Chattopadhyay
Publisher: Springer
Format: Hardcover, eBook (2022)

Das Bremen Ambient Assisted Living Lab und darüber hinaus – Intelligente Umgebungen, smarte Services und Künstliche Intelligenz in der Medizin für den Menschen
Author: Serge Autexier, Christoph Lüth, Rolf Drechsler
Booktitle: Künstliche Intelligenz im Gesundheitswesen | Editor: Mario A. Pfannstiel
Publisher: Springer
Format: Hardcover (2022)

Intelligent Umgeben: Ausgewählte Einblicke in 10 Jahre Bremen Ambient Assisted Living Lab
Author: Serge Autexier, Rolf Drechsler
Booktitle: Smart City – Made in Germany | Editor: Etezadzadeh, Chirine
Publisher: Springer
Format: gebunden (2020)

Automatic Design of Microfluidic Devices: An Overview of Platforms and Corresponding Design Tasks
Author: Robert Wille, Bing Li, Rolf Drechsler, and Ulf Schlichtmann
Booktitle: Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2018 | Editor: Tom J. Kazmierski, Sebastian Steinhorst, Daniel Große
Publisher: Springer
Format: Hardcover (2020)

Extensible and Configurable RISC-V Based Virtual Prototype
Author: Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
Booktitle: Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2018 | Editor: Tom J. Kazmierski, Sebastian Steinhorst, Daniel Große
Publisher: Springer
Format: Hardcover (2020)

Approximate Memory: Data Storage in the Context of Approximate Computing
Author: Saman Fröhlich, Daniel Große, Rolf Drechsler
Booktitle: Information Storage | Editor: Cornelia S. Große, Rolf Drechsler
Publisher: Springer
Format: Hardcover (2019)

Modular and Reconfigurable System Design for Underwater Vehicles
Author: Marc Hildebrandt, Kenneth Schmitz, Rolf Drechsler
Booktitle: AI Technology for Underwater Robots | Editor: Frank Kirchner, Sirko Straube, Daniel Kühn, Nina Hoyer
Publisher: Springer
Format: DOI:10.1007/978-3-030-30683-0 (2019)

Verification for Autonomous Underwater Systems
Author: Christoph Lüth, Nicole Megow, Rolf Drechsler, Udo Frese
Booktitle: AI Technology for Underwater Robots | Editor: Frank Kirchner, Sirko Straube, Daniel Kühn, Nina Hoyer
Publisher: Springer
Format: DOI:10.1007/978-3-030-30683-0 (2019)

An Efficient Nearest Neighbor Design for 2D Quantum Circuits
Author: A. Bhattacharjee, C. Bandyopadhyay, B. Mondal, Robert Wille, Rolf Drechsler, H. Rahaman
Booktitle: Design and Testing of Reversible Logic | Editor: Ashutosh Kumar SinghMasahiro FujitaAnand Mohan
Publisher: Springer
Format: gebunden (2020)

Assistenzsysteme der Zukunft – Nutzen und Potenzial künstlicher Intelligenz
Author: Rolf Drechsler, Christoph Lüth
Booktitle: Brauchen wir eine neue Staatskunst? | Editor: Henning Lühr
Publisher: Kellner Verlag
Format: Gebunden, Softcover (2019)

In-Memory Computing: The Integration of Storage and Processing
Author: Saeideh Shirinzadeh, Rolf Drechsler
Booktitle: Information Storage A Multidisciplinary Perspective | Editor: Cornelia S. Große, Rolf Drechsler
Publisher: Springer
Format: Hardcover (2019)

Approximate Hardware Generation Using Formal Techniques
Author: Saman Fröhlich, Daniel Große, Rolf Drechsler
Booktitle: Approximate Circuits: Methodologies and CAD | Editor: Sherief Reda, Muhammad Shafique
Publisher: Springer
Format: Hardcover (2019)

Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Booktitle: Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2017 | Editor: Daniel Große, Sara Vinco, Hiren Patel
Publisher: Springer
Format: Hardcover (2019)

Computational Complexity of Error Metrics in Approximate Computing
Author: Oliver Keszöcze, Mathias Soeken, Rolf Drechsler
Booktitle: Further Improvements in the Boolean Domain | Editor: Bernd Steinbach
Publisher: Cambridge Scholars Publishing
Format: Paperback (2018)

On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-Based Error Effect Simulation: A Case Study
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Booktitle: Languages, Design Methods, and Tools for Electronic System Design: Selected Contributions from FDL 2016 | Editor: Franco Fummi, Robert Wille
Publisher: Springer
Format: Hardcover (2018)

Logic Synthesis for Majority based In-Memory Computing
Author: Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
Booktitle: Advances in Memristors, Memristive Devices and Systems | Editor: Sundarapandian Vaidyanathan, Christos Volos
Publisher: Springer
Format: Hardcover (2017)

Formal Verification of SystemC-based Cyber Components
Author: Daniel Große, Hoang M. Le, Rolf Drechsler
Booktitle: Industrial Internet of Things: Cybermanufacturing Systems | Editor: Sabina Jeschke, Christian Brecher, Houbing Song, Danda B. Rawat
Publisher: Springer
Format: Hardcover (2016)

A framework for reversible circuit complexity
Author: Mathias Soeken, Nabila Abdessaied, Rolf Drechsler
Booktitle: Problems and New Solutions in the Boolean Domain | Editor: Bernd Steinbach
Publisher: Cambridge Scholars Publishing
Format: Paperback (2016)

Formal Specification Level
Author: Rolf Drechsler, Mathias Soeken, Robert Wille
Booktitle: Models, Methods, and Tools for Complex Chip Design: Selected Contributions from FDL 2012 | Editor: Jan Haase
Publisher: Springer
Format: Hardcover (2014)

SyReC: A Programming Language for Synthesis of Reversible Circuits
Author: Robert Wille, Sebastian Offermann, Rolf Drechsler
Booktitle: System Specification and Design Languages: Selected Contributions from FDL 2010 | Editor: Tom J. Kazmierski, Adam Morawiec
Publisher: Springer
Format: Hardcover (2012)

Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis
Author: Daniel Große, Görschwin Fey, Rolf Drechsler
Booktitle: Design and Test Technology for Dependable Systems-on-Chip | Editor: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus
Publisher: Information Science Reference
Format: Hardcover (2011)

SMT-based Stimuli Generation in the SystemC Verification Library
Author: Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
Booktitle: Advances in Design Methods from Modeling Languages for Embedded Systems and SoC’s: Selected Contributions on Specification, Design, and Verification from FDL 2009 | Editor: Dominique Borrione
Publisher: Springer
Format: Hardcover (2010)

Synthesis of Boolean Functions in Reversible Logic
Author: Robert Wille, Rolf Drechsler
Booktitle: Progress in Applications of Boolean Functions (Synthesis Lectures on Digital Circuits and Systems) | Editor: Tsutomu Sasao, Jon T. Butler, Mitchell Thornton
Publisher: Morgan and Claypool Publishers
Format: Paperback (2010)

Non-Clausal SAT and ATPG
Author: Rolf Drechsler, Tommi Junttila and Ilkka Niemelä
Booktitle: Handbook of Satisfiability | Editor: A. Biere, M. Heule, H. van Maaren, T. Walsh
Publisher: IOS Press
Format: gebunden (2009)

Debugging Contradictory Constraints in Constraint-based Random Simulation
Author: Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Booktitle: Languages for Embedded Systems and their Applications: Selected Contributions on Specification, Design, and Verification from FDL'08 | Editor: Martin Radetzki
Publisher: Springer
Format: gebunden (2009)

SWORD: A SAT like Prover Using Word Level Information
Author: Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
Booktitle: VLSI-SoC: Advanced Topics on Systems on a Chip: A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip | Editor: Ricardo Reis, Vincent Mooney, Paul Hasler
Publisher: Springer
Format: Hardcover (2009)

An Integrated SystemC Debugging Environment
Author: Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke
Booktitle: Embedded Systems Specification and Design Languages: Selected contributions from FDL'07 | Editor: Eugenio Villar
Publisher: Springer
Format: gebunden (2008)

Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques
Author: Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
Booktitle: Embedded Systems Specification and Design Languages: Selected contributions from FDL'07 | Editor: Eugenio Villar
Publisher: Springer
Format: gebunden (2008)

Exact BDD Minimization for Path-Related Objective Functions
Author: Rüdiger Ebendt, Rolf Drechsler
Booktitle: VLSI-SoC: From Systems to Silicon | Editor: Ricardo Reis, Ada Osseiran, Hans-Jörg Pleiderer
Publisher: Springer
Format: gebunden (2007)

Stuck-At-Fault Testability of SPP Three-Level Logic Forms
Author: V. Ciriani, A. Bernasconi, Rolf Drechsler
Booktitle: VLSI-SOC: From Systems to Chips | Editor: M. Glesner, R. Reis, L. Indrusiak, V. Mooney, H. Eveking
Publisher: Springer
Format: gebunden (2006)

Exploration of Sequential Depth by Evolutionary Algorithms
Author: Nicole Drechsler, Rolf Drechsler
Booktitle: VLSI-SOC: From Systems to Chips | Editor: M. Glesner, R. Reis, L. Indrusiak, V. Mooney, H. Eveking
Publisher: Springer Boston
Format: gebunden (2006)

Processor Verification
Author: Daniel Große, Robert Siegmund, Rolf Drechsler
Booktitle: Customizable Embedded Processors | Editor: Paolo Ienne, Rainer Leupers
Publisher: Elsevier
Format: gebunden (2006)

Automatic Test Pattern Generation
Author: Rolf Drechsler, Görschwin Fey
Booktitle: Formal Methods for Hardware Verification, LNCS 3965 | Editor: Marco Bernardo, Alessandro Cimatti
Publisher: Springer
Format: gebunden (2006)

System-level validation using formal techniques
Author: Rolf Drechsler, Daniel Große
Booktitle: System-on-Chip: Next Generation Electronics | Editor: Bashir M. Al-Hashimi
Publisher: The IEE
Format: gebunden (2006)

cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits
Author: Chandan Kumar Jha, Muhammad Hassan, Rolf Drechsler
Jorunal: IEEE Transactions on Circuits and Systems I: Regular Papers
Details: DOI: 10.1109/TCSI.2024.3388256, noch nicht veröffentlicht (2024)

Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices
Author: Saeideh Nabipour, Javad Javidan, Rolf Drechsler
Jorunal: Memories-Materials, Devices, Circuits and Systems
Details: DOI: 10.1016/j.memori.2024.100099 (2024)

Special issue on in-memory computing: Circuits, system, architecture and verification
Author: Kamalika Datta, Rolf Drechsler
Jorunal: Memories-Materials, Devices, Circuits and Systems
Details: DOI: 10.1016/j.memori.2023.100062, Volume 5 (2023)

Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style
Author: Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin Patkar, Rolf Drechsler, Farhad Merchant
Jorunal: IEEE Embedded Systems Letters (ESL)
Details: DOI: 10.1109/LES.2023.3298740 (2023)

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation
Author: Sallar Ahmadi-Pour, Mathis Logemann, Vladimir Herdt, Rolf Drechsler
Jorunal: Chips
Details: DOI: 10.3390/chips2030012, Volume 2, Issue 3, pp. 195-208 (2023)

ReSG: A Data Structure for Verification of Majority based In-Memory Computing on ReRAM Crossbars
Author: Kousik Bhunia, Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler
Jorunal: ACM Transactions on Embedded Computing Systems
Details: DOI: 10.1145/3615358 (2023)

KI-gestützte Optimierung repetitiver Prozesse - Eine Kodierungstechnik für repetitive Prozesse in der evolutionären Optimierung
Author: Christina Plump, Bernhard J. Berger, Rolf Drechsler
Jorunal: Industrie 4.0 Management
Details: DOI: 10.30844/IM_23-1_19-22, IM 39, pp. 19-22 (2023)

AI-Driven and Automated MRI Sequence Optimization in Scanner-Independent MRI Sequences Formulated by a Domain-Specific Language
Author: Daniel Christopher Hoinkiss, Jörn Huber, Christina Plump, Christoph Lüth, Rolf Drechsler, Matthias Günther
Jorunal: Frontiers in Neuroimaging
Details: DOI: 10.3389/fnimg.2023.1090054, Volume 2-2023 (2023)

Impact of Sneak Paths on In-Memory Logic Design in Memristive Crossbars Information Technology
Author: Kamalika Datta, Arighna Deb, Abhoy Kole, Rolf Drechsler
Jorunal: it-Information Technology
Details: DOI: 10.1515/itit-2023-0020 (2023)

A Novel Default Risk Prediction and Feature Importance Analysis Technique for Marketplace Lending using Machine Learning
Author: Sana Hassan Imam, Sebastian Huhn, Lars Hornuf, Rolf Drechsler
Jorunal: Journal of Credit and Capital Markets
Details: DOI: 10.3790/ccm.56.1.27, Vol. 56 (2023), Iss. 1 : pp. 27–62 (2023)

MARADIV: Library of MAGIC based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors
Author: Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler
Jorunal: IEEE Transactions on Circuits and Systems II: Express Briefs
Details: DOI: 10.1109/TCSII.2023.3242976, Volume: 70 Issue: 7 (2023)

Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Jorunal: IEEE Internet of Things Journal
Details: DOI: 10.1109/JIOT.2023.3236694, Volume: 10 Issue: 11 (2023)

IMAGIN: Library of IMPLY and MAGIC NOR Based Approximate Adders for In-Memory Computing
Author: Chandan Kumar Jha, Phrangboklang Lyngton Thangkhiew, Kamalika Datta, Rolf Drechsler
Jorunal: IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Details: DOI: 10.1109/JXCDC.2022.3222015, Volume: 8 Issue: 2 (2022)

The MicroRV32 framework: An Accessible and Configurable Open Source RISC-V Cross-Level Platform for Education and Research
Author: Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Jorunal: Journal of Systems Architecture - Embedded Software Design (JSA)
Details: DOI: 10.1016/j.sysarc.2022.102757, Volume 133, 2022 (2022)

Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype
Author: Pascal Pieper, Vladimir Herdt and Rolf Drechsler
Jorunal: Journal of Low Power Electronics and Applications
Details: DOI: 10.3390/jlpea12040052, 12(4):52 (2022)

Feed-Forward learning algorithm for resistive memories
Author: Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta, Sandip Chakraborty, Rolf Drechsler and Indranil Sengupta
Jorunal: Journal of System Architecture (JSA)
Details: DOI: 10.1016/j.sysarc.2022.102730, 131 (2022) 102730 (2022)

FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications
Author: Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta, Sandip Chakraborty, Rolf Drechsler, Indranil Sengupta
Jorunal: Journal of Electronic Testing, Springer
Details: DOI: 10.1007/s10836-022-06001-2, Volume 38, pages 145–163 (2022) (2022)

Early SoCs Information Flow Policies Validation using SystemC-based Virtual Prototypes at the ESL
Author: Mehran Goli, Rolf Drechsler
Jorunal: ACM Transactions on Embedded Computing Systems (TECS)
Details: DOI: 10.1145/3544780 (2022)

Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits
Author: Kemal Çağlar Coşkun, Muhammad Hassan, Rolf Drechsler
Jorunal: Chips
Details: DOI 10.3390/chips1010006, Volume 1, Issue 1, pp. 54-71 (2022)

Power-aware Test Scheduling Framework for IEEE 1687 Multi-Power Domain Networks using Formal Techniques
Author: Payam Habiby, Sebastian Huhn, Rolf Drechsler
Jorunal: Microelectronics Reliability
Details: DOI: 10.1016/j.microrel.2022.114551, Volume 134, pp. 1-11 (2022)

Towards Quantification and Visualization of the Effects of Concretization during Concolic Testing
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Jorunal: IEEE Embedded Systems Letters (ESL)
Details: DOI: 10.1109/LES.2022.3171603, Volume: 14 Issue: 4 (2022)

CoMIC: Complementary Memristor based in-memory computing in 3D architecture
Author: F. Lalchhandama, Kamalika Datta, S. Chakraborty, Rolf Drechsler, I. Sengupta
Jorunal: Journal of Systems Architecture (JSA)
Details: DOI: 10.1016/j.sysarc.2022.102480, Volume 126, Article 102480 (2022)

Template-based mapping of reversible circuits to IBM quantum computers
Author: Philipp Niemann, Alexandre A. A. de Almeida, Gerhard Dueck, Rolf Drechsler
Jorunal: Microprocessors and Microsystems (MICPRO)
Details: DOI: 10.1016/j.micpro.2022.104487, Volume 90, April 2022 (2022)

SymEx-VP: An Open Source Virtual Prototype for OS-Agnostic Concolic Testing of IoT Firmware
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Jorunal: Journal of Systems Architecture - Embedded Software Design (JSA)
Details: DOI: 10.1016/ j.sysarc.2022.102456, Volume 126 (2022)

Unlocking Approximation for In-Memory Computing with Cartesian Genetic Programming and Computer Algebra for Arithmetic Circuits
Author: Saman Fröhlich, Rolf Drechsler
Jorunal: it-Information Technology
Details: DOI: 10.1515/itit-2021-0042 (2022)

Verzahnung von Data Stewardship und Data Science – Wege und Perspektiven
Author: Lena Steinmann, Rolf Drechsler
Jorunal: Bausteine Forschungsdatenmanagement
Details: DOI: 10.17192/bfdm.2021.3.8342, Nummer 3, pp. 83-91 (2021)

Disziplinübergreifendes Modell zur Ausbildung von Forschungsdatenmanagement und Data Science Kompetenzen: „Data Train – Training in Research Data Management and Data Science“
Author: Tanja Hörner, Frank Oliver Glöckner, Rolf Drechsler, Iris Pigeot
Jorunal: Bausteine Forschungsdatenmanagement
Details: DOI: 10.17192/bfdm.2021.3.8343, Nummer 3, pp. 57-69 (2021)

Advanced Virtual Prototyping for Cyber-Physical Systems using RISC-V: Implementation, Verification and Challenges
Author: Vladimir Herdt, Rolf Drechsler
Jorunal: Science China Information Sciences (SCIS)
Details: DOI: 10.1007/s11432-020-3308-4 (2021)

RevSCA-2.0: SCA-based Formal Verification of Non-trivial Multipliers using Reverse Engineering and Local Vanishing Removal
Author: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Jorunal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Details: DOI: 10.1109/TCAD.2021.3083682, Volume: 41 Issue: 5, pp.1573-1586 (2021)

Towards RISC-V CSR Compliance Testing
Author: Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
Jorunal: IEEE Embedded Systems Letters (ESL)
Details: DOI: 10.1109/LES.2021.3077368, Volume: 13 Issue: 4, pp. 202-205 (2021)

Parallel Computing of Graph-Based functions in ReRAM
Author: Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
Jorunal: Journal on Emerging Technologies in Computing Systems (JETC)
Details: DOI: 10.1145/3453163, Volume 18, Issue 2, Article No. 41, pp 1–2 (2021)

An ant colony based mapping of quantum circuits to nearest neighbor architectures
Author: Anirban Bhattacharjee, Chandan Bandyopadhyay, Angshu Mukherje, Robert Wille, Rolf Drechsler, Hafizur Rahamana
Jorunal: Integration
Details: DOI: 10.1016/j.vlsi.2020.12.002, Volume 78, May 2021, Pages 11-24 (2021)

Adaptive Simulation with Virtual Prototypes in an Open-Source RISC-V Evaluation Platform
Author: Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
Jorunal: Journal of Systems Architecture - Embedded Software Design (JSA)
Details: DOI: 10.1016/j.sysarc.2021.102135, Volume 116 (2021)

Through the Looking Glass: Automated Design Understanding of SystemC-based VPs at the ESL
Author: Mehran Goli, Rolf Drechsler
Jorunal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Details: DOI: 10.1109/TCAD.2021.3074050, Volume: 41 Issue: 4, pp. 1181-1185 (2021)

On the Difficulty of Inserting Trojans in Reversible Computing Architectures
Author: Xiaotong Cui, Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Kaijie Wu, Rolf Drechsler, Ramesh Karri
Jorunal: IEEE Transactions on Emerging Topics in Computing
Details: DOI 10.1109/TETC.2018.2823315, Volume: 8, Issue: 4, Oct.-Dec. 1 2020 (2020)

An Improved Heuristic Technique for Nearest Neighbor Realization of Quantum Circuits in 2D Architecture
Author: Anirban Bhattacharjee, Chandan Bandyopadhyay, Philipp Niemann, Bappaditya Mondal, Rolf Drechsler, Hafizur Rahaman
Jorunal: Integration
Details: DOI 10.1016/j.vlsi.2020.09.003, Volume 76, January 2021, Pages 40-54 (2020)

Improving the Designs of Nearest Neighbor Quantum Circuits for 1D and 2D Architectures
Author: Chandan Bandyopadhyay, Anirban Bhattacharjee, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Jorunal: IETE Journal of Research
Details: DOI: 10.1080/03772063.2020.1822215, Volume 69, 2023 - Issue 1, pp. 340-353 (2020)

ReCoFused partial reconfiguration for secure moving-target countermeasures on FPGAs
Author: Buse Ustaoğlu, Kenneth Schmitz, Daniel Große, Rolf Drechsler
Jorunal: SN Applied Sciences | Springer Nature
Details: DOI 10.1007/s42452-020-3003-x, Article number: 1363 (2020) (2020)

Advanced Exact Synthesis of Clifford+T Circuits
Author: Philipp Niemann, Robert Wille, Rolf Drechsler
Jorunal: Quantum Information Processing
Details: DOI: 10.1007/s11128-020-02816-0, 19, Article number: 317 (2020) (2020)

Overcoming the Trade-off Between Accuracy and Compactness in Decision Diagrams for Quantum Computation
Author: Philipp Niemann, Alwin Zulehner, Rolf Drechsler, Robert Wille
Jorunal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2020.2977603, Volume: 39 Issue: 12 (2020)

On the Impact of the Synchronization Constraint and Interconnections in Quantum-dot Cellular Automata
Author: Frank Sill Torres, Pedro A. Silva, Geraldo Fontes, Marcel Walter, José Augusto M. Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Robert Wille, Philipp Niemann, Daniel Große, Rolf Drechsler
Jorunal: Microprocessors and Microsystems (MICPRO)
Details: DOI: 10.1016/j.micpro.2020.103109, Volume 76, July 2020 (2020)

PREASC: Automatic Portion Resilience Evaluation for Approximating SystemC-based Designs using Regression Analysis Techniques
Author: Mehran Goli, Rolf Drechsler
Jorunal: ACM Transactions on Design Automation of Electronic Systems (TODAES)
Details: DOI: 10.1145/3388140, Volume: 25, number: 5, numpages: 28 (2020)

RISC-V based Virtual Prototype: An Extensible and Configurable Platform for the System-level
Author: Vladimir Herdt, Daniel Große, Pascal Pieper, Rolf Drechsler
Jorunal: Journal of Systems Architecture - Embedded Software Design (JSA)
Details: DOI: 10.1016/j.sysarc.2020.101756, Volume 109 (2020)

Reversible Circuits: IC/IP Piracy Attacksand Countermeasures
Author: Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler and Ramesh Karri
Jorunal: IEEE Transactions On Very Large Scale Integration (VLSI) Systems
Details: DOI: 10.1109/TVLSI.2019.2934465, Volume: 27 Issue: 11, pp. 1-13 (2019)

Near Zero-Energy Computation Using Quantum-dot Cellular Automata
Author: Frank Sill Torres, Robert Wille, Philipp Niemann, Rolf Drechsler
Jorunal: Journal on Emerging Technologies in Computing Systems (JETC)
Details: DOI 10.1145/3365394,Vol. 16, No. 1 (2019)

Placement & Routing for Tile-based Field-coupled Nanocomputing Circuits is NP-complete
Author: Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
Jorunal: Journal on Emerging Technologies in Computing Systems (JETC)
Details: DOI: 10.1145/3312661, Volume 15, Issue 3, Number 29 (2019)

Combining Sequentialization-based Verification of Multi-Threaded C Programs with Symbolic Partial Order Reduction
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Jorunal: International Journal of Software Tools for Technology Transfer (STTT)
Details: DOI: 10.1007/s10009-019-00507-5, 21(5):545-565 (2019)

Security Validation of VP-based SoCs Using Dynamic Information Flow Tracking
Author: Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
Jorunal: it-Information Technology
Details: DOI: 10.1515/itit-2018-0027 (2019)

Automated Non-intrusive Analysis of Electronic System Level Designs
Author: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Jorunal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2018.2889665, Volume: 39, number: 2, pages: 492-505 (2020)

Determining Application-specific Knowledge for Improving Robustness of Sequential Circuits
Author: Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler
Jorunal: IEEE Transactions On Very Large Scale Integration (VLSI) Systems
Details: DOI: 10.1109/TVLSI.2018.2890601, Volume 27, Number 4, Pages. 875-887 (2019)

The complexity of error metrics
Author: Oliver Keszöcze, Mathias Soeken, Rolf Drechsler
Jorunal: Information Processing Letters
Details: DOI: 10.1016/j.ipl.2018.06.010, Volume 139, pp. 1-7 (2018)

On the complexity of design tasks for Digital Microfluidic Biochips
Author: Oliver Keszöcze, Philipp Niemann, Arved Friedemann, Rolf Drechsler
Jorunal: Microelectronics Journal
Details: DOI: 10.1016/j.mejo.2018.05.013, Volume 78, Pages 35-45 (2018)

Evaluation of (power) side-channels in cryptographic implementations
Author: Florian Bache, Christina Plump, Jonas Wloka, Tim Güneysu, and Rolf Drechsler
Jorunal: it – Information Technology
Details: DOI: 10.1515/itit-2018-0028, Volume 61(1) (2019)

Arduinos in der Schule - Lernen mit Mikrocontrollern
Author: Cornelia Große, Claudia Sobich, Sebastian Huhn, Markus Leuschner, Rolf Drechsler, Lutz Mädler
Jorunal: Computer + Unterricht
Details: Volume 110, May 2018, Pages 43-45 (2018)

Verifying SystemC using Intermediate Verification Language and Stateful Symbolic Simulation
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)
Details: DOI: 10.1109/TCAD.2018.2846638, 38(7):1359-1372 (2018)

Logic synthesis for RRAM-based in-memory computing
Author: Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
Jorunal: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2017.2750064, Vol. 37, no. 7, pp. 1422-1435 (2018)

Behaviour Driven Development for Hardware Design
Author: Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler
Jorunal: IPSJ Transactions on System LSI Design Methodology
Details: DOI: 10.2197/ipsjtsldm.11.29, Vol. 11, pp. 29-45, PDF Download (2018)

An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs
Author: Robert Wille, Oliver Keszöcze, Larts Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Jorunal: Journal of Low Power Electronics
Details: DOI: 10.1166/jolpe.2017.1515, Volume 13, Number 4, Pages 633-641 (2017)

An Energy-aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata
Author: Frank Sill Torres, Robert Wille, Philipp Niemann, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2018.2789782, Vol. 37, no. 12, pp. 3031-3041 (2018)

Frame Conditions in the Automatic Validation and Verification of UML/OCL Models: A Symbolic Formulation of modifies only Statements
Author: Nils Przigoda, Philipp Niemann, Jonas Gomes Filho, Robert Wille, Rolf Drechsler
Jorunal: Computer Languages, Systems & Structures
Details: DOI: 10.1016/j.cl.2017.11.002, Volume 54, Pages 512-527 (2018)

Synthesis of optical circuits using binary decision diagrams
Author: Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler
Jorunal: Integration, the VLSI Journal
Details: DOI: 10.1016/j.vlsi.2017.05.001, Volume 59, September 2017, Pages 42–51 (2017)

A PLiM computer for the IoT
Author: Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli
Jorunal: Computer
Details: DOI: 10.1109/MC.2017.173, 50(6):35-40 (2017)

Towards a Verification Flow Across Abstraction Levels:
Verifying Implementations Against Their Formal Specification

Author: Pablo Gonzalez-de-Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, Pablo Sanchez
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2016.2611494, 36(3):475-488 (2017)

metaSMT: Focus On Your Application And Not On Solver Integration
Author: Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey
Jorunal: International Journal of Software Tools for Technology Transfer
Details: DOI 10.1007/s10009-016-0426-1, 19(5):605-621 (2017)

Verifying the Structure and Behavior in UML/OCL Models Using Satisfiability Solvers
Author: Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler
Jorunal: IET Cyber-Physical Systems: Theory & Applications
Details: DOI: 10.1049/iet-cps.2016.0022, Volume 1, Issue 1, pp. 49-59 (2016)

Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits
Author: Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler
Jorunal: Journal on Emerging Technologies in Computing Systems (JETC)
Details: DOI: 10.1145/2904445, Volume 13, Issue 1 (2016)

Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability
Author: Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya
Jorunal: Journal on Emerging Technologies in Computing Systems (JETC)
Details: DOI: 10.1145/2894757, Volume 12 Issue 4, Article No. 34 (2016)

On Optimization-based ATPG and its Application for Highly Compacted Test Sets
Author: Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2016.2552822, Vol. 35(12), pp. 2104-2117 (2016)

Time-resolved detection of diffusion limited temperature gradients inside single isolated burning droplets using Rainbow Refractometry
Author: Christopher Rosebrock, Saeideh Shirinzadeh, Mathias Soeken, Norbert Riefler, Thomas Wriedt, Rolf Drechsler, Lutz Mädler
Jorunal: Combustion and Flame
Details: DOI: 10.1016/j.combustflame.2016.03.007, Volume 168, June 2016, Pages 255–269 (2016)

Complexity of Reversible Circuits and their Quantum Implementations
Author: Nabila Abdessaied, Matthew Amy, Rolf Drechsler, Mathias Soeken
Jorunal: Theoretical Computer Science
Details: DOI: 10.1016/j.tcs.2016.01.011, Volume 618, pp. 85–106 (2016)

Analyzing Inconsistencies in UML/OCL Models
Author: Nils Przigoda, Robert Wille, Rolf Drechsler
Jorunal: Journal of Circuits, Systems and Computers
Details: DOI: 10.1142/S0218126616400211, Volume 25, Issue 03 (2016)

KI-Unterstützung im Systementwurf – Wenn Computer lernen, wie Computer arbeiten
Author: Jannis Stoppe, Rolf Drechsler
Jorunal: Industrie 4.0 Management
Details: 1/2015, Nr. 5104 (2015)

Atomic distributions in crystal structures solved by Boolean satisfiability techniques
Author: Mathias Soeken, Rolf Drechsler, Reinhard X. Fischer
Jorunal: Zeitschrift für Kristallographie - Crystalline Materials
Details: DOI: 10.1515/zkri-2015-1887, Z. Kristallogr. 2016; 231(2): 107–111 (2015)

SyReC: A Hardware Description Language for the Specification and Synthesis of Reversible Circuits
Author: Robert Wille, Eleonora Schonborn, Mathias Soeken, Rolf Drechsler
Jorunal: INTEGRATION, the VLSI Journal
Details: DOI: 10.1016/j.vlsi.2015.10.001, 53(3):39-53 (2016)

Analyzing SystemC Designs: SystemC Analysis Approaches for Varying Applications
Author: Jannis Stoppe, Rolf Drechsler
Jorunal: Sensors
Details: DOI: 10.3390/s150510399, Volume (issue) 15(5), pages 10399-10421 (2015)

Scalable One-Pass Synthesis for Digital Microfluidic Biochips
Author: Robert Wille, Oliver Keszöcze, Tobias Boehnisch, Alexander Kroker, Rolf Drechsler
Jorunal: IEEE Design & Test of Computers
Details: DOI: 10.1109/MDAT.2015.2455344, Volume 32, Issue 66, Pages 41—50 (2015)

QMDDs: Efficient Quantum Function Representation and Manipulation
Author: Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2015.2459034, Volume 35, Number 1, pp. 86-99 (2016)

Embedding of Large Boolean Functions for Reversible Logic
Author: Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler
Jorunal: Journal on Emerging Technologies in Computing Systems (JETC)
Details: DOI 10.48550/arXiv.1408.3586, Volume 12, Issue 4 (2015)

Ancilla-free synthesis of large reversible functions using binary decision diagrams
Author: Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler
Jorunal: Journal of Symbolic Computation
Details: DOI 10.48550/arXiv.1408.3955 (2015)

Benefits of illustrations and videos for technical documentations
Author: Cornelia Große, Lisa Jungmann, Rolf Drechsler
Jorunal: Computers in Human Behavior
Details: DOI 10.1016/j.chb.2014.11.095, Volume 45, Pages 109–120 (2015)

Incorporating User Preferences in Many-Objective Optimization using Relation epsilon-Preferred
Author: Nicole Drechsler, André Sülflow, Rolf Drechsler
Jorunal: Natural Computing
Details: DOI: 10.1007/s11047-014-9422-0, Volume 14, Issue 3, pp 469-483 (2015)

Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures
Author: Robert Wille, Aaron Lye, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2014.2356463, Volume 33, Number 12, pp. 1818-1831 (2014)

Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic
Author: Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler
Jorunal: Transactions on Computational Science
Details: XXIV, pp 129–146, DOI: 10.1007/978-3-662-45711-5_8 (2014)

An Approach to Reversible Logic Synthesis Using Input and Output Permutations
Author: Kamalika Datta, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Jorunal: Transactions on Computational Science
Details: XXIV, pp 92-110, DOI: 10.1007/978-3-662-45711-5_6 (2014)

Special Issue on Reversible Computation
Author: Robert Wille, Rolf Drechsler, Mehdi . B. Tahoori (editors)
Jorunal: Journal on Emerging Technologies in Computing Systems (JETC)
Details: DOI: 10.1145/2663349, Volume 11, Number 2 (2014)

An effective fault ordering heuristic for SAT-based dynamic test compaction techniques
Author: Stephan Eggersglüß, Rolf Drechsler
Jorunal: it-Information Technology
Details: DOI: 10.1515/itit-2013-1041, Volume 56, Number 4, pp. 157-164 (2014)

Testing integrated circuits
Author: Rolf Drechsler
Jorunal: it-Information Technology
Details: DOI: 10.1515/itit-2014-1043, Volume 56, Number 4, pp. 148-149 (2014)

Upper bounds for reversible circuits based on Young subgroups
Author: Nabila Abdessaied, Mathias Soeken, Michael Kirkedal Thomsen, Rolf Drechsler
Jorunal: Information Processing Letters
Details: DOI: 10.1016/j.ipl.2014.01.003, Volume 114, Number 06, pp. 282-286 (2014)

Formale Verifikation von UML-basierten Spezifikationen, Prüfung der Korrektheit von Systementwürfen vor deren Implementierung
Author: Mathias Soeken, Robert Wille, Rolf Drechsler
Jorunal: In Industrie Management 1/2013
Details: pp.44-48, 2013 (2013)

Considering Nearest Neighbor Constraints of Quantum Circuits at the Reversible Circuit Level
Author: Robert Wille, Aaron Lye, Rolf Drechsler
Jorunal: Quantum Information Processing
Details: DOI: 10.1007/s11128-013-0642-5 (2013)

Quantum circuits employing roots of the Pauli matrices
Author: Mathias Soeken, D. Michael Miller, Rolf Drechsler
Jorunal: Physical Review A
Details: DOI: 10.1103/PhysRevA.88.042322, Volume 88 (2013)

Trading Off Circuit Lines and Gate Costs in the Synthesis of Reversible Logic
Author: Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler
Jorunal: INTEGRATION, the VLSI Journal
Details: DOI: 10.1016/j.vlsi.2013.08.002, Volume 47, Number 2, pp. 284-294 (2014)

A Formal Model for Embedded Brain Reading
Author: Elsa Andrea Kirchner, Rolf Drechsler
Jorunal: Industrial Robot: an International Journal
Details: DOI 10.1108/IR-01-2013-318, Volume 40, Issue 6, pp. 530-540 (2013)

Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits
Author: Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Jorunal: Multiple-Valued Logic and Soft Computing
Details: Volume 21, Number 5-6, 2013, pp. 627-640 (2013)

RevKit: An Open Source Toolkit for the Design of Reversible Circuits
Author: Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Jorunal: Reversible Computation 2011 (Series: Lecture Notes in Computer Science)
Details: DOI: 10.1007/978-3-642-29517-1_6, Volume 7165, 3rd Int. Workshop, RC 2011, Revised Papers, pp. 64-76 (2012)

Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis
Author: Daniel Große, Görschwin Fey, Rolf Drechsler
Jorunal: Electronic Communications of the EASST
Details: DOI 10.14279/tuj.eceasst.62.860, Volume 62, pp. 13 (2013)

Automatic TLM Fault Localization for SystemC
Author: Hoang M. Le, Daniel Große, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2012.2188800 , Volume 31, Number 8, pp. 1249-1262 (2012)

Special Issue on Reversible Computation
Author: Rolf Drechsler, Irek Ulidowski, Robert Wille (editors)
Jorunal: Multiple-Valued Logic and Soft Computing
Details: Volume 18, Number 1 (2012)

RevKit: A Toolkit for Reversible Circuit Design
Author: Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Jorunal: Multiple-Valued Logic and Soft Computing
Details: Volume 18, Number 1, pp. 55-65 (2012)

A Highly Fault-Efficient SAT-Based ATPG Flow
Author: Stephan Eggersglüß, Rolf Drechsler
Jorunal: IEEE Design & Test of Computers
Details: DOI: 10.1109/MDT.2012.2205479, Volume 29, Issue 4, pp. 63-70 (2012)

Efficient Data Structures and Methodologies for SAT-based ATPG providing High Fault Coverage in Industrial Application
Author: Stephan Eggersglüß, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2011.2152450, Volume 30, Number 9, pp. 1411-1415 (2011)

Effective Robustness Analysis using Bounded Model Checking Techniques
Author: Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2011.2120950, Volume 30, Number 8, pp. 1239-1252 (2011)

Synthesis of Quantum Circuits for Linear Nearest Neighbor Architectures
Author: Mehdi Saeedi, Robert Wille, Rolf Drechsler
Jorunal: Quantum Information Processing
Details: DOI :10.1007/s11128-010-0201-2, Volume 10, Number 3, pp. 355-377 (2011)

Debugging Reversible Circuits
Author: Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Jorunal: INTEGRATION, the VLSI Journal
Details: DOI: 10.1016/j.vlsi.2010.08.002, Volume 44, Number 1, pp. 51-61, January (2011)

BDD-Based Synthesis of Reversible Logic
Author: Robert Wille, Rolf Drechsler
Jorunal: International Journal of Applied Metaheuristic Computing (IJAMC)
Details: DOI: 10.1145/1629911.1629984, Volume 1, Number 4, pp. 25-41 (2010)

Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen
Author: Görschwin Fey, Andre Sülflow, Stefan Frehse, Rolf Drechsler
Jorunal: it-Information Technology
Details: DOI: 10.1524/itit.2010.0594, Volume 52, Number 4, pp. 216-223 (2010)

Towards Fully Automatic Synthesis of Embedded Software
Author: Ulrich Kühne, Daniel Große, Rolf Drechsler
Jorunal: IEEE Embedded Systems Letters
Details: DOI: 10.1109/LES.2010.2049983, Volume 2, Number 3, pp. 53-57 (2010)

Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
Author: Robert Wille, Rolf Drechsler
Jorunal: Electronic Notes in Theoretical Computer Science
Details: DOI: 10.1016/j.entcs.2010.02.006, Volume 253, Number 6, pp. 57-70 (2010)

Incremental Solving Techniques for SAT-based ATPG
Author: Daniel Tille, Stephan Eggersglüß, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2010.2044673, Volume 29, Number 7, pp. 1125-1130 (2010)

Synthese reversibler Logik
Author: Robert Wille, Rolf Drechsler
Jorunal: it-Information Technology
Details: DOI: 10.1524/itit.2010.0568,Volume 52, Number 1, pp. 30-38 (2010)

MONSOON: SAT-based ATPG for Path Delay Faults Using Multiple-Valued Logics
Author: Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Rolf Drechsler
Jorunal: Journal of Electronic Testing: Theory and Applications
Details: DOI: 10.1007/s10836-010-5146-y,Volume 26, Number 3, pp. 307-322, Pdf download (2010)

Overcoming the limitations of data introspection for SystemC
Author: Christian Genz, Rolf Drechsler
Jorunal: EDA Tech Forum
Details: DOI: 10.1109/DATE.2009.5090734, Volume 6, Issue 5, pp. 30-34 (2009)

Formale Verifikation von logistischen Prozessmodellen
Author: B. Scholz-Reiter, M. Lütjen, C. Ruthenbeck, F. Harjes, Rolf Drechsler
Jorunal: ERP Management
Details: Volume 5, pp.44-47 (2009)

Weighted A* search - unifying view and application
Author: Rüdiger Ebendt, Rolf Drechsler
Jorunal: Artificial Intelligence
Details: DOI: 10.1016/j.artint.2009.06.004, Volume 173, Issue 15, pp. 1367-1456 (2009)

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
Author: Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille
Jorunal: it - information technology
Details: DOI: 10.1524/itit.2009.0529, Volume 51, Number 2, pp. 102-111, Pdf download (2009)

Exact Synthesis of Elementary Quantum Gate Circuits
Author: Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Jorunal: Multiple-Valued Logic and Soft Computing
Details: DOI: 10.1109/ISMVL.2008.42, Volume 15, Number 4, pp. 283-300 (2009)

Advanced Verification by Automatic Property Generation
Author: Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
Jorunal: IET Computers & Digital Techniques
Details: DOI: 10.1049/iet-cdt.2008.0110, Volume 3, Issue 4, pp. 338-353 (2009)

Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
Author: Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2009.2017215, Volume 28, Number 5, pp. 703-715 (2009)

Modeling and Proving Completeness in Formal Verification of Counting Heads
Author: Sebastian Kinder, Rolf Drechsler
Jorunal: Software Tools for Technology Transfer (STTT)
Details: DOI: 10.1007/s10009-008-0084-z, Springer, Volume 10, Number 6, pp. 521 - 534 (2008)

On Acceleration of SAT-based ATPG for Industrial Designs
Author: Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel, Daniel Tille
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2008.923107, Volume 27, Number 7, pp. 1329-1333 (2008)

Improved SAT-based Reachability Analysis with Observability Don’t Cares
Author: Sean Safarpour, Andreas Veneris and Rolf Drechsler
Jorunal: Journal on Satisfiability, Boolean Modeling and Computation (JSAT)
Details: DOI: 10.3233/SAT190050, Volume 5, pp. 1-25, Special Volume on Application of Constraints to Formal Verification (2008)

On the Construction of Small Fully Testable Circuits with Low Depth
Author: Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
Jorunal: Embedded Hardware Design - Microprocessors and Microsystems (MICPRO)
Details: DOI: 10.1016/j.micpro.2008.03.005, Special Issue, Volume 32, Issues 5-6, pp. 263-269 (2008)

Logic Minimization and Testability of 2-SPP Networks
Author: Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2008.923072, Volume 27, Number 7, pp. 1190-1202 (2008)

Analyzing Functional Coverage in Bounded Model Checking
Author: Daniel Große, Ulrich Kühne, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2008.925790, Volume 27, Number 7, pp. 1305-1314 (2008)

Automatic Fault Localization for Property Checking
Author: Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2008.923234, Volume 27, Number 6, pp. 1138-1149, June (2008)

BDD-based Verification of Scalable Designs
Author: Daniel Große, Rolf Drechsler
Jorunal: Facta Universitatis, Series: Electronics and Energetics
Details: DOI: 10.2298/FUEE0703367G, Volume 20, Number 3, pp. 367-379 (2007)

Building Free Binary Decision Diagrams Using SAT Solvers
Author: Robert Wille, Görschwin Fey, Rolf Drechsler
Jorunal: Facta Universitatis, Series: Electronics and Energetics
Details: DOI: 10.2298/FUEE0703381W, Volume 20, Number 3, pp. 381-394, (2007)

An Integrated Approach for Combining BDDs and SAT Provers
Author: Rolf Drechsler, Görschwin Fey, Sebastian Kinder
Jorunal: Facta Universitatis, Series: Electronics and Energetics
Details: DOI: 10.2298/FUEE0703415D, Volume 20, Number 3, pp. 415-436 (2007)

Technische Dokumentation von Soft- und Hardware in eingebetteten Systemen
Author: Beate Muranko, Rolf Drechsler
Jorunal: it - information technology
Details: DOI: 10.1524/itit.2007.49.2.110, Number 2, pp. 110-117, Pdf download (2007)

Exact minimisation of path-related objective functions for binary decision diagrams
Author: Rüdiger Ebendt, Rolf Drechsler
Jorunal: IEE Proceedings Computer & Digital Techniques
Details: DOI: 10.1049/ip-cdt:20050181, Volume 153, Number 4, pp. 231-242 (2006)

Testability of SPP Three-Level Logic Networks in Static Fault Models
Author: Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2005.862746, Volume 25, Number 10, pp. 2241-2248 (2006)

The Effect of Improved Lower Bounds in Dynamic BDD Reordering
Author: Rüdiger Ebendt, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2005.854632, Volume 25, Number 5, pp. 902-909 (2006)

Minimizing the Number of Paths in BDDs - Theory and Algorithm
Author: Görschwin Fey, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2005.852662, Volume 25, Number 1, pp. 4-11 (2006)

Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization
Author: Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2005.852053, Volume 24, Number 10, pp. 1515-1529 (2005)

System Level Validation Using Formal Techniques
Author: Rolf Drechsler, Daniel Große
Jorunal: IEE Proceedings Computer & Digital Techniques, Special Issue on Embedded Microelectronic Systems: Status and Trends
Details: DOI: 10.1049/ip-cdt:20045073, Volume 152, Number 3, pp. 393-406 (2005)

Generic Implementation of Multi-Valued Decision Diagram Packages
Author: Rolf Drechsler, Dragan Jankovic, Radomir Stankovic
Jorunal: Multiple-Valued Logic and Soft Computing
Details: Volume 11, Numbers 1-2, pp. 1-18 (2005)

Project-Based Learning in Student Teams in Computer Science Education
Author: Andreas Breiter, Görschwin Fey, Rolf Drechsler
Jorunal: Facta Universitatis, Series: Electronics and Energetics
Details: DOI: 10.2298/FUEE0502165B, Volume 18, Number 2, pp. 165-180 (2005)

Synthesis of Fully Testable Circuits from BDDs
Author: Rolf Drechsler, Junhao Shi, Görschwin Fey
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2004.823342, Volume 23, Number 3 (2004)

Methods for Construction of Recursive Algorithms for Reed-Mulle-Fourier Polarity Matrices Calculation
Author: Dragan Jankovic, Rolf Drechsler
Jorunal: Multiple-Valued Logic and Soft Computing
Details: Volume 10, Numbers 1, pp. 29-50 (2004)

Using Word-Level Information in Formal Hardware Verification
Author: Rolf Drechsler
Jorunal: Automation and Remote Control
Details: DOI: 10.1023/B:AURC.0000030907.28679.82, Volume 65, Issue 6, pp. 963-977 (2004)

An Improved Branch and Bound Algorithm for Exact BDD Minimization
Author: Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/TCAD.2003.819427, Volume 22, Number 12, pp. 1657-1663 (2003)

Recursive Bi-Partitioning of Netlists for Large Number of Partitions
Author: Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
Jorunal: Journal of Systems Architecture - the Euromicro Journal
Details: DOI: 10.1109/DSD.2002.1115349, Volume 49, pp. 521-528 (2003)

Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC
Author: Daniel Große, Rolf Drechsler
Jorunal: it - information technology
Details: DOI: 10.1524/itit.45.4.219.22731, Number 4, pp. 219-226 (2003)

Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams
Author: Wolfgang Günther, Rolf Drechsler
Jorunal: IEEE Transactions on Computers
Details: DOI: 10.1109/TC.2003.1228514, Volume 52, Number 9, pp. 1196-1209 (2003)

Exact Routing with Search Space Reduction
Author: Frank Schmiedle, Rolf Drechsler, Bernd Becker
Jorunal: IEEE Transactions on Computers
Details: DOI: 10.1109/TC.2003.1204836, Volume 52, Number 6, pp. 815-825 (2003)

Computer Architecture Core of Knowledge for Computer Science Studies
Author: M. Stojcev, I. Milentijevic, D. Kehagias, Rolf Drechsler, M. Gusev
Jorunal: Cyprus Computer Society Journal
Details: Volume I, Edition 4, April (2003)

Polynomial Formal Verification of Multipliers
Author: Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor
Jorunal: Formal Methods in System Design: An International Journal
Details: DOI: 10.1023/A:1021752130394, Volume 22, Issue 1, pp. 39-58 (2003)

Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation
Author: Rolf Drechsler, Mikael Kerttu, Per Lindgren, Mitch Thornton
Jorunal: Canadian Journal of Electrical and Computer Engineering
Details: Volume 27, Number 4, pp. 159-164, October (2002)

Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts
Author: M. Perkowski, B. Falkowski, M. Chrzanowska-Jeske, Rolf Drechsler
Jorunal: In VLSI Design — An International Journal of Custom-Chip Design, Simulation, and Testing, Special Issue on Spectral Techniques and Decision Diagrams
Details: Volume 14, Number 1, pp. 35-52, February 2002 (2002)

Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs
Author: M. A. Thornton, Rolf Drechsler, W. Günther
Jorunal: VLSI Design
Details: DOI: 10.1080/10655140290009800, Volume 14, Article ID 290173 (2002)

Minimization of Word-level Decision Diagrams
Author: Rolf Drechsler, Wolfgang Günther, Stefan Höreth.
Jorunal: INTEGRATION, the VLSI Journal
Details: DOI: 10.1016/S0167-9260(02)00047-0, Volume 33, Issue 1-2, pp. 39-70 (2002)

Minimization of Free BDDs
Author: Wolfgang Günther, Rolf Drechsler
Jorunal: INTEGRATION, the VLSI Journal
Details: DOI: 10.1109/ASPDAC.1999.760024, Volume 32, Issue 1-2, pp. 41-59 (2002)

Verifying Integrity of Decision Diagrams
Author: Rolf Drechsler
Jorunal: INTEGRATION, the VLSI Journal
Details: DOI: 10.1016/S0167-9260(02)00042-1, Volume 32, Issue 1-2, pp. 61-75 (2002)

Heuristic Learning based on Genetic Programming
Author: Frank Schmiedle, Nicole Drechsler, Daniel Große and Rolf Drechsler
Jorunal: Genetic Programming and Evolvable Machines
Details: DOI: 10.1023/A:1020988925923, Volume 3, pp. 363-388 (2002)

Dynamic Re-Encoding During MDD Minimization
Author: Frank Schmiedle, Wolfgang Günther, Rolf Drechsler
Jorunal: Multiple-Valued Logic - An International Journal
Details: Volume 8, Numbers 5-6, pp. 625-643 (2002)

History-based Dynamic BDD Minimization
Author: Rolf Drechsler, Wolfgang Günther
Jorunal: INTEGRATION, the VLSI Journal
Details: DOI: 10.1016/S0167-9260(01)00021-9, Volume 31, Issue 1, pp. 51-63 (2001)

Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld
Author: Rolf Drechsler
Jorunal: it+ti - Informationstechnik und Technische Informatik
Details: DOI: 10.1524/itit.2001.43.4.200, Oldenbourg Wissenschaftsverlag, Number 4, pp. 200-205 (2001)

Fault Simulation in Multi-Valued Logic Networks
Author: Rolf Drechsler, Martin Keim, Bernd Becker
Jorunal: Multiple-Valued Logic - An International Journal
Details: Volume 7, Numbers 1-2, pp. 25-47 (2001)

Binary Decision Diagrams in Theory and Practice
Author: Rolf Drechsler, Detlef Sieling
Jorunal: Software Tools for Technology Transfer (STTT)
Details: DOI: 10.1007/s100090100056, Springer, Number 3, pp. 112-136 (2001)

Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
Author: Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker
Jorunal: Journal of Electronic Testing, Theory and Application (JETTA)
Details: DOI: 10.1023/A:1011193725824, No. 17, pp. 37-51 (2001)

Decision Diagram Method for Calculation of Pruned Walsh Transform
Author: Dragan Jankovic, Radomir Stankovic, Rolf Drechsler
Jorunal: IEEE Transactions on Computers
Details: DOI: 10.1109/12.908990, Volume 50, Number 2, pp. 147-157 (2001)

Using Lower Bounds during Dynamic BDD Minimization
Author: Rolf Drechsler, Wolfgang Günther, Fabio Somenzi
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/43.905674, Volume 20, Number 1, pp. 51-57 (2001)

ACTion: Combining Logic Synthesis and Technology Mapping for MUX based FPGAs
Author: Wolfgang Günther and Rolf Drechsler.
Jorunal: Journal of Systems Architecture - the Euromicro Journal
Details: DOI: 10.1016/S1383-7621(00)00027-8, Volume 46, Issue 14, pp. 1321-1334, December (2000)

EXOR transform of inputs to design efficient two-level AND/EXOR adders
Author: Rolf Drechsler, Bernd Becker
Jorunal: Electronics Letters
Details: DOI: 10.1049/el:20000214, Stevenage Bd. 36, Ausg. 3, (Feb 3, 2000): 1-2 (2000)

Boolean Function Representation and Spectral Characterization Using AND/OR Graphs
Author: Alenka Zuzek, Rolf Drechsler, Mitch Thornton
Jorunal: INTEGRATION, the VLSI Journal
Details: DOI: 10.1016/S0167-9260(00)00003-1, Volume 29, Issue 2, pp. 101-116, September (2000)

Genetic Algorithm for Minimization of fixed polarity Reed-Muller expressions
Author: Rolf Drechsler, Bernd Becker and Nicole Drechsler
Jorunal: IEE Proceedings Computers and Digital Techniques
Details: DOI: 10.1049/ip-cdt:20000743, Volume 147, Number 5, September (2000)

On the Computational Power of Linearly Transformed BDDs
Author: Wolfgang Günther, Rolf Drechsler
Jorunal: Information Processing Letters
Details: DOI: 10.1016/S0020-0190(00)00083-1, Volume 75, Nummer 3, pp. 119-125, August (2000)

Fast Exact Minimization of BDDs
Author: Rolf Drechsler, Nicole Drechsler, Wolfgang Günther
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: Volume 19, Number 3, pp. 384-389, March (2000)

Pseudo Kronecker Expressions for Symmetric Functions
Author: Rolf Drechsler
Jorunal: IEEE Transactions on Computers
Details: DOI: 10.1109/12.795226, Volume 48, Number 9, pp. 987-990, September (1999)

ETDD-based synthesis of two-dimensional cellular arrays for multi-output incompletely specified Boolean functions
Author: G. Lee, Rolf Drechsler, M. A. Perkowski
Jorunal: IEE Proceedings - Computers and Digital Techniques
Details: DOI: 10.1049/ip-cdt:19990798, Volume 146, Issue 6, pp. 302–308 (1999)

OKFDD minimization by genetic algorithms with application to circuit design
Author: Rolf Drechsler, Bernd Becker, Nicole Drechsler
Jorunal: Integration
Details: DOI: 10.1016/S0167-9260(99)00017-6, Volume 28, Issue 2, pp. 121-139 (1999)

Testability of 2-Level AND/EXOR Circuits
Author: Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker
Jorunal: Journal of Electronic Testing, Theory and Application (JETTA)
Details: DOI: 10.1023/A:1008306002882, Volume 14, Number 3, pp. 173-192, June (1999)

BDD Minimization Using Symmetries
Author: Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler
Jorunal: IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
Details: DOI: 10.1109/43.743706, Volume 18, Number 2, pp. 81-100, February (1999)

On Variable Ordering and Decomposition Type Choice in OKFDDs
Author: Rolf Drechsler, Bernd Becker, Andrea Jahnke
Jorunal: IEEE Transactions on Computers
Details: DOI: 10.1109/12.737685, Volume 47, Number 12, December (1998)

Is Simulation the Only Alternative for Effective Verification of Dynamic Quantum Circuits?
Author: Liam Hurwitz, Kamalika Datta, Abhoy Kole, Rolf Drechsler
Conference: International Conference on Reversible Computation (RC)
Reference: Torun, Poland, 2024

Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification
Author: Khushboo Qayyum, Abhoy Kole, Kamalika Datta, Muhammad Hassan, Rolf Drechsler
Conference: Great Lakes Symposium on VLSI (GLSVLSI)
Reference: Tempa Bay Area, Florida, USA , 2024

Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification
Author: Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Reference: San Francisco, USA, 2024

Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent
Author: Kemal Çağlar Coşkun, Muhammad Hassan, Lars Hedrich, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2024

Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences
Author: Jan Zielasko, Rune Krauss, Marcel Merten, Rolf Drechsler
Conference: International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Kielce, Poland, 2024

Polynomial Formal Verification of Approximate Adders with Constant Cutwidth
Author: Mohamed Nadeem, Chandan Kumar Jha, Rolf Drechsler
Conference: IEEE European Test Symposium (ETS)
Pdf | Reference: The Hague, Netherlands, 2024

Polynomial Formal Verification of Multi-Valued Logic Circuits within Constant Cutwidth Architectures
Author: Mohamed Nadeem, Rolf Drechsler
Conference: IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Brno, Czech Republic, 2024

Polynomial Formal Verification of Sequential Circuits
Author: Caroline Dominik, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Valencia, Spain, 2024

Hidden Cost of Circuit Design with RFETs
Author: Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Valencia, Spain, 2024

LLM-guided Formal Verification Coupled with Mutation Testing
Author: Muhammad Hassan, Sallar Ahmadi-Pour, Khushboo Qayyum, Chandan Kumar Jha, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Valencia, Spain, 2024

Dynamic Realization of Multiple Control Toffoli Gate
Author: Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Valencia, Spain, 2024

Complete and Efficient Verification for a RISC-V Processor using Formal Verification
Author: Lennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Valencia, Spain, 2024

In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures
Author: Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta and Rolf Drechsler
Conference: International Conference on VLSI Design (VLSID)
Pdf | Reference: Kolkata, India, 2024

Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array
Author: Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana
Conference: International Conference on VLSI Design (VLSID)
Pdf | Reference: Kolkata, India, 2024

Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic
Author: Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler
Conference: International Conference on VLSI Design (VLSID)
Pdf | Reference: Kolkata, India, 2024

A Dynamic Programming Based Graph Traversal Approach for Efficient Implementation of Nearest Neighbor Architecture in 2D
Author: Sneha Lahiri, Megha Kesh, Rupsa Mandal, Sovan Bhattacharya, Anirban Bhattacharjee, Dola Sinha, Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler, Robert Wille
Conference: International Conference on VLSI Design (VLSID)
Reference: Kolkata, India, 2024

MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory
Author: Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin Patkar, Rolf Drechsler, Farhad Merchant
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Reference: Incheon Songdo Convensia, South Korea, 2024

Security Coverage Metrics for Information Flow at the System Level
Author: Ece Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Incheon Songdo Convensia, South Korea, 2024

Energy-Efficient CNN inferencing on GPUs with Dynamic Frequency Scaling
Author: Rolf Drechsler, Christopher Metz, und Christina Plump
Conference: International Conference on Innovations in Data Analytics (ICIDA)
Pdf | Reference: West Bengal, India, 2023

PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor
Author: Lennart Weingarten, Kamalika Datta, Rolf Drechsler
Conference: ACM International Symposium on Nanoscale Architectures (NANOARCH)
Reference: Dresden, Germany, 2023

Memristors: Device Modeling, Design and Verification
Author: Kamalika Datta, Rolf Drechsler
Conference: IEEE International Symposium on Smart Electronic Systems (iSES)
Reference: Ahmedabad, India, 2023

Automated Polynomial Formal Verification: Human-Readable Proof Generation
Author: Rolf Drechsler, Martha Schnieber
Conference: IEEE International Symposium on Smart Electronic Systems (iSES)
Pdf | Reference: Ahmedabad, India, 2023

Aktuelle Entwicklungen und Perspektiven (an Hochschulen) im Bereich Data Science
Author: Lena Steinmann, Dirk Nowotka, Lea Oberländer , Helen Pfuhl, Heiner Stuckenschmidt, Rolf Drechsler
Conference: INFORMATIK 2023
Reference: Berlin, Deutschland, 2023

Das Data Science Center an der Universität Bremen: Interdisziplinärer Knotenpunkt und Service-Infrastruktur für die datenintensive Forschung
Author: Lena Steinmann, Heike Thöricht, Sandra Zänkert, Rolf Drechsler
Conference: E-Science-Tage 2023
Pdf | Reference: Heidelberg, Deutschland, 2023

Data Train – The Cross-disciplinary Training in Research Data Management and Data Science
Author: Tanja Hörner, Maya Dalby, Rolf Drechsler, Frank Oliver Glöckner, Iris Pigeot
Conference: International Conference for YOUNG Marine Researchers (ICYMARE)
Reference: Oldenburg, Germany, 2023

Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style
Author: Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin Patkar, Rolf Drechsler, Farhad Merchant
Conference: International Conference on Hardware/Software Codesign and System Synthesis | Embedded System Week (CODES+ISSS)
Pdf | Reference: Hamburg, Germany, 2023

Virtual Prototypes and Open Source Hardware Design in Research and Education
Author: Sallar Ahmadi-Pour, Rolf Drechsler
Conference: The premier open source silicon conference (ORConf)
Reference: Munich, Germany, 2023

RADOPA: Robustifying a Design Against Optical Probing Attacks
Author: Sajjad Parvin, Rolf Drechsler
Conference: The premier open source silicon conference (ORConf)
Reference: Munich, Germany, 2023

RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan Networks
Author: Payam Habiby, Sebastian Huhn, Rolf Drechsler
Conference: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Reference: Juan-Les-Pins, France, 2023

Efficient ML-Based Performance Estimation Approach across Different Microarchitectures for RISC-V Processors
Author: Weiyan Zhang, Mehran Goli, Muhammad Hassan, Rolf Drechsler
Conference: Euromicro Conference Series on Digital System Design (DSD)
Pdf | Reference: Durres, Albania, 2023

Polynomial Formal Verification of KFDD Circuits
Author: Martha Schnieber, Rolf Drechsler
Conference: International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Reference: Hamburg, Germany, 2023

Next-Generation Automatic Human-Readable Proofs Enabling Polynomial Formal Verification
Author: Rolf Drechsler, Martha Schnieber
Conference: International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Reference: Hamburg, Germany, 2023

Hidden in Plain Sight: A Detailed Investigation of Selectively Increasing Local Density to Camouflage and Robustify Against Optical Probing Attacks
Author: Sajjad Parvin, Chandan Kumar Jha, Sallar Ahmadi-Pour, Frank Sill Torres, and Rolf Drechsler
Conference: IEEE International Test Conference India (ITC India)
Pdf | Reference: Bengaluru, India, 2023

Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core
Author: Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler
Conference: IEEE INTERNATIONAL CONFERENCE ON OMNI-LAYER INTELLIGENT SYSTEMS (IEEE COINS)
Pdf | Reference: Berlin, Germany, 2023

Hybrid PTX Analysis for GPU accelerated CNN inferencing aiding Computer Architecture Design
Author: Christopher Metz, Christina Plump, Bernhard J. Berger, Rolf Drechsler
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: Turin, Italy, 2023

Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models
Author: Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: Turin, Italy, 2023

Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification
Author: Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: Turin, Italy, 2023

Virtual Prototype driven Application Specific Hardware Optimization
Author: Jan Zielasko, Rolf Drechsler
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: Turin, Italy, 2023

LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing
Author: Sajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Iguazu Falls, Brazil, 2023

EvoAl: A domain-specific language-based approach to optimisation
Author: Bernhard J. Berger, Christina Plump, Rolf Drechsler
Conference: IEEE 2023 Congress on Evolutionary Computation (CEC)
Reference: Chicago, 2023

Verification of In-Memory Logic Design Using ReRAM Crossbars
Author: Kamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler
Conference: IEEE Interregional NEWCAS Conference (NEWCAS)
Pdf | Reference: Edinburgh, Scotland, 2023

Finite State Automata Design using 1T1R ReRAM Crossbar
Author: Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad Shafik, Alex Yakovlev, Sachin Patkar, Farhad Merchant
Conference: IEEE Interregional NEWCAS Conference (NEWCAS)
Pdf | Reference: Edinburgh, Scotland, 2023

Benchmarking Multiplier Architectures for MAGIC Based In-Memory Computing
Author: Chandan Kumar Jha, Rolf Drechsler
Conference: IEEE Interregional NEWCAS Conference (NEWCAS)
Pdf | Reference: Edinburgh, Scotland, 2023

Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures
Author: Abhoy Kole, Kamalika Datta, Philipp Niemann, Indranil Sengupta and Rolf Drechsler
Conference: International Conference on Reversible Computation (RC)
Pdf | Reference: Giessen, Germany, 2023

Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture
Author: Kamalika Datta, Abhoy Kole, Indranil Sengupta and Rolf Drechsler
Conference: International Conference on Reversible Computation (RC)
Pdf | Reference: Giessen, Germany, 2023

Scalable Neuroevolution of Ensemble Learners
Author: Marcel Merten, Rune Krauss, Rolf Drechsler
Conference: The Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Reference: Lisbon, Portugal, 2023

Repetitive Processes and their surrogate-model congruent encoding for evolutionary algorithms - A theoretic proposal
Author: Christina Plump, Bernhard J. Berger, Rolf Drechsler
Conference: The Genetic and Evolutionary Computation Conference (GECCO)
Reference: Lisbon, Portugal, 2023

Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes
Author: Rune Krauss, Mehran Goli, Rolf Drechsler
Conference: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Tallinn, Estonia, 2023

Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques
Author: Marcel Merten, Muhammad Hassan, Rolf Drechsler
Conference: 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Tallinn, Estonia, 2023

Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips
Author: Payam Habiby, Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich, Sebastian Huhn, Rolf Drechsler
Conference: IEEE European Test Symposium (ETS)
Pdf | Reference: Venice, Italy, 2023

Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods
Author: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference: IEEE European Test Symposium (ETS)
Pdf | Reference: Venice, Italy, 2023

VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking
Author: Ece Nur Demirhan Coskun, Muhammad Hassan, Mehran Goli, Rolf Drechsler
Conference: International Symposium on Quality Electronic Design (ISQED'23)
Pdf | Reference: San Francisco, USA, 2023

Polynomial Formal Verification of a Processor: A RISC-V Case Study
Author: Lennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler
Conference: International Symposium on Quality Electronic Design (ISQED'23)
Pdf | Reference: San Francisco, USA, 2023

Coverage-guided Fuzzing for Plan-based Robotics
Author: Tim Meywerk, Vladimir Herdt, Rolf Drechsler
Conference: 15th International Conference on Agents and Artificial Intelligence (ICAART)
Pdf | Reference: Lissabon, Portugal, 2023

Polynomial Formal Verification of Floating Point Adders
Author: Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2023

Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors
Author: Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed E. Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, Violetta Sessi, Maximilian Drescher, Sabine Kolodinski and Maciej Wiatr
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2023

Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex Circuits
Author: Rolf Drechsler, Alireza Mahzoon
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2023

Processor Verification using Symbolic Execution: A RISC-V Case-Study
Author: Niklas Bruns, Vladimir Herdt, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2023

Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits
Author: Kemal Çağlar Coşkun, Muhammad Hassan, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2023

FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing
Author: Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2023

Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network
Author: Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2023

Automated Equivalence Checking Method for Majority based In-Memory Computing on ReRAM Crossbars
Author: Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Tokyo, Japan, 2023

Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - a RISC-V Case Study
Author: Sajjad Parvin, Mehran Goli, Frank Sill Torres, and Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Tokyo, Japan, 2023

EDDY: A Multi-Core BDD Package With Dynamic Memory Management and Reduced Fragmentation
Author: Rune Krauss, Mehran Goli, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Tokyo, Japan, 2023

A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS
Author: Muhammad Hassan, Thilo Vörtler, Karsten Einwich, Rolf Drechsler, Daniel Große
Conference: Design and Verification Conference in Europe (DVCon Europe)
Pdf | Reference: Munich, Germany, 2022

Symbolic Fault Injection for Plan-based Robotics
Author: Tim Meywerk, Vladimir Herdt, Rolf Drechsler
Conference: The 22nd International Conference on Control, Automation and Systems (ICCAS)
Pdf | Reference: Busan, Korea, 2022

Investigating Various Adder Architectures for Digital In-Memory Computing Using MAGIC-based Memristor Design Style
Author: Chandan Kumar Jha, Alireza Mahzoon, Rolf Drechsler
Conference: International Conference on Emerging Electronics (ICEE)
Pdf | Reference: Bangalore, India, 2022

Monitoring the Effects of Static Variable Orders on the Construction of BDDs
Author: Khushboo Qayyum, Alireza Mahzoon, Rolf Drechsler
Conference: International Interdisciplinary Conference on Mathematics, Engineering and Science (MESIICON)
Pdf | Reference: Virtual Conference, 2022

Polynomial Formal Verification: Ensuring Correctness under Resource Constraints
Author: Rolf Drechsler, Alireza Mahzoon
Conference: International Conference on Computer Aided Design (ICCAD)
Pdf | Reference: San Diego, USA, 2022

Divider Verification Using Symbolic Computer Algebra and Delayed Don’t Care Optimization
Author: Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler
Conference: Formal Methods in Computer-Aided Design (FMCAD)
Pdf | Reference: Trento, Italy, 2022

Preserving Design Hierarchy Information for Polynomial Formal Verification
Author: Rolf Drechsler, Alireza Mahzoon
Conference: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Pdf | Reference: Patras, Greece, 2022

Fast and Exact is Doable: Polynomial Algorithms in Test and Verification
Author: Rolf Drechsler
Conference: IEEE Latin-American Test Symposium (LATS)
Pdf | Reference: Virtual Conference, 2022

Design Modification for Polynomial Formal Verification
Author: Rolf Drechsler, Alireza Mahzoon
Conference: 2022 International Symposium on Electrical, Electronics and Information Engineering (ISEEIE)
Pdf | Reference: Virtual Conference, 2022

Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency Scaling
Author: Christopher Metz, Mehran Goli, Rolf Drechsler
Conference: ACM/IEEE Workshop on Machine Learning for CAD (MLCAD)
Pdf | Reference: Snowbird, USA, 2022

Next Generation Design For Testability, Debug and Reliability Using Formal Techniques
Author: Sebastian Huhn and Rolf Drechsler
Conference: International Test Conference (ITC)
Pdf | Reference: Anaheim, CA, USA, 2022

Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device
Author: Alexander Fratzer, Vladimir Herdt, Christoph Lüth, Rolf Drechsler
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: Linz, Austria, 2022

Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification
Author: Niklas Bruns, Vladimir Herdt, Rolf Drechsler
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: Linz, Austria, 2022

3D Visualization of Symbolic Execution Traces
Author: Jan Zielasko, Sören Tempel, Vladimir Herdt, Rolf Drechsler
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: Linz, Austria, 2022

SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification
Author: Sören Tempel, Vladimir Herdt and Rolf Drechsler
Conference: Automated Technology for Verification and Analysis (ATVA)
Pdf | Reference: Beijing, China, 2022

Simulation-Based Debugging of Formal Environment Models
Author: Tim Meywerk, Arthur Niedzwiecki, Vladimir Herdt and Rolf Drechsler
Conference: The 30th Mediterranean Conference on Control and Automation (MED)
Pdf | Reference: Athen, Griechenland, 2022

AQuCiDe: Architecture Aware Quantum Circuit Decomposition
Author: Soumya Sengupta, Abhoy Kole, Kamalika Datta, Indranil Sengupta and Rolf Drechsler
Conference: 2022 International Symposium on Quantum Computing: Circuits Systems Automation and Applications (QC-CSAA)
Pdf | Reference: Knoxville, USA, 2022

Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study
Author: Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler and Klaus McDonald-Maier
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Gran Canaria, Spain, 2022

Generation of Verified Programs for In-Memory Computing
Author: Saman Froehlich and Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Gran Canaria, Spain, 2022

Polynomial Formal Verification of Approximate Adders
Author: Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Gran Canaria, Spain, 2022

SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library
Author: Abhoy Kole, Kamalika Datta, Indranil Sengupta and Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Gran Canaria, Spain, 2022

Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles
Author: Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta and Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Gran Canaria, Spain, 2022

Polynomial Formal Verification of Approximate Functions
Author: Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Pafos, Cyprus, 2022

Using density of training data to improve evolutionary algorithms with approximative fitness functions
Author: Christina Plump, Bernhard J. Berger, Rolf Drechsler
Conference: Congress of Evolutionary Computation (CEC)
Pdf | Reference: Padua, Italien, 2022

Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype
Author: Pascal Pieper, Vladimir Herdt, Rolf Drechsler
Conference: Great Lakes Symposium on VLSI (GLSVLSI)
Reference: Irvine, CA, USA, 2022

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
Author: Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: Irvine, CA, USA, 2022

Adapting mutation and recombination operators to range-aware relations in real-world application data
Author: Christina Plump, Bernhard J. Berger, Rolf Drechsler
Conference: The Genetic and Evolutionary Computation Conference (GECCO Companion)
Reference: Boston, USA, 2022

Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal Qubit Architecture
Author: Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler
Conference: IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Virtual Conference, Dallas, 2022

Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic
Author: Philipp Niemann, Rolf Drechsler
Conference: IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Dallas, USA, 2022

Formal Verification of Modular Multipliers using Symbolic Computer Algebra and Boolean Satisfiability
Author: Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2022

Verifying SystemC TLM Peripherals using Modern C++ Symbolic Execution Tools
Author: Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2022

Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters
Author: Kemal Çağlar Coşkun, Muhammad Hassan, Rolf Drechsler
Conference: 25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Prague, Czech Republic, 2022

Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression
Author: Weiyan Zhang, Mehran Goli, Rolf Drechsler
Conference: 25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Prague, Czech Republic, 2022

Towards Polynomial Formal Verification of Complex Arithmetic Circuits
Author: Rolf Drechsler, Alireza Mahzoon, Mehran Goli
Conference: 25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Prague, Czech Republic, 2022

Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions
Author: Milan Funck, Vladimir Herdt, Rolf Drechsler
Conference: 25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Prague, Czech Republic, 2022

ML-based Power Estimation of Convolutional Neural Networks on GPGPUs
Author: Christopher Metz, Mehran Goli, Rolf Drechsler
Conference: 25th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Prague, Czech Republic, 2022

Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods
Author: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference: IEEE European Test Symposium (ETS)
Pdf | Reference: Barcelona, Spain, 2022

Choosing the right technique for the right restriction - a domain-specific approach for enforcing search-space restrictions in evolutionary algorithms
Author: Christina Plump, Bernhard Berger, Rolf Drechsler
Conference: LDIC-2022
Pdf | Reference: Bremen, Germany

A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection
Author: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference: 40th IEEE VLSI Test Symposium (VTS)
Pdf | Reference: San Diego, USA, 2022

The Scale4Edge RISC-V Ecosystem
Author: Wolfgang Ecker, Milos Krstic, Andreas Mauderer, Eyck Jentzsch, Mihaela Damian, Julian Oppermann, Andreas Koch, Peer Adelt, Wolfgang Müller, Vladimir Herdt, Rolf Drechsler, Rafael Stahl, Karsten Emrich, Daniel Müller-Gritschneder, Jan Schlamelcher, Kim Grüttner, Jörg Bormann, Wolfgang Kunz, Reinhold Heckmann, Gerhard Angst, Ralf Wimmer, Bernd Becker, Philipp Scholl, Paul Palomero Bernardo, Oliver Bringmann, Johannes Partzsch, Christian Mayr
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2022

Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
Author: Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2022

LiM-HDL: HDL-Based Synthesis for In-Memory Computing
Author: Saman Fröhlich, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Antwerp, Belgium, 2022

Polynomial Formal Verification of Arithmetic Circuits
Author: Rolf Drechsler, Alireza Mahzoon, Lennart Weingarten
Conference: International Conference on Computational Intelligence and Data Engineering (ICCIDE)
Pdf | Reference: Vijayawada, India, 2021

Polynomial Word-Level Verification of Arithmetic Circuits
Author: Mohammed Barhoush, Alireza Mahzoon, Rolf Drechsler
Conference: International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Reference: Beijing, China, 2021

Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques
Author: Sajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres and Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Taipei, Taiwan, 2022

Automated Detection of Spatial Memory Safety Violations for Constrained Devices
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Taipei, Taiwan, 2022

Modeling for Explainability: Ethical Decision-Making in Automated Resource Allocation
Author: Christina Cociancig, Christoph Lüth, Rolf Drechsler
Conference: Upper-Rhine Artificial Intelligence Symposium (UR-AI 2021)
Pdf | Reference: Kaiserslautern, Germany, 2021

Polynomial Formal Verification of Prefix Adders
Author: Alireza Mahzoon, Rolf Drechsler
Conference: Asian Test Symposium (ATS)
Pdf | Reference: Virtual Conference, Japan, 2021

A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks
Author: Marcel Merten, Sebastian Huhn, Rolf Drechsler
Conference: 34th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Reference: Athens, Greece, 2021

Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs
Author: Mehran Goli, Rolf Drechsler
Conference: International Conference on Computer Aided Design (ICCAD)
Pdf | Reference: Munich, Germany, 2021

Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level
Author: Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Pdf | Reference: Virtual Conference, Singapore, 2021

RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems
Author: Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: Antibes, France, 2021

VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes
Author: Mehran Goli, Rolf Drechsler
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: Antibes, France, 2021
Best Paper Award

In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: Antibes, France, 2021

Work-in-Progress: Early Power Estimation of CUDA-based CNNs on GPGPUs
Author: Christopher Metz, Mehran Goli, Rolf Drechsler
Conference: International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
Pdf | Reference: VIRTUAL CONFERENCE, 2021

Minimally Invasive HW/SW Co-debug Live Visualization on Architecture Level
Author: Pascal Pieper, Ralf Wimmer, Gerhard Angst, Rolf Drechsler
Conference: 31st ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: Virtual Conference, 2021

Finding Optimal Implementations of Non-native CNOT Gates using SAT
Author: Philipp Niemann, Luca Müller, Rolf Drechsler
Conference: Reversible Computation (RC)
Pdf | Reference: Nagoya, Japan, 2021

Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation
Author: Philipp Niemann, Luca Müller, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Palermo, Sicily, Italy, 2021

Automated Debugging-Aware Visualization Technique for SystemC HLS Designs
Author: Mehran Goli, Alireza Mahzoon, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Palermo, Sicily, Italy, 2021

ALF – A Fitness-Based Artificial Life Form for Evolving Large-Scale Neural Networks
Author: Rune Krauss, Marcel Merten, Mirco Bockholt, Rolf Drechsler
Conference: The Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Reference: Lille, France, 2021

Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability
Author: Payam Habiby, Sebastian Huhn, Rolf Drechsler
Conference: 28th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
Pdf | Reference: Apulia, Italy, 2021

Synthesis of Asymptotically Optimal Adders for Multiple-Valued Logic
Author: Philipp Niemann, Rolf Drechsler
Conference: 51st International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Video | Reference: Nursultan, Kazakhstan, 2021

Depth Optimized Synthesis of Symmetric Boolean Functions
Author: Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Tampa, Florida, USA, 2021

Domain-driven correlation-aware recombination and mutation operators for complex real-world applications
Author: Christina Plump, Bernhard J. Berger, Rolf Drechsler
Conference: IEEE Congress on Evolutionary Computation (CEC)
Pdf | Reference: Kraków, Poland, 2021

Improving evolutionary algorithms by enhancing an approximative fitness function through prediction intervals
Author: Christina Plump, Bernhard J. Berger, Rolf Drechsler
Conference: IEEE Congress on Evolutionary Computation (CEC)
Pdf | Reference: Krakow, Poland, 2021

PolyAdd: Polynomial Formal Verification of Adder Circuits
Author: Rolf Drechsler
Conference: 24th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Vienna, Austria, 2021

Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2021

Late Breaking Results: Polynomial Formal Verification of Fast Adders
Author: Alireza Mahzoon, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2021

XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding
Author: Lucas Klemmer, Saman Fröhlich, Rolf Drechsler, Daniel Große
Conference: IEEE International Symposium on Circuits & Systems (ISCAS)
Pdf | Reference: Daegu, Korea, 2021

Performance Aspects of Correctness-oriented Synthesis Flows
Author: Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Conference: Int’l Conf. on Model-Driven Engineering and Software Development (MODELSWARD)
Pdf | Reference: 2021

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?
Author: Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Grenoble, France, 2021

Nano Security: From Nano-Electronics to Secure Systems
Author: Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Grenoble, France, 2021

Combining SWAPs and Remote Toffoli Gates in the Mapping to IBM QX Architectures
Author: Philipp Niemann, Chandan Bandyopadhyay, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Grenoble, France, 2021

Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization
Author: Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Grenoble, France, 2021

An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Grenoble, France, 2021

System Level verification of Phase-Locked Loop using Metamorphic Relations
Author: Muhammad Hassan, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe Conference (DATE)
Pdf | Reference: Grenoble, France, 2021

ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs
Author: Mehran Goli, Rolf Drechsler
Conference: 26th Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Tokyo, Japan, 2021

One-pass Synthesis for Field-coupled Nanocomputing Technologies
Author: Marcel Walter, Winston Haaswijk, Robert Wille, Frank Sill Torres, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Tokyo, Japan, 2021
Best Paper Candidate

System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations
Author: Muhammad Hassan, Daniel Große, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Tokyo, Japan, 2021

Mutation-based Compliance Testing for RISC-V
Author: Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Tokyo, Japan, 2021

Clustering-Guided SMT(LRA) Learning
Author: Tim Meywerk, Marcel Walter, Daniel Große, Rolf Drechsler
Conference: International Conference on integrated Formal Methods (iFM)
Pdf | Reference: Lugano, Switzerland, 2020

Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime
Author: Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler
Conference: 38th IEEE International Conference on Computer Design (ICCD)
Pdf | Reference: Hartford, USA, 2020

ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique
Author: Mehran Goli, Alireza Mahzoon, Rolf Drechsler
Conference: 38th IEEE International Conference on Computer Design (ICCD)
Pdf | Reference: Hartford, USA, 2020

Verifying Safety Properties of Robotic Plans operating in Real-World Environments via Logic-based Environment Modeling
Author: Tim Meywerk, Marcel Walter, Vladimir Herdt, Jan Kleinekathöfer, Daniel Große, Rolf Drechsler
Conference: 9th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation (ISoLA)
Pdf | Reference: Rhodes, Greece, 2020

Power-aware Test Scheduling for IEEE 1687 Networks with Multiple Power Domains
Author: Payam Habiby, Sebastian Huhn, Rolf Drechsler
Conference: 33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Reference: Frascati (Rome), Italy, 2020

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
Author: Vladimir Herdt, Daniel Große, Eyck Jentzsch, Rolf Drechsler
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: Kiel, Germany, 2020
Best Paper Award

RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms
Author: Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference: Automated Technology for Verification and Analysis (ATVA)
Pdf | Reference: Hanoi, Vietnam, 2020

ToPoliNano and fiction: Design Tools for Field-coupled Nanocomputing
Author: Umberto Garlando, Marcel Walter, Robert Wille, Fabrizio Riente, Frank Sill Torres, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Portorož, Slowenien, 2020

Design Space Exploration in the Mapping of Reversible Circuits to IBM Quantum Computers
Author: Philipp Niemann, Alexandre A. A. de Almeida, Gerhard Dueck, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Portorož, Slowenien, 2020

Combining Machine Learning and Formal Techniques for Small Data Applications - A Framework to Explore New Structural Materials
Author: Rolf Drechsler, Sebastian Huhn, Christina Plump
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Portorož, Slowenien, 2020

Post Synthesis-Optimization of Reversible Circuit using Template Matching
Author: Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference: In 2020 24th International Symposium on VLSI Design and Test (VDAT)
Pdf | Reference: pp. 1-4. IEEE, 2020, DOI: 10.1109/VDAT50263.2020.9190279

Design Automation for Field-coupled Nanotechnologies
Author: Marcel Walter, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Limassol, Cyprus, 2020
Best Student Forum Paper Award

Efficient Techniques to Strongly Enhance the Virtual Prototype based Design Flow
Author: Vladimir Herdt, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Limassol, Cyprus, 2020

Automated Design Understanding of SystemC-based Virtual Prototypes: Data Extraction, Analysis and Visualization
Author: Mehran Goli, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Limassol, Cyprus, 2020

Bail on Balancing: An Alternative Approach to the Physical Design of Field-coupled Nanocomputing Circuits
Author: Marcel Walter, Robert Wille, Frank Sill Torres, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Limassol, Cyprus, 2020
Best Paper Candidate

Towards Generation of a Programmable Power Management Unit at the Electronic System Level
Author: David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
Conference: 23rd IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Novi Sad, Serbia, 2020

Impacts of Block-based Programming on Young Learners' Programming Skills and Attitudes in the Context of Smart Environments
Author: Mazyar Seraj, Rolf Drechsler
Conference: The 25th ACM annual conference on Innovation and Technology in Computer Science Education (ITiCSE)
Reference: Trondheim, Norway, 2020

Efficient Machine Learning through Evolving Combined Deep Neural Networks
Author: Rune Krauss, Marcel Merten, Mirco Bockholt, Saman Fröhlich, Rolf Drechsler
Conference: Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Reference: Electronic-only, 2020

Early Verification of ISA Extension Specifications Using Deep Reinforcement Learning
Author: Niklas Bruns, Daniel Große, Rolf Drechsler
Conference: 30th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: Beijing, China, 2020

Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes
Author: Vladimir Herdt, Daniel Große, Jonas Wloka, Tim Güneysu, Rolf Drechsler
Conference: 30th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: Beijing, China, 2020

Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side
Author: Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2020

Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes
Author: Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2020

Verification for Field-coupled Nanocomputing Circuits
Author: Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: San Francisco, USA, 2020

Efficient Implementation of Nearest Neighbor Quantum Circuits Using Clustering with Genetic Algorithm
Author: Anirban Bhattacharjee, Chandan Bandyopadhyay, Angshu Mukherjee, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference: 50th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Miyazaki, Japan, 2020

ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks
Author: Saman Fröhlich, Lucas Klemmer, Daniel Große, Rolf Drechsler
Conference: 50th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Miyazaki, Japan, 2020

Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars
Author: Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
Conference: IEEE International Symposium on Circuits & Systems (ISCAS)
Pdf | Reference: Sevilla, Spain, 2020

Impacts of Creating Smart Everyday Objects on Young Female Students' Programming Skills and Attitudes
Author: Mazyar Seraj, Eva-Sophie Katterfeldt, Serge Autexier, Rolf Drechsler
Conference: The 51st ACM Technical Symposium on Computer Science Education (SIGCSE)
Pdf | Reference: Portland, Oregon, USA, 2020

Towards Specification and Testing of RISC-V ISA Compliance
Author: Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Grenoble, France, 2020

Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes
Author: Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Grenoble, France, 2020

Towards Formal Verification of Optimized and Industrial Multipliers
Author: Alireza Mahzoon, Daniel Große, Christoph Scholl, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Grenoble, France, 2020

Integer Overflow Detection in Hardware Designs at the Specification Level
Author: Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Conference: 8th International Conference on Model-Driven Engineering and Software Development (MODELSWARD)
Pdf | Reference: Valetta, Malta, 2020

Towards Automatic Hardware Synthesis from Formal Specification to Implementation
Author: Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Beijing, China, 2020

Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems
Author: Rolf Drechsler, Daniel Große
Conference: Asian Test Symposium (ATS)
Pdf | Reference: Kolkata, India, 2019

Scratch and Google Blockly: How Girls’ Programming Skills and Attitudes are Influenced
Author: Mazyar Seraj, Eva-Sophie Katterfeldt, Kerstin Bub, Serge Autexier, Rolf Drechsler
Conference: The 19th Koli Calling International Conference on Computing Education Research (Koli Calling)
Pdf | Reference: Koli, Finland, 2019

A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems
Author: Sebastian Huhn, Daniel Tille, Rolf Drechsler
Conference: International Test Conference in Asia (ITC-Asia)
Pdf | Reference: Tokyo, Japan, 2019

Functional Coverage-Driven Characterization of RF Amplifiers
Author: Muhammad Hassan, Daniel Große, Thilo Vörtler, Karsten Einwich and Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: Southampton, United Kingdom, 2019
Best Paper Candidate

Systematic RISC-V based Firmware Design
Author: Vladimir Herdt, Daniel Große, Rolf Drechsler, Christoph Gerum, Alexander Jung, Joscha-Joel Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: Southampton, United Kingdom, 2019

SAT-Hard: A Learning-based Hardware SAT-Solver
Author: Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Große and Rolf Drechsler
Conference: EUROMICRO Digital System Design Conference (DSD)
Pdf | Reference: Kallithea - Chalkidiki, Greece, 2019

Towards Formal Verification of Plans for Cognition-enabled Autonomous Robotic Agents
Author: Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference: EUROMICRO Digital System Design Conference (DSD)
Pdf | Reference: Kallithea - Chalkidiki, Greece, 2019

Scalable Simulation-based Verification of SystemC-based Virtual Prototypes
Author: Mehran Goli, Rolf Drechsler
Conference: EUROMICRO Digital System Design Conference (DSD)
Pdf | Reference: Kallithea - Chalkidiki, Greece, 2019

Code is Ethics —Formal Techniques for a Better World
Author: Rolf Drechsler, Christoph Lüth
Conference: EUROMICRO Digital System Design Conference (DSD)
Pdf | Reference: Kallithea - Chalkidiki, Greece, 2019

Property-driven Timestamps Encoding for Timeprints-based Tracing and Monitoring
Author: Rehab Massoud, Hoang M. Le, Rolf Drechsler
Conference: 17th International Conference on Formal Modeling and Analysis of Timed Systems, (FORMATS)
Pdf | Reference: Amsterdam, Netherlands, 27-29 August, 2019

Temporal Tracing of On-Chip Signals using Timeprints
Author: Rehab Massoud, Hoang M. Le, Peter Chini, Prakash Saivasan, Roland Meyer and Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: Las Vegas, USA, 2019

RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers
Author: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: Las Vegas, USA, 2019

Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study
Author: Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: Las Vegas, USA, 2019

ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing
Author: Steffen Frerix, Saeideh Shirinzadeh, Saman Fröhlich, Rolf Drechsler
Conference: International Symposium on Nanoscale Architectures (NanoArch 2019)
Pdf | Reference: Qingdao, China, 2019

Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits
Author: Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Miami, Florida, USA, 2019

Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-coupled Nanotechnologies
Author: Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Miami, Florida, USA, 2019

Improved Look-ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits
Author: Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler and Hafizur Rahaman
Conference: International Conference on VLSI Design (VLSI Design)
Pdf | Reference: Florida, USA, 2019

Smart Homes Programming: Development and Evaluation of an Educational Programming Application for Young Learners
Author: Mazyar Seraj, Cornelia Große, Serge Autexier, Rolf Drechsler
Conference: The 18th ACM International Conference on Interaction Design and Children (IDC)
Pdf | Reference: Boise, Idaho, USA, 2019

Automated Analysis of Virtual Prototypes at Electronic System Level
Author: Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
Conference: 29th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: Washington, D.C., USA, 2019

Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns
Author: Sebastian Huhn, Daniel Tille, Rolf Drechsler
Conference: IEEE European Test Symposium (ETS)
Pdf | Reference: Baden Baden, Germany, 2019

Machine Learning-based Prediction of Test Power
Author: Harshad Dhotre, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
Conference: IEEE European Test Symposium (ETS)
Pdf | Reference: Baden Baden, Germany, 2019

HotAging - Impact of Power Dissipation on Hardware Degradation
Author: Frank Sill Torres, Alberto Garcia Ortiz and Rolf Drechsler
Conference: IEEE International Symposium on Circuits and Systems (ISCAS)
Pdf | Reference: Sapporo, Japan, 2019.

Look What I Can Do: Acquisition of Programming Skills in the Context of Living Labs
Author: Mazyar Seraj, Cornelia Große, Serge Autexier, Rolf Drechsler
Conference: The IEEE/ACM 41st International Conference on Software Engineering: Software Engineering Education and Training (ICSE-SEET)
Pdf | Reference: Montréal, QC, Canada, 2019

T-Depth Optimization for Fault-Tolerant Quantum Circuits
Author: Philipp Niemann, Anshu Gupta, Rolf Drechsler
Conference: 49th IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Fredericton, NB, Canada, 2019

One Additional Qubit is Enough: Encoded Embeddings for Boolean Components in Quantum Circuits
Author: Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille
Conference: 49th IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Fredericton, NB, Canada, 2019

(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-based Countermeasures on FPGAs
Author: Kenneth Schmitz, Buse Ustaoglu, Daniel Große, Rolf Drechsler
Conference: International Symposium on Applied Reconfigurable Computing (ARC)
Pdf | Reference: Darmstadt, Germany, 2019

Impact of NBTI on Increasing the Susceptibility of FinFET to Radiation
Author: Frank Sill Torres, Hussam Amrouch, Jörg Henkel and Rolf Drechsler
Conference: IEEE International Reliability Physics Symposium (IRPS 2019)
Pdf | Reference: Monterey, California, USA, March 31 - April 4, 2019

Accuracy and Compactness in Decision Diagrams for Quantum Computation
Author: Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Florence, Italy, 2019

One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing
Author: Saman Fröhlich, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Florence, Italy, 2019

Verifying Instruction Set Simulators using Coverage-guided Fuzzing
Author: Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Florence, Italy, 2019

Data Flow Testing for SystemC-AMS Timed Data Flow Models
Author: Muhammad Hassan, Daniel Große, Hoang M. Le, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Florence, Italy, 2019

Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing
Author: Hoang M. Le, Daniel Große, Niklas Bruns, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Florence, Italy, 2019

Better Late Than Never: Verification of Embedded Systems After Deployment
Author: Martin Ring, Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Florence, Italy, 2019

Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements
Author: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Conference: 20th IEEE Latin American Test Symposium (LATS)
Pdf | Reference: Santiago, Chile, 2019

Scalable Design for Field-coupled Nanocomputing Circuits
Author: Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Tokyo, Japan, 2019

Maximizing Power State Cross Coverage in Firmware-based Power Management
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference: 24th Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Tokyo, Japan, 2019

PolyCleaner: Clean your Polynomials before Backward Rewriting to Verify Million-gate Multipliers
Author: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Conference: International Conference on Computer Aided Design (ICCAD)
Pdf | Reference: San Diego, USA, 2018
Best Paper Award

IC/IP Piracy Assessment of Reversible Logic
Author: Samah Mohamed Saeed, Xiaotong Cui, Alwin Zulehner,, Robert Wille, Rolf Drechsler, Kaijie Wu, Ramesh Karri
Conference: International Conference on Computer-Aided Design (ICCAD)
Pdf | Reference: San Diego, 2018

Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters
Author: David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
Conference: IEEE Nordic Circuits and Systems Conference (NORCAS)
Pdf | Reference: Tallinn, Estonia, 2018

Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques
Author: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference: IEEE International Symposium on Rapid System Prototyping (RSP), 2018
Pdf | Reference: Torino, Italy, 2018

Multi-Objective Synthesis of Quantum Circuits Using Genetic Programming
Author: Moein Sarvaghad-Moghaddam, Philipp Niemann, Rolf Drechsler
Conference: Reversible Computation
Pdf | Reference: pp. 220-227, Leicester, UK, 2018

Extensible and Configurable RISC-V based Virtual Prototype
Author: Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: Munich, Germany, 2018

Automatic Design of Microfluidic Devices: An Overview of Platforms and Corresponding Design Tasks
Author: Robert Wille, Bing Li, Rolf Drechsler and Ulf Schlichtmann
Conference: In Forum on specification & Design Languages (FDL), München, 2018
Pdf | Reference:

Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata
Author: Frank Sill Torres, Pedro A. Silva, Geraldo Fontes, José Augusto M. Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Prague, Czech Republic, 2018

Towards Self-explaining Intelligent Environments
Author: Serge Autexier, Rolf Drechsler
Conference: International Converence on Reliability, Infocom Technologies and Optimization (ICRITO)
Pdf | Reference: Noida, India, 2018

Towards Reversed Approximate Hardware Design
Author: Saman Fröhlich, Daniel Große, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Prague, Czech Republic, 2018

Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata
Author: Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Große, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: pp. 649-656, Prague, Czech Republic, 2018

Synchronization of Clocked Field-Coupled Circuits
Author: Frank Sill Torres, Marcel Walter, Robert Wille, Daniel Große, Rolf Drechsler
Conference: IEEE International Conference on Nanotechnology (Nano)
Pdf | Reference: Cork, Ireland, 2018

Logic Synthesis for In-Memory Computing using Resistive Memories
Author: Saeideh Shirinzadeh, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Hong Kong SAR, China, 2018

A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits
Author: Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Hong Kong SAR, China, 2018

Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers
Author: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: pp. 351-356, Hong Kong SAR, China, 2018

Towards Dynamic Execution Environment for System Security Protection against Hardware Flaws
Author: Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: pp. 557-562, Hong Kong SAR, China, 2018

Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling
Author: Robert Schmidt, Rehab Massoud, Jaan Raik, Alberto Garcia-Ortiz, Rolf Drechsler
Conference: 24th IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)
Pdf | Reference: Costa Brava, Spain, 2018

Natural Language based Power Domain Partitioning
Author: David Lemma, Daniel Große, Rolf Drechsler
Conference: 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: pp. 101-106, Budapest, Hungary, 2018

Constraint-based Pattern Retargeting for Reducing Localized Power Activity during Testing
Author: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen
Conference: 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Budapest, Hungary, 2018

SAT-Lancer: A Hardware SAT-Solver for Self-Verification
Author: Buse Ustaoglu, Sebastian Huhn, Daniel Große, Rolf Drechsler
Conference: 28th ACM Great Lakes Symposium on VLSI (GLVLSI)
Pdf | Reference: pp. 479-482, Chicago, Illinois, USA, 2018
Received Best Poster Award

Synthesis of Reversible Circuits Using Conventional Hardware Description Languages
Author: Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference: IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Linz, Austria, 2018

Logic Design using Memristors: An Emerging Technology
Author: Saeideh Shirinzadeh, Kamalika Datta, Rolf Drechsler
Conference: IEEE International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Linz, Austria, 2018

Building Fast Multi-Agent Systems using Hardware Design Languages for High-Throughput Systems
Author: Jannis Stoppe, Christina Plump, Sebastian Huhn, Rolf Drechsler
Conference: 6th International Conference on Dynamics in Logistics (LDIC)
Pdf | Reference: Bremen, Germany, 2018

Improved Synthesis of Clifford+T Quantum Functionality
Author: Philipp Niemann, Robert Wille, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 597-600, Dresden, Germany, 2018

Resiliency Evaluation via Symbolic Fault Injection on Intermediate Code
Author: Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 845-850, Dresden, Germany, 2018

Towards Fully Automated TLM-to-RTL Property Refinement
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1508-1511, Dresden, Germany, 2018

Testbench Qualification for SystemC-AMS Timed Data Flow Models
Author: Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 857-860, Dresden, Germany, 2018

Approximate Hardware Generation using Symbolic Computer Algebra employing Gröbner Basis
Author: Saman Fröhlich, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 889-892, Dresden, Germany, 2018

An Exact Method for Design Exploration of Quantum-dot Cellular Automata
Author: Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 503-508, Dresden, Germany, 2018

Analyzing Frame Conditions in UML/OCL Models: Consistency, Equivalence, and Independence
Author: Philipp Niemann, Nils Przigoda, Robert Wille, Rolf Drechsler
Conference: 6th International Conference on Model-Driven Engineering and Software Development (MODELSWARD)
Pdf | Reference: pp. 139-151, Funchal, Portugal, 2018

Approximation-aware Testing for Approximate Circuits
Author: Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler
Conference: 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: pp. 239 - 244, Jeju, Korea, 2018

Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips
Author: Oliver Keszöcze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Conference: International Conference on VLSI Design (VLSID)
Pdf | Reference: Pune, Indien, 2018

Revealing Properties of Structural Materials by Combining Regression-based Algorithms and Nano Indentation Measurements
Author: Sebastian Huhn, Heike Sonnenberg, Stephan Eggersglüß, Brigitte Clausen, Rolf Drechsler
Conference: 10th IEEE Symposium Series on Computational Intelligence (SSCI)
Pdf | Reference: Hawaii, USA, 2017

Towards Lightweight Satisfiability Solvers for Self-Verification
Author: Fritjof Bornebusch, Robert Wille, Rolf Drechsler
Conference: 7th International Symposium on Embedded Computing and System Design (ISED)
Pdf | Reference: Durgapur, Indien, 2017

Verifying Next Generation Electronic Systems
Author: Rolf Drechsler, Daniel Große
Conference: International Conference on Infocom Technologies and Unmanned Systems (ICTUS)
Pdf | Reference: pp. 6 - 10, Dubai, United Arab Emirates, 2017

Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata
Author: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference: 35th IEEE International Conference on Computer Design (ICCD)
Pdf | Reference: Boston Area, Massachusetts, USA, 2017

Identification of Efficient Clustering Techniques for Test Power Activity on the Layout
Author: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Conference: 26th IEEE Asian Test Symposium (ATS)
Pdf | Reference: Taipei, Taiwan, 2017

More than true or false: Native Support of Irregular Values in the Automatic Validation & Verification of UML/OCL Models
Author: Nils Przigoda, Philipp Niemann, Judith Peters, Frank Hilken, Robert Wille, Rolf Drechsler
Conference: 15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Reference: pp. 77-86, Vienna, Austria, 2017

Yise - A novel Framework for Boolean Networks using Y-Inverter Graphs
Author: Arun Chandrasekharan, Daniel Große, Rolf Drechsler
Conference: 15th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Reference: pp. 114-117, Vienna, Austria, 2017

Reconfigurable TAP Controllers with Embedded Compression for Large Test Data Volume
Author: Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler
Conference: 30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Reference: Cambridge, UK, 2017

Machine Learning Based Test Pattern Analysis for Localizing Critical Power Activity Areas
Author: Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler
Conference: 30th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Reference: Cambridge, UK, 2017

Unintrusive Aging Analysis based on Offline Learning
Author: Frank Sill Torres, Pedro F. R. Leite Junior and Rolf Drechsler
Conference: 30th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Pdf | Reference: Cambridge, UK, 2017

Towards Early Validation of Firmware-Based Power Management using Virtual Prototypes: A Constrained Random Approach
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: pp. 1-8, Verona, Italy, 2017
Best Paper Candidate

Semi-Formal Cycle-Accurate Temporal Execution Traces Reconstruction
Author: Rehab Massoud, Jannis Stoppe, Daniel Große, Rolf Drechsler
Conference: 15th International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS)
Pdf | Reference: pp. 335-351, Berlin, Germany, 2017

Early SoC Security Validation by VP-based Static Information Flow Analysis
Author: Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference: International Conference on Computer Aided Design (ICCAD)
Pdf | Reference: pp. 400-407, Irvine, USA, 2017

Dedicated Synthesis for MZI-based Optical Circuits based on AND-Inverter Graphs
Author: Arighna Deb, Robert Wille, Rolf Drechsler
Conference: International Conference on Computer Aided Design (ICCAD)
Pdf | Reference: Irvine, USA, 2017

Self-practicing of logic circuits through mobile devices: Lecturers' and students' perceptions
Author: Mazyar Seraj, Cornelia Große, Rolf Drechsler
Conference: The 9th annual International Conference on Education and New Learning Technologies (EduLearn17)
Pdf | Reference: Barcelona, Spain, 2017

BioViz: An Interactive Visualization Engine for Digital Microfluidic Biochips
Author: Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Bochum, Germany, 2017

Towards VHDL-based Design of Reversible Circuits
Author: Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference: Reversible Computation
Pdf | Reference: Kolkata, India, 2017

Efficient Construction of QMDDs for Irreversible, Reversible and Quantum Functions
Author: Philipp Niemann, Alwin Zulehner, Robert Wille, Rolf Drechsler
Conference: Reversible Computation
Pdf | Reference: pp. 214-231, Kolkata, India, 2017

An Adaptive Prioritized ε-Preferred Evolutionary Algorithm for Approximate BDD Optimization
Author: Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference: Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Reference: Berlin, Germany, 2017

ProACt: A Processor for High Performance On-demand Approximate Computing
Author: Arun Chandrasekharan, Daniel Große, Rolf Drechsler
Conference: 27th ACM Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: pp. 463-466, Banff, Alberta, Canada, 2017

OR-Inverter Graphs for the Synthesis of Optical Circuits
Author: Arighna Deb, Robert Wille, Rolf Drechsler
Conference: 47th International Symposium on Multiple-Valued Logic (ISMVL)
Reference: Novi Sad, Serbia, 2017

Extensions to the Reversible Hardware Description Language SyReC
Author: Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference: 47th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Novi Sad, Serbia, 2017

Error Bounded Exact BDD Minimization in Approximate Computing
Author: Saman Fröhlich, Daniel Große, Rolf Drechsler
Conference: 47th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: pp. 254-259, Novi Sad, Serbia, 2017

Exact Synthesis of Ternary Reversible Functions using Ternary Toffoli Gates
Author: Abhoy Kole, P. Mercy Nesa Rani, Kamalika Datta, Indranil Sengupta, Rolf Drechsler
Conference: 47th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Novi Sad, Serbia, 2017

Effects of Cell Shapes on the Routability of Digital Microfluidic Biochips
Author: Kevin Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Lausanne, Switzerland, 2017

Automatic Equivalence Checking for SystemC-TLM 2.0 Models Against their Formal Specifications
Author: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Lausanne, Switzerland, 2017

Data Flow Testing for Virtual Prototypes
Author: Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Lausanne, Switzerland, 2017

Endurance Management for Resistive Logic-In-Memory Computing Architectures
Author: Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Lausanne, Switzerland, 2017

Optimization of Retargeting for IEEE 1149.1 TAP Controllers with Embedded Compression
Author: Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Lausanne, Schweiz, 2017

Trust is good, Control is better: Hardware-based Instruction-Replacement for Reliable Processor-IPs
Author: Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler
Conference: 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Chiba/Tokyo, Japan, 2017

Enhancing Robustness of Sequential Circuits Using Application-specific Knowledge and Formal Methods
Author: Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference: 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Chiba/Tokyo, Japan, 2017

Exact Routing for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
Author: Oliver Keszöcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler
Conference: 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Chiba/Tokyo, Japan, 2017

Exploring Superior Structural Materials Using Multi-Objective Optimization and Formal Techniques
Author: Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler
Conference: 6th IEEE International Symposium on Embedded Computing & System Design (ISED)
Pdf | Reference: Indian Institute of Technology, Patna, India, 2016

Clocks vs. Instants Relations: Verifying CCSL Time Constraints in UML/MARTE Models
Author: Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler
Conference: 14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Reference: Indian Institute of Technology, Kanpur, India, 2016

Frame Conditions in Symbolic Representations of UML/OCL Models
Author: Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler
Conference: 14th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)
Pdf | Reference: pp. 65-70, Indian Institute of Technology, Kanpur, India, 2016

Guided Lightweight Software Test Qualification for IP Integration using Virtual Prototypes
Author: Daniel Große, Hoang M. Le, Muhammad Hassan, Rolf Drechsler
Conference: IEEE International Conference on Computer Design (ICCD)
Pdf | Reference: Phoenix, USA, 2016

AIBA: an Automated Intra-Cycle Behavioral Analysis for SystemC-based Design Exploration
Author: Mehran Goli, Jannis Stoppe, Rolf Drechsler
Conference: IEEE International Conference on Computer Design (ICCD)
Pdf | Reference: Phoenix, USA, 2016

Generating and Checking Control Logic in the HDL-based Design of Reversible Circuits
Author: Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Conference: International Symposium on Electronic System Design (ISED)
Reference: Patna, Indien, 2016

An Improved Gate Library for Logic Synthesis of Optical Circuits
Author: Shuchisman Burman, Kamalika Datta, Robert Wille, Indranil Sengupta, Rolf Drechsler
Conference: International Symposium on Electronic System Design (ISED)
Reference: Patna, Indien, 2016

Towards a Model-Based Verification Methodology for Complex Swarm Systems
Author: Jonas Gomes Filho, Nils Przigoda, Robert Wille, Rolf Drechsler
Conference: International Symposium on Electronic System Design (ISED)
Reference: Patna, Indien, 2016

Ground Setting Properties for an Efficient Translation of OCL in SMT-based Model Finding
Author: Nils Przigoda, Robert Wille, Rolf Drechsler
Conference: ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Pdf | Reference: Saint Malo, Brittany, France, 2016

Equivalence Checking Using Gröbner Bases
Author: Amr Sayed Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler
Conference: Formal Methods in Computer Aided Design (FMCAD)
Pdf | Reference: Mountain View, USA, 2016

On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-based Error Effect Simulation - A Case Study
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: Bremen, Germany, 2016
Best Paper Candidate

Approximation-aware Rewriting of AIGs for Error Tolerant Applications
Author: Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference: International Conference on Computer Aided Design (ICCAD)
Pdf | Reference: Austin, USA, 2016

Compiled Symbolic Simulation for SystemC
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference: International Conference on Computer Aided Design (ICCAD)
Pdf | Reference: Austin, USA, 2016

Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs
Author: Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler
Conference: Reversible Computation
Reference: Bologna, Italy, 2016

ParCoSS: Efficient Parallelized Compiled Symbolic Simulation
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference: International Conference on Computer Aided Verification (CAV)
Pdf | Reference: Toronto, Canada, 2016

Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm
Author: Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference: Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Reference: Denver, USA, 2016

An MIG-based Compiler for Programmable Logic-in-Memory Architectures
Author: Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli
Conference: Design Automation Conference (DAC)
Pdf | Reference: Austin, USA, 2016

Precise Error Determination of Approximated Components in Sequential Circuits with Model Checking
Author: Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: Austin, USA, 2016

Multi-Objective BDD Optimization for RRAM based Circuit Design
Author: Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
Conference: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'16)
Pdf | Reference: Košice, Slovakia, 2016

VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers
Author: Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler
Conference: IEEE European Test Symposium (ETS)
Pdf | Reference: Amsterdam, Niederlande, 2016

Fault Detection in Parity Preserving Reversible Circuits
Author: Nils Przigoda, Gerhard Dueck, Robert Wille, Rolf Drechsler
Conference: 46th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Sapporo, Japan, 2016

Re-writing HDL Descriptions for Line-aware Synthesis of Reversible Circuits
Author: Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference: 46th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Sapporo, Japan, 2016

Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation
Author: Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference: 46th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Sapporo, Japan, 2016

Technology mapping of reversible circuits to Clifford+T quantum circuits
Author: Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler
Conference: 46rd International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Sapporo, Japan, 2016

Quantitative Timing Analysis of UML Activity Diagrams Using Statistical Model Checking
Author: Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 780-785, Dresden, Germany, 2016

Towards Formal Verification of Real-World SystemC TLM Peripheral Models - A Case Study
Author: Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1160-1163, Dresden, Germany, 2016

Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction
Author: Amr Sayed Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1048-1053, Dresden, Germany, 2016
Best Paper Candidate

Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs
Author: Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Dresden, Germany, 2016

Look-ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits
Author: Robert Wille, Oliver Keszöcze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Macao, China, 2016

BDD Minimization for Approximate Computing
Author: Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: pp. 474-479, Macao, China, 2016

Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library
Author: Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
Conference: International Conference on VLSI Design (VLSI Design)
Reference: Kolkata, India, 2016

Hardware/Software Co-Visualization on the Electronic System Level using SystemC
Author: Rolf Drechsler, Jannis Stoppe
Conference: International Conference on VLSI Design
Pdf | Reference: Kolkata, India, 2016

Ensuring Safety and Reliability of IP-based System Design – A Container Approach
Author: Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, Rolf Drechsler
Conference: IEEE International Symposium on Rapid System Protoyping (RSP), 2015
Pdf | Reference:

Reversible Computation: An Alternative Computation Paradigm for Low Power Applications
Author: Rolf Drechsler, Robert Wille
Conference: International Green and Sustainable Computing Conference (IGSC)
Pdf | Reference: Las Vegas, USA, 2015

Checking Concurrent Behavior in UML/OCL Models
Author: Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, Rolf Drechsler
Conference: ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS)
Pdf | Reference: Ottawa, Kanada, 2015

Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation
Author: Hoang M. Le, Rolf Drechsler
Conference: Design and Verification Conference and Exhibition Europe (DVCon Europe)
Pdf | Reference: Munich, Germany, 2015

Reverse Engineering with Simulation Graphs
Author: Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton
Conference: Formal Methods in Computer Aided Design (FMCAD)
Pdf | Reference: Austin, 2015

Reversible Circuit Rewriting with Simulated Annealing
Author: Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, and Rolf Drechsler
Conference: IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Pdf | Reference: Daejeon, Korea, 2015

A General and Exact Routing Methodology for Digital Microfluidic Biochips
Author: Oliver Keszöcze, Robert Wille, Krishnendu Chakrabarty Rolf Drechsler
Conference: International Conference on Computer Aided Design (ICCAD)
Pdf | Reference: Austin, USA, 2015

Formal Methods for Emerging Technologies
Author: Robert Wille, Rolf Drechsler
Conference: International Conference on Computer Aided Design (ICCAD)
Reference: Austin, USA, 2015

Leveraging the Analysis for Invariant Independence in Formal System Models
Author: Nils Przigoda, Robert Wille, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Funchal, Madeira, Portugal, 2015

Verification-driven Design Across Abstraction Levels - A Case Study
Author: Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Funchal, Madeira, Portugal, 2015

Envisioning Self-Verification of Electronic Systems
Author: Rolf Drechsler, Martin Fränzle, Robert Wille
Conference: Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
Pdf | Reference: Bremen, Germany, 2015

Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits
Author: Amr Sayed Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015).
Pdf | Reference: pp. 1-6, Montpellier, France, 2015.

Coverage of OCL Operation Specifications and Invariants
Author: Mathias Soeken, Julia Seiter, Rolf Drechsler
Conference: 9th International Conference on Tests & Proofs (TAP)
Pdf | Reference: L’Aquila, Italy, 2015

Towards Line-aware Realizations of Expressions for HDL-based Synthesis of Reversible Circuits
Author: Zaid Al-Wardi, Robert Wille, Rolf Drechsler
Conference: Reversible Computation
Pdf | Reference: Grenoble, France, 2015

Technology mapping for quantum circuits using Boolean functional decomposition
Author: Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
Conference: Reversible Computation
Pdf | Reference: Grenoble, France, 2015

Multi-Objective BDD Optimization with Evolutionary Algorithms
Author: Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler
Conference: Genetic and Evolutionary Computation Conference (GECCO)
Pdf | Reference: Madrid, 2015

Contradiction Analysis for Inconsistent Formal Models
Author: Nils Przigoda, Robert Wille, Rolf Drechsler
Conference: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Pdf | Reference: Belgrade, Serbia, 2015

Requirement Phrasing Assistance using Automatic Quality Assessment
Author: Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler
Conference: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS'15)
Pdf | Reference: Belgrade, Serbia, 2015

A Generic Representation of CCSL Time Constraints for UML/MARTE Models
Author: Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: San Francisco, 2015

Verifying SystemC using Stateful Symbolic Simulation
Author: Vladimir Herdt, Hoang M. Le, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: San Francisco, 2015

An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization
Author: Arighna Deb, Robert Wille, Rolf Drechsler, Debesh Das
Conference: 45th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Waterloo, Canada, 2015

An Examination of the NCV-v1 Quantum Library Based on Minimal Circuits
Author: Arman Allahyari-Abhari, Robert Wille, Rolf Drechsler
Conference: 45th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: Waterloo, Canada, 2015

Automated Feature Localization for Dynamically Generated SystemC Designs
Author: Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE'15)
Pdf | Reference: Grenoble, France, 2015

BDD-based Synthesis for All-optical Mach-Zehnder Interferometer Circuits
Author: Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference: International Conference on VLSI Design (VLSI Design)
Pdf | Reference: Bengaluru, India, 2015

Determining the Minimal Number of SWAP Gates for Multi-dimensional Nearest Neighbor Quantum Circuits
Author: Aaron Lye, Robert Wille, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Chiba/Tokyo, 2015

Reverse BDD-based Synthesis for Splitter-free Optical Circuits
Author: Robert Wille, Oliver Keszöcze, Clemens Hopfmuller, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: Chiba/Tokyo, 2015

Safe IP Integration Using Container Modules
Author: Rolf Drechsler, Ulrich Kühne
Conference: International Symposium on Electronic System Design (ISED)
Pdf | Reference: Mangalore, India, 2014

Exact Routing for Digital Microfluidic Biochips with Temporary Blockages
Author: Oliver Keszöcze, Robert Wille, Rolf Drechsler
Conference: International Conference on Computer Aided Design (ICCAD)
Pdf | Reference: San Jose, 2014

Automated and Quality-driven Requirements Engineering
Author: Rolf Drechsler, Mathias Soeken, Robert Wille,
Conference: International Conference on Computer Aided Design (ICCAD)
Pdf | Reference: San Jose, 2014

CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC
Author: Hoang M. Le, Rolf Drechsler
Conference: Design and Verification Conference and Exhibition Europe (DVCon Europe)
Pdf | Reference: Munich, Germany, 2014

metaSMT: A Unified Interface to SMT-LIB2
Author: Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL'14)
Pdf | Reference: pp. 1-6, Munich, Germany, 2014

Automating the Translation of Assertions Using Natural Language Processing Techniques
Author: Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris and Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: Munich, Germany, 2014

Automatic Refinement Checking for Formal System Models
Author: Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: Munich, Germany, 2014

Verifying Consistency between Activity Diagrams and Their Corresponding OCL Contracts
Author: Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: Munich, Germany, 2014

Quality Assessment for Requirements based on Natural Language Processing
Author: Mathias Soeken, Nabila Abdessaied, Arman Allahyari-Abhari, Andi Buzo, Liana Musat, Georg Pelz, Rolf Drechsler
Conference: Special Session at the Forum on Specification & Design Languages (FDL'14)
Pdf | Reference: Munich, Germany, 2014

Improving Coverage of Simulation-based Verification by Dedicated Stimuli Generation
Author: Shuo Yang, Robert Wille, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: pp. 599-606, Verona, Italy, 2014

Determining Cases of Scenarios to Improve Coverage in Simulation-based Verication
Author: Shuo Yang, Robert Wille, Rolf Drechsler
Conference: Symposium on Integrated Circuits and System Design (SBCCI)
Pdf | Reference: Aracaju, Brazil, 2014

Validating SystemC Implementations Against Their Formal Specifications
Author: Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference: Symposium on Integrated Circuits and System Design (SBCCI)
Pdf | Reference: Aracaju, Brazil, 2014

Self-Verification as the Key Technology for Next Generation Electronic Systems
Author: Rolf Drechsler, Hoang M. Le, Mathias Soeken
Conference: Symposium on Integrated Circuits and System Design (SBCCI)
Pdf | Reference: Aracaju, Brazil, 2014

Recent Advances in SAT-based ATPG: Non-Standard Fault Models, Multi Constraints and Optimization
Author: Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer
Conference: International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)
Pdf | Reference: pp. 1-10, Santorini, Greece, 2014

Behaviour Driven Development for Tests and Verification
Author: Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler
Conference: 8th International Conference on Tests & Proofs (TAP)
Pdf | Reference: pp. 61-77, York, 2014

Generating SystemC Implementations for Clock Constraints specified in UML/MARTE CCSL
Author: Judith Peters, Robert Wille, Rolf Drechsler
Conference: International Conference on Engineering of Complex Computer Systems (ICECCS)
Pdf | Reference: pp. 116-125, Tianjin, China, 2014

Exact One-pass Synthesis of Digital Microfluidic Biochips
Author: Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: San Francisco, 2014

Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State-of-the-Art and Research Challenges
Author: Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Gruettner, Thomas Kruse, Christoph Kuznik, Hoang M. Le, Andreas Mauderer, Wolfgang Mueller, Daniel Mueller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, Simon Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl
Conference: Design Automation Conference (DAC)
Reference: pp. 113:1-6, San Francisco, 2014

Mapping NCV Circuits to Optimized Clifford+T Circuits
Author: D. Michael Miller, Mathias Soeken, Rolf Drechsler
Conference: Reversible Computation
Pdf | Reference: Kyoto, Japan, 2014

Equivalence Checking in Multi-level Quantum Systems
Author: Philipp Niemann, Robert Wille, Rolf Drechsler
Conference: Reversible Computation
Pdf | Reference: pp. 201-215, Kyoto, Japan, 2014

RevVis: Visualization of Structures and Properties in Reversible Circuits
Author: Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler
Conference: Reversible Computation
Pdf | Reference: Kyoto, Japan, 2014

Quantum Circuit Optimization by Hadamard Gate Reduction
Author: Nabila Abdessaied, Mathias Soeken, Rolf Drechsler
Conference: Reversible Computation
Pdf | Reference: Kyoto, Japan, 2014

Optimizing DD-based Synthesis of Reversible Circuits using Negative Control Lines
Author: Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference: IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: pp. 129-134, Warschau, Polen, 2014

Optimization-based Multiple Target Test Generation for Highly Compacted Test Sets
Author: Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Conference: 19th IEEE European Test Symposium (ETS)
Pdf | Reference: Paderborn, Germany, 2014

A Cube Pairing Approach for Synthesis of ESOP based Reversible Circuit
Author: Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler
Conference: 44rd International Symposium on Multiple-Valued Logic (ISMVL)
Reference: Bremen, 2014

Future SoC Verification Methodology: UVM Evolution or Revolution?
Author: Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev
Conference: Design, Automation and Test in Europe (DATE'14)
Pdf | Reference: Dresden, Germany, 2014

Towards Verifying Determinism of SystemC Designs
Author: Hoang M. Le, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE'14)
Pdf | Reference: pp. 153:1-4, Dresden, Germany, 2014

Grammar-based Program Generation Based on Model Finding
Author: Mathias Soeken, Rolf Drechsler
Conference: IEEE Design and Test Symposium 2013 (IDT)
Pdf | Reference: Marrakesch, 2013

Optimal SWAP Gate Insertion for Nearest Neighbor Quantum Circuits
Author: Robert Wille, Aaron Lye, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: pp. 489-494, Singapore, 2014

Efficient Synthesis of Quantum Circuits Implementing Clifford Group Operations
Author: Philipp Niemann, Robert Wille, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: pp. 483-488, Singapore, 2014

Improved SAT-based ATPG: More Constraints, Better Compaction
Author: Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Conference: IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
Pdf | Reference: pp. 85-90, San Jose, USA, 2013

A Compact and Efficient SAT Encoding for Quantum Circuits
Author: Robert Wille, Nils Przigoda, Rolf Drechsler
Conference: IEEE Africon
Pdf | Reference: Mauritius, 2013

Exploiting Reversibility in the Complete Simulation of Reversible Circuits
Author: Robert Wille, Simon Stelter, Rolf Drechsler
Conference: IEEE Africon
Pdf | Reference: Mauritius, 2013

Cone of Influence Analysis at the Electronic System Level Using Machine Learning
Author: Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Santander, Spain, 2013

Minimal Stimuli Generation in Simulation-based Verification
Author: Shuo Yang, Robert Wille, Daniel Große and Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Santander, Spain, 2013

The SyReC Hardware Description Language: Enabling Scalable Synthesis of Reversible Circuits
Author: Robert Wille, Rolf Drechsler
Conference: International Midwest Symposium on Circuits and Systems (MWSCAS)
Reference: Columbus, USA, 2013

Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred
Author: Nicole Drechsler, André Sülflow, Rolf Drechsler
Conference: International Conference on Evolutionary Computation Theory and Applications (ECTA)
Reference: Vilamoura, Portugal, 2013

Data Extraction from SystemC Designs using Debug Symbols and the SystemC API
Author: Jannis Stoppe, Robert Wille, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: Natal, Brazil, 2013

On the “Q” in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-structure
Author: Philipp Niemann, Robert Wille, Rolf Drechsler
Conference: Reversible Computation
Pdf | Reference: pp. 125-140, Victoria, Canada, 2013

Exploiting Negative Control Lines in the Optimization of Reversible Circuits
Author: Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler
Conference: Reversible Computation
Pdf | Reference: pp. 209-220, Victoria, Canada, 2013

Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure
Author: Arighna Deb, Debesh Kumar Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler
Conference: Reversible Computation
Pdf | Reference: pp. 182-195, Victoria, Canada, 2013

Reducing the Depth of Quantum Circuits Using Additional Lines
Author: Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler
Conference: Reversible Computation
Pdf | Reference: pp. 221-233, Victoria, Canada, 2013

Hardware-Software Co-Visualization: Developing Systems in the Holodeck
Author: Rolf Drechsler, Mathias Soeken
Conference: 16th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: pp. 1-4, Karlovy Vary, Czech Republic, 2013

Verifying SystemC using an Intermediate Verification Language and Symbolic Simulation
Author: Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: pp. 116:1-6 Austin, Texas, 2013

Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits
Author: Robert Wille, Hongyan Zhang, Rolf Drechsler
Conference: 43rd International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: pp. 29-34, Toyama, 2013

Debugging of Reversible Circuits using πDDs
Author: Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler
Conference: 43rd International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: pp. 316-321, Toyama, Japan, 2013

Exact Template Matching Using Boolean Satisfiability
Author: Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler
Conference: 43rd International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: pp. 328-333, Toyama, Japan, 2013

Synchronized Debugging across Different Abstraction Levels in System Design
Author: Rolf Drechsler, Daniel Große, Hoang M. Le, André Sülflow
Conference: embedded world Conference 2013
Pdf | Reference: Nürnberg, 2013

Scalable Fault Localization for SystemC TLM Designs
Author: Hoang M. Le, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE'13)
Pdf | Reference: pp. 35-38, Grenoble, France, 2013

Determining Relevant Model Elements for the Verification of UML/OCL Specifications
Author: Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1189-1192, Grenoble, France, 2013

Towards a Generic Verification Methodology for System Models
Author: Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1193-1196, Grenoble, France, 2013

Improving the Mapping of Reversible Circuits to Quantum Circuits Using Multiple Target Lines
Author: Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: pp. 145-150. Yokohama, Japan, 2013

An Evolutionary Approach to Reversible Logic Synthesis using Output Permutation
Author: Kamalika Datta, Indranil Sen Gupta, Hafizur Rahaman, Rolf Drechsler
Conference: IEEE Design and Test Symposium 2012 (IDT)
Pdf | Reference: Doha, 2012

Towards Dialog Systems for Assisted Natural Language Processing in the Design of Embedded Systems
Author: Rolf Drechsler, Mathias Soeken, Robert Wille
Conference: IEEE Design and Test Symposium 2012 (IDT)
Pdf | Reference: Doha, 2012

Synthesis of Reversible Circuits Using Decision Diagrams
Author: Rolf Drechsler, Robert Wille
Conference: International Symposium on Electronic System Design (ISED)
Pdf | Reference: pp. 1-5, Kolkata, WB, India, 2012

SyDe - a New Graduate School for System Design in an Excellent Setting
Author: Ulrich Kühne, Rolf Drechsler
Conference: Informatics Europe (ECSS)
Reference: Barcelona, 2012

From Requirements and Scenarios to ESL Design in SystemC
Author: Hoang M. Le, Daniel Große, Rolf Drechsler
Conference: International Symposium on Electronic System Design (ISED)
Pdf | Reference: pp. 183-187, Kolkata, WB, India, 2012

FoREnSiC - An Automatic Debugging Environment for C Programs
Author: Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow
Conference: Haifa Verification Conference (HVC)
Pdf | Reference: Haifa, 2012

The System Verification Methodology for Advanced TLM Verification
Author: Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Mueller, Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler, Wolfgang Ecker, Volkan Esen
Conference: International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)
Pdf | Reference: pp. 313-322, Tampere, 2012

Complete and Effective Robustness Checking by Means of Interpolation
Author: Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav and Rolf Drechsler
Conference: Formal Methods in Computer-Aided Design (FMCAD'12)
Pdf | Reference: Cambridge, UK, 2012, page 82-90

Completeness-Driven Development
Author: Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang M. Le, Julia Seiter, Mathias Soeken, Robert Wille
Conference: International Conference on Graph Transformation
Pdf | Reference: pp. 38-50, Bremen, 2012

CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC
Author: Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler
Conference: International Symposium on System-on-Chip (SoC)
Pdf | Reference: pp. 1-7, Tampere, 2012

Localizing Features of ESL Models for Design Understanding
Author: Marc Michael, Daniel Große, Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: Vienna, 2012

Formal Specification Level: Towards Verification-driven Design Based on Natural Language Processing
Author: Rolf Drechsler, Mathias Soeken, Robert Wille
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: pp. 53-58, Vienna, Austria, 2012

Circuit Line Minimization in the HDL-based Synthesis of Reversible Logic
Author: Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: pp. 213-218, Amherst, USA, 2012

Coverage-driven Stimuli Generation
Author: Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler
Conference: 15th Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: Izmir, Turkey, 2012

Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology
Author: Rolf Drechsler, Robert Wille
Conference: International Symposium on VLSI Design and Test (VDAT)
Pdf | Reference: Shibpur, India, 2012

Assisted Behavior Driven Development Using Natural Language Processing
Author: Mathias Soeken, Robert Wille, Rolf Drechsler
Conference: 50th International Conference on Objects, Models, Components, Patterns (TOOLS)
Pdf | Reference: pp. 269-287, Prague, Czech Republic, 2012

A New SAT-based ATPG for Generating Highly Compacted Test Sets
Author: Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
Conference: 15th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: pp. 230-235, Tallinn, Estonia, 2012

Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits
Author: Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler
Conference: 42nd International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: pp. 173-178, Victoria, Canada, 2012

A Synthesis Flow for Sequential Reversible Circuits
Author: Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler
Conference: 42nd International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: pp. 299-304, Victoria, Canada, 2012

Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines
Author: Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler
Conference: 42nd International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: pp. 69-74, Victoria, Canada, 2012

Automatic Design of Low-Power Encoders Using Reversible Circuit Synthesis
Author: Robert Wille, Rolf Drechsler, Christof Oswald, Alberto Garcia-Ortiz
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Dresden, 2012

A Guiding Coverage Metric for Formal Verification
Author: Finn Haedicke, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: Dresden, 2012

Eliminating Invariants in UML/OCL Models
Author: Mathias Soeken, Robert Wille, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1142-1145, Dresden, 2012

Debugging of Inconsistent UML/OCL Models
Author: Robert Wille, Mathias Soeken, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1078-1083, Dresden, 2012

Synthesis of Reversible Circuits with Minimal Lines for Large Functions
Author: Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference (ASP-DAC)
Pdf | Reference: pp. 85-92, Sydney, 2012

Improved Fault Diagnosis for Reversible Circuits
Author: Hongyan Zhang, Robert Wille, Rolf Drechsler
Conference: Asian Test Symposium (ATS)
Pdf | Reference: New Delhi, 2011

Hochoptimierter Ablauf zur Robustheitsprüfung
Author: Stefan Frehse, Finn Haedicke, Melanie Diepenbeck, Görschwin Fey, Rolf Drechsler
Conference: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)
Pdf | Reference: Hamburg-Harburg, 2011

Analyzing Dependability Measures at the Electronic System Level
Author: Marc Michael, Daniel Große, Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: pp. 1-8, Oldenburg, 2011

Efficient Realization of Control Logic in Reversible Circuits
Author: Sebastian Offermann, Robert Wille, Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: Oldenburg, 2011

Determining Minimal Testsets for Reversible Circuits Using Boolean Satisfiability
Author: Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference: 10th IEEE Africon
Pdf | Reference: Livingstone, 2011

VisSAT: Visualization of SAT Solver Internals for Computer Aided Hardware Verification
Author: Robert Wille, André Sülflow, Rolf Drechsler
Conference: International Conference on Modeling, Simulation and Visualization Methods (MSV)
Pdf | Reference: pp. 36-39, Las Vegas, 2011

ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization
Author: Robert Wille, Hongyan Zhang, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: pp. 120-125, Chennai, 2011

Encoding OCL Data Types for SAT-based Verification of UML/OCL Models
Author: Mathias Soeken, Robert Wille, Rolf Drechsler
Conference: 5th International Conference on Tests & Proofs (TAP)
Pdf | Reference: pp. 152-170, Zurich, 2011

Automatic Property Generation for the Formal Verification of Bus Bridges
Author: Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Conference: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: pp. 417-422, Cottbus, 2011

TLM Protocol Compliance Checking at the Electronic System Level
Author: Mohamed Bawadekji, Daniel Große, Rolf Drechsler
Conference: 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: pp. 435-440, Cottbus, 2011

Designing a RISC CPU in Reversible Logic
Author: Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Conference: 41st International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: pp. 170-175, Tuusula, 2011

From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits
Author: Rolf Drechsler, Robert Wille
Conference: 41st International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: pp. 78-85, Tuusula, 2011

Simulation-based Equivalence Checking between SystemC Models at different Levels of Abstraction
Author: Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Conference: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: pp. 223-228, Lausanne, 2011

Verifying Dynamic Aspects of UML Models
Author: Mathias Soeken, Robert Wille, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1077-1082, Grenoble, 2011

Determining the Minimal Number of Lines for Large Reversible Circuits
Author: Robert Wille, Oliver Keszöcze, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1204—1207, Grenoble, 2011

As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
Author: Stephan Eggersglüß, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1291-1296, Grenoble, 2011

Automatic Fault Localization for Programmable Logic Controllers
Author: Andre Sülflow, Rolf Drechsler
Conference: Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT)
Pdf | Reference: pp. 247-256, Braunschweig, 2010

Robust Algorithms for High Quality Test Pattern Generation Using Boolean Satisfiability
Author: Stephan Eggersglüß, Rolf Drechsler
Conference: International Test Conference (ITC)
Pdf | Reference: pp. 1-10, Austin, 2010

Polynomial Datapath Optimization using Constraint Solving and Formal Modelling
Author: Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler
Conference: IEEE/ACM International Conference on Computer Aided Design (ICCAD)
Pdf | Reference: San Jose, 2010

SyReC: A Programming Language for Synthesis of Reversible Circuits
Author: Robert Wille, Sebastian Offermann, Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: pp. 184-189, Southampton, 2010
Received Best Paper Award

Proving Transaction and System-level Properties of Untimed SystemC TLM Designs
Author: Daniel Große, Hoang M. Le, Rolf Drechsler
Conference: International Conference on Formal Methods and Models for Codesign (MEMOCODE)
Pdf | Reference: pp. 113-122, Grenoble, 2010

RobuCheck: A Robustness Checker for Digital Circuits
Author: Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: pp. 226-231, Lille, 2010

Reducing the Number of Lines in Reversible Circuits
Author: Robert Wille, Mathias Soeken, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: pp. 647-652, Anaheim, 2010

Synthesizing Multiplier in Reversible Logic
Author: Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: pp. 335-340, Vienna, 2010

Window Optimization of Reversible and Quantum Circuits
Author: Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: pp. 431-435, Vienna, 2010

A Better-Than-Worst-Case Robustness Measure
Author: Stefan Frehse, Görschwin Fey, Rolf Drechsler
Conference: 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: pp. 78-83, Vienna, 2010

Enhancing Debugging of Multiple Missing Control Errors in Reversible Logic
Author: Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
Conference: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: pp. 465-470, Rhode Island, 2010

Improving CNF Representations in SAT-based ATPG for Industrial Circuits using BDDs
Author: Daniel Tille, Stephan Eggersglüß, René Krenz-Bååth, Juergen Schloeffel, Rolf Drechsler
Conference: 15th IEEE European Test Symposium (ETS)
Pdf | Reference: pp. 176-181, Prag, 2010

An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions
Author: Alexander Finder, Rolf Drechsler
Conference: 40th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: pp. 150-155, Barcelona, 2010

Efficient Simulation-based Debugging of Reversible Logic
Author: Stefan Frehse, Robert Wille, Rolf Drechsler
Conference: 40th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: pp. 156-161, Barcelona, 2010

Reducing Reversible Circuit Cost by Adding Lines
Author: D. Michael Miller, Robert Wille, Rolf Drechsler
Conference: 40th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: pp. 217-222, Barcelona, 2010

Efficient Test Generation with Maximal Crosstalk-Induced Noise using Unconstrained Aggressor Excitation
Author: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Conference: IEEE International Symposium on Circuits and Systems (ISCAS)
Pdf | Reference: pp. 649-652, Paris, 2010

Using QBF to Increase Accuracy of SAT-Based Debugging
Author: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Conference: IEEE International Symposium on Circuits and Systems (ISCAS)
Pdf | Reference: pp.641-644, Paris, 2010

Verifying UML/OCL Models Using Boolean Satisfiability
Author: Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1341-1344, Dresden, 2010, 2010

Timing Arc Based Logic Analysis for False Noise Reduction
Author: Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler
Conference: IEEE/ACM International Conference on Computer Aided Design (ICCAD)
Pdf | Reference: pp. 225-230, San Jose, 2009

Anwendungsbezogene Analyse der Robustheit von Digitalen Schaltungen
Author: Andre Sülflow, Stefan Frehse, Görschwin Fey, Rolf Drechsler
Conference: GMM/GI/ITG-Fachtagung Zuverlässigkeit und Entwurf (ZUE)
Pdf | Reference: pp. 45-52, Stuttgart, 2009

Structural Heuristics for SAT-based ATPG
Author: Daniel Tille, Stephan Eggersglüß, Hoang M. Le, Rolf Drechsler
Conference: 17th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2009)
Pdf | Reference: pp. 77-82, Florianópolis, 2009

Speeding up SAT-based ATPG using Dynamic Clause Activation
Author: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Conference: 18th Asian Test Symposium (ATS'09)
Pdf | Reference: pp. 177-182, Taichung, 2009

Automatic Debugging of System-on-a-Chip Designs
Author: Frank Rogin, Rolf Drechsler, Steffen Rülke
Conference: IEEE International SOC Conference (SOCC)
Pdf | Reference: Belfast, 2009

SMT-based Stimuli Generation in the SystemC Verification Library
Author: Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: pp. 1-6, Sophia Antipolis, 2009

Robustness Check for Multiple Faults using Formal Techniques
Author: Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: pp. 85-90, Patras, 2009

BDD-based Synthesis of Reversible Logic for Large Functions
Author: Robert Wille, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: pp. 270-275, San Francisco, 2009

Computing Bounds for Fault Tolerance using Formal Techniques
Author: Görschwin Fey, Andre Sülflow, Rolf Drechsler
Conference: Design Automation Conference (DAC)
Pdf | Reference: pp. 190-195, San Francisco, USA, 2009

WoLFram - A Word Level Framework for Formal Verification
Author: Andre Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler
Conference: IEEE/IFIP International Symposium on Rapid System Prototyping (RSP)
Pdf | Reference: pp. 11-17, Paris, 2009

A Fast Untestability Proof for SAT-based ATPG
Author: Daniel Tille, Rolf Drechsler
Conference: 12th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Pdf | Reference: pp. 38-43, Liberec, 2009

Increasing Robustness of SAT-based Delay Test Generation using Efficient Dynamic Learning Techniques
Author: Stephan Eggersglüß, Rolf Drechsler
Conference: 14th IEEE European Test Symposium (ETS)
Pdf | Reference: pp. 81-86, Sevilla, 2009

Contradictory Antecedent Debugging in Bounded Model Checking
Author: Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Conference: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: pp. 173-176, Boston, 2009

Evaluation of Cardinality Constraints on SMT-based Debugging
Author: Andre Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler
Conference: 39th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: pp. 298-303, Naha, Okinawa, 2009

Equivalence Checking of Reversible Circuits
Author: Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Conference: 39th International Symposium on Multiple-Valued Logic (ISMVL)
Pdf | Reference: pp. 324-330, Naha, Okinawa, 2009

Approximate BDD Minimization by Weighted A*
Author: Rüdiger Ebendt, Rolf Drechsler
Conference: IEEE International Symposium on Circuits and Systems (ISCAS'09)
Reference: Taipei, 2009

Overcoming Limitations of the SystemC Data Introspection
Author: Christian Genz, Rolf Drechsler
Conference: Design Automation and Test in Europe (DATE)
Pdf | Reference: pp. 590-593, Nice, 2009

Property Analysis and Design Understanding
Author: Ulrich Kühne, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1246-1249, Nice, 2009

Debugging of Toffoli Networks
Author: Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1284-1289, Nice, 2009

Increasing the Accuracy of SAT-based Debugging
Author: Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1326-1332, Nice, 2009

Reversible Logic Synthesis with Output Permutation
Author: Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Conference: 22nd International Conference on VLSI Design
Pdf | Reference: pp. 189-194, New Delhi, 2009

Formaler Nachweis der Fehlertoleranz von Schaltkreisen
Author: Görschwin Fey, Andre Sülflow, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Conference: GMM/GI/ITG-Fachtagung: Zuverlässigkeit und Entwurf (ZuE 2008)
Pdf | Reference: pp. 75-82, Ingolstadt, 2008

Verification of PLC Programs using Formal Proof Techniques
Author: Andre Sülflow, Rolf Drechsler
Conference: Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
Pdf | Reference: pp. 43-50, Budapest, 2008

Efficient Formal Verification of Track Vacancy Detection Sections
Author: Sebastian Kinder und Rolf Drechsler
Conference: Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2008)
Reference: pp. 233-240, Budapest, 2008

Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking
Author: Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Pdf | Reference: pp. 542-549, Parma, 2008

Contradiction Analysis for Constraint-based Random Simulation
Author: Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: pp. 130-135, Stuttgart, 2008

Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
Author: Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: pp. 411-416, Montpellier, 2008

RevLib: An Online Resource for Reversible Functions and Reversible Circuits
Author: Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler
Conference: 38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Pdf | Reference: pp. 220-225, Dallas
RevLib is available at www.revlib.org, 2008

Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don’t Cares
Author: Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
Conference: 38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Pdf | Reference: pp. 214-219, Dallas
Received IEEE Young Researcher Award, 2008

On the Influence of Boolean Encodings in SAT-based ATPG for Path Delay Faults
Author: Stephan Eggersglüß, Rolf Drechsler
Conference: 38th International Symposium on Multiple-Valued Logic 2008 (ISMVL '08)
Pdf | Reference: pp. 94-99, Dallas, 2008

Using Unsatisfiable Cores to Debug Multiple Design Errors
Author: Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Conference: IEEE Great Lakes Symposium on VLSI (GLSVLSI'08)
Pdf | Reference: pp. 77-82, Orlando, 2008

Process Variations Aware Robust on-Chip Bus Architecture Synthesis for MPSoCs
Author: Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner
Conference: IEEE International Symposium on Circuits and Systems (ISCAS'08)
Reference: Seattle, 2008

A Basis for Formal Robustness Checking
Author: Görschwin Fey, Rolf Drechsler
Conference: International Symposium on Quality of Electronic Design (ISQED)
Pdf | Reference: San Jose, 2008

Adaptive Branch and Bound using SAT to Estimate False Crosstalk
Author: Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
Conference: International Symposium on Quality of Electronic Design (ISQED)
Reference: San Jose, 2008

Automatic Generation of Complex Properties for Hardware Designs
Author: Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler Steffen Rülke
Conference: Design, Automation, and Test in Europe (DATE)
Pdf | Reference: Munich, 2008

Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs
Author: Sujan Pandey, Rolf Drechsler
Conference: Design, Automation, and Test in Europe (DATE)
Pdf | Reference: Munich, 2008

Robust On-Chip Bus architecture Synthesis for MPSoCs Under Random Tasks Arrival
Author: Sujan Pandey, Rolf Drechsler
Conference: 13th Asia and South Pacific Design Automation Conference, (ASP-DAC 2008)
Pdf | Reference: Seoul, 2008

SWORD: A SAT like Prover Using Word Level Information
Author: Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler
Conference: IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC)
Pdf | Reference: pp. 88-93, Atlanta, 2007

Co-Synthesis of Custom On-Chip Bus and Memory for MPSoC Architectures
Author: Sujan Pandey, Christian Genz, Rolf Drechsler
Conference: IFIP International Conference on Very Large Scale Integration Systems and Systems on Chip (VLSI-SoC)
Pdf | Reference: pp. 304-307, Atlanta, 2007

Improving Test Pattern Compactness in SAT-based ATPG
Author: Stephan Eggersglüß, Rolf Drechsler
Conference: 16th Asian Test Symposium (ATS’07)
Pdf | Reference: pp. 445-450, Beijing, 2007

An Integrated SystemC Debugging Environment
Author: Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke
Conference: Forum on Specification & Design Languages (FDL)
Pdf | Reference: pp. 140-145, Barcelona, 2007

Measuring the Quality of a SystemC Testbench by using Code Coverage Technqiues
Author: Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler
Conference: Forum on specification & Design Languages (FDL)
Pdf | Reference: pp. 146-151, Barcelona
Received Best Paper Award, 2007

Proving Completeness of Properties in Formal Verification of Counting Heads for Railways
Author: Sebastian Kinder and Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools

Pdf | Reference: Lübeck, 2007

On the Construction of Small Fully Testable Circuits with Low Depth
Author: Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
Conference: Euromicro Conference on Digital System Design (DSD)
Architectures, Methods and Tools

Pdf | Reference: Lübeck, 2007

Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?
Author: Rolf Drechsler, Andreas Breiter
Conference: 2nd International Conference on Software and Data Technologies
Pdf | Reference: Barcelona, 2007

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Author: Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel
Conference: Fifth ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2007)
Pdf | Reference: pp. 181-187, Nice, 2007

Improving the Quality of Bounded Model Checking by Means of Coverage Estimation
Author: Ulrich Kühne, Daniel Große, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
Pdf | Reference: pp. 165-170, Porto Alegre, 2007

Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^m) in SystemC
Author: Andre Sülflow, Rolf Drechsler
Conference: 37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Pdf | Reference: pp. 42, Oslo, 2007

Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL
Author: Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler
Conference: 37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Pdf | Reference: Oslo, 2007

Experimental Studies on SAT-based ATPG for Gate Delay Faults
Author: Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Conference: 37th International Symposium on Multiple-Valued Logic 2007 (ISMVL '07)
Pdf | Reference: Oslo, 2007

Visualization of SystemC Designs
Author: Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard
Conference: IEEE International Symposium on Circuits and Systems (ISCAS)
Pdf | Reference: pp. 413-416, New Orleans, 2007

SAT-based ATPG for Path Delay Faults in Sequential Circuits
Author: Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler
Conference: IEEE International Symposium on Circuits and Systems (ISCAS'07)
Pdf | Reference: pp. 3671-3674, New Orleans, 2007

Improvements for Constraint Solving in the SystemC Verification Library
Author: Daniel Große, Rüdiger Ebendt, Rolf Drechsler
Conference: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: pp. 493-496, Stresa, 2007

Exact SAT-based Toffoli Network Synthesis
Author: Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
Conference: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: pp. 96-101, Stresa, 2007

Ein formaler Ansatz zum Robustheitsnachweis
Author: Görschwin Fey, Rolf Drechsler
Conference: Zuverlässigkeit und Entwurf
Pdf | Reference: München, 2007

Robust Multi-Objective Optimization in High Dimensional Spaces
Author: André Sülflow, Nicole Drechsler, Rolf Drechsler
Conference: Fourth International Conference on Evolutionary Multi-Criterion Optimization
Pdf | Reference: pp. 715-726, Matsushima, 2007

Estimating Functional Coverage in Bounded Model Checking
Author: Daniel Große, Ulrich Kühne, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1176-1181, Nice, 2007

Modeling and Formal Verification of Counting Heads for Railways
Author: Sebastian Kinder, Rolf Drechsler
Conference: Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2007)
Pdf | Reference: Braunschweig, 2007

Reusing Learned Information in SAT-based ATPG
Author: Görschwin Fey, Tim Warode, Rolf Drechsler
Conference: 20th International Conference on VLSI Design
Pdf | Reference: Bangalore, 2007

Automatic Fault Localization for Property Checking
Author: Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Conference: Haifa Verification Conference
Pdf | Reference: Haifa, 2006

Technical Documentation of Software and Hardware in Embedded Systems
Author: Beate Muranko, Rolf Drechsler
Conference: IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2006)
Pdf | Reference: Nice, France, 2006

A Framework for Quasi-Exact Optimization using Relaxed Best-First Search
Author: Rüdiger Ebendt, Rolf Drechsler
Conference: 29th Annual German Conference on Artificial Intelligence (KI'06)
Pdf | Reference: Bremen, 2006, 2006

HW/SW Co-Verification of Embedded Systems using Bounded Model Checking
Author: Daniel Große, Ulrich Kühne, Rolf Drechsler
Conference: Great Lakes Symposium on VLSI (GLSVLSI)
Pdf | Reference: pp. 43-48, Philadelphia, 2006

Efficiency of Multiple-Valued Encoding in SAT-based ATPG
Author: Görschwin Fey, Junhao Shi, Rolf Drechsler
Conference: IEEE International Symposium on Multiple-Valued Logic (ISMVL '06)
Pdf | Reference: Singapore, 2006

Integrating Observability Don't Cares in All-Solution SAT Solvers
Author: Sean Safarpour, Andreas Veneris, Rolf Drechsler
Conference: IEEE International Symposium on Circuits and Systems (ISCAS'06)
Pdf | Reference: Kos, 2006

On the Sensitivity of BDDs with Respect to Path-Related Objective Functions
Author: Rüdiger Ebendt, Rolf Drechsler
Conference: IEEE International Symposium on Circuits and Systems (ISCAS'06)
Pdf | Reference: Kos, 2006

System Exploration of SystemC Designs
Author: Christian Genz, Rolf Drechsler
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Pdf | Reference: pp. 335-340, Karlsruhe, 2006

On the Relation Between Simulation-based and SAT-based Diagnosis
Author: Görschwin Fey, Sean Safarpour, Andreas Veneris, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1139-1144, Munich, 2006

Efficient Minimization of Fully Testable 2-SPP Networks
Author: Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1300-1305, Munich, 2006

Avoiding False Negatives in Formal Verification for Protocol-Driven Blocks
Author: Görschwin Fey, Daniel Große, Rolf Drechsler
Conference: Design, Automation and Test in Europe (DATE)
Pdf | Reference: pp. 1225-1226, Munich, 2006

An Integrated Approach for Combining BDD and SAT Provers
Author: Rolf Drechsler, Görschwin Fey, Sebastian Kinder
Conference: International Conference on VLSI Design
Pdf | Reference: Hyderabad, 2006

Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits
Author: Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
Conference: International Conference on ASIC (ASICON 2005)
Pdf | Reference: pp. 967-970, Shanghai, 2005

Post-Verification Debugging of Hierarchical Designs
Author: Moayad Ali, Sean Safarpour, Andreas Veneris, Magdy Abadir, Rolf Drechsler
Conference: IEEE International Conference on Computer Aided Design (ICCAD'05)
Pdf | Reference: pp. 871-876, San Jose, 2005

Exact BDD Minimization for Path-Related Objective Functions
Author: Rüdiger Ebendt, Rolf Drechsler
Conference: IFIP International Conference on Very Large Scale Integration (IFIP VLSI-SOC 2005)
Reference: pp. 525-530, Perth, 2005

Acceleration of SAT-based Iterative Property Checking
Author: Daniel Große, Rolf Drechsler
Conference: Correct Hardware Design and Verification Methods (CHARME)
Pdf | Reference: pp. 349-353, Saarbrücken, 2005

Quasi-Exact BDD Minimization using Relaxed Best-First Search
Author: Rüdiger Ebendt and Rolf Drechsler
Conference: IEEE Annual Symposium on VLSI (ISVLSI '05)
Pdf | Reference: pp. 59-64, Tampa, Florida, 2005

PASSAT: Efficient SAT-based Test Pattern Generation
Author: Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Conference: IEEE Annual Symposium on VLSI (ISVLSI '05)
Reference: pp.212-217, Tampa, Florida, 2005

Controlling the Memory During Manipulation of Word-Level Decision Diagrams
Author: Sebastian Kinder, Görschwin Fey, Rolf Drechsler
Conference: IEEE International Symposium on Multi-Valued Logic (ISMVL 2005)
Reference: pp. 250-255, Calgary, 2005

Utilizing Don't Care States in SAT-based Bounded Sequential Problems
Author: Sean Safarpour, Görschwin Fey, Andreas Veneris, Rolf Drechsler
Conference: Great Lakes Symposium on VLSI (GLSVLSI'05)
Pdf | Reference: Chicago, 2005

CheckSyC: An Efficient Property Checker for RTL SystemC Designs
Author: Daniel Große, Rolf Drechsler
Conference: IEEE International Symposium on Circuits and Systems (ISCAS'05)
Pdf | Reference: pp. 4167-4170, Kobe, 2005

Bridging Fault Testability of BDD Circuits
Author: Junhao Shi, Görschwin Fey, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005)
Pdf | Reference: pp. 188-191 Shanghai, 2005

Lower Bounds for Dynamic BDD Reordering
Author: Rüdiger Ebendt and Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005)
Pdf | Reference: pp. 579-582, Shanghai, 2005

Automated Verification For Train Control Systems
Author: Jan Peleska, Daniel Große, Anne E. Haxthausen, Rolf Drechsler
Conference: Formal Methods for Automation and Safety in Railway and Automotive Systems (FORMS/FORMAT 2004)
Pdf | Reference: pp. 252-265, Braunschweig, 2004

Debugging Sequential Circuits Using Boolean Satisfiability
Author: Moayad Ali, Andreas Veneris, Sean Safarpour, Magdy Abadir, Rolf Drechsler, Alexander Smith
Conference: IEEE International Conference on Computer Aided Design (ICCAD'04)
Pdf | Reference: pp. 204-209, San Jose, 2004

BDD Circuit Optimization for Path Delay Fault Testability
Author: Görschwin Fey, Junhao Shi, Rolf Drechsler
Conference: Euromicro Symposium on Digital System Design (DSD'2004)
Reference: pp. 168-172, Rennes, 2004

Checkers for SystemC Designs
Author: Daniel Große, Rolf Drechsler
Conference: Second ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2004)
Pdf | Reference: pp. 171-178, San Diego, 2004

Reduction of Sizes of Multiple-Valued Decision Diagrams by Copy Properties
Author: Dragan Jankovic, Radomir Stankovic, Rolf Drechsler
Conference: IEEE International Symposium on Multi-Valued Logic (ISMVL'2004)
Reference: pp. 229-234, Toronto, 2004

Algorithms for Taylor Expansion Diagrams
Author: Görschwin Fey, Rolf Drechsler, Maciej Ciesielski
Conference: IEEE International Symposium on Multi-Valued Logic (ISMVL'2004)
Reference: pp. 235-240, Toronto, 2004

Placement and Routing Optimization for Circuits Derived from BDDs
Author: Thomas Eschbach, Rolf Drechsler, Bernd Becker
Conference: IEEE International Symposium on Circuits and Systems (ISCAS'04)
Pdf | Reference: Vancouver, 2004

Managing Don't Cares in Boolean Satisfiability
Author: Sean Safarpour, Andreas Veneris, Rolf Drechsler, Joanne Hang
Conference: IEEE Design, Automation and Test in Europe
Pdf | Reference: Vol. I, pp. 260-265, Paris, 2004

Improving Simulation-Based Verification by Means of Formal Methods
Author: Görschwin Fey, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
Pdf | Reference: pp. 640-643, Yokohama, 2004

Minimization of the Expected Path Length in BDDs Based on Local Changes
Author: Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
Pdf | Reference: pp. 866-871, Yokohama, 2004

Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization
Author: Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler
Conference: Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004)
Pdf | Reference: pp. 876-879, Yokohama, 2004

Hardware Project Management – What we Can Learn from the Software Development Process for Hardware Design?
Author: Rolf Drechsler, Andreas Breiter
Conference: 4th Conference of Informatics and Information Technologies
Reference: Bitola, 2003

Minimizing the Number of One-Paths in BDDs by an Evolutionary Algorithm
Author: Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler
Conference: Congress on Evolutionary Computation 2003 (CEC2003)
Pdf | Reference: Vol.3, pp. 1724-1731, Canberra, 2003

Testability of SPP Three-Level Logic Networks
Author: Valentina Ciriani, Anna Bernasconi, Rolf Drechsler
Conference: IFIP International Conference on Very Large Scale Integration (VLSI'03)
Pdf | Reference: pp. 331-336, Darmstadt, 2003

Exploration of Sequential Depth by Evolutionary Algorithms
Author: Nicole Drechsler, Rolf Drechsler
Conference: IFIP International Conference on Very Large Scale Integration (VLSI'03)
Pdf | Reference: pp. 81-85, Darmstadt, 2003

BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
Author: Junhao Shi, Görschwin Fey, Rolf Drechsler
Conference: Twelfth Asian Test Symposium (ATS03)
Reference: pp. 290-293, Xi'an, 2003

Efficient Automatic Visualization of SystemC Designs
Author: Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst
Conference: Forum on Specification & Design Languages (FDL'03)
Pdf | Reference: pp. 646-657, Frankfurt, 2003

Finding Good Counter-Examples to Aid Design Verification
Author: Görschwin Fey, Rolf Drechsler
Conference: First ACM & IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE'2003)
Pdf | Reference: pp. 51-52, Mont Saint-Michel, 2003

Fast Heuristics for the Edge Coloring of Large Graphs
Author: Mario Hilgemeier, Nicole Drechsler and Rolf Drechsler
Conference: Euromicro Symposium on Digital System Design (DSD'2003)
Pdf | Reference: pp. 230-237, Antalya, 2003

MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits
Author: Rolf Drechsler, Junhao Shi and Görschwin Fey
Conference: IEEE Great Lakes Symposium on VLSI (GLSV'03)
Pdf | Reference: p. 80-83, Washington, 2003

Efficient Minimization of Multi-Valued Decision Diagrams for Incompletely Specified Functions
Author: Denis Popel and Rolf Drechsler
Conference: IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Reference: pp. 241-246, Tokyo, 2003

Augmented Sifting for Multiple-Valued Decision Diagrams
Author: Michael Miller and Rolf Drechsler
Conference: IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Pdf | Reference: pp. 375-382, Tokyo, 2003

Modeling Multi-Valued Circuits in SystemC
Author: Daniel Große, Görschwin Fey and Rolf Drechsler
Conference: IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Pdf | Reference: pp. 281-286, Tokyo, 2003

Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques
Author: Görschwin Fey, Sebastian Kinder and Rolf Drechsler
Conference: IEEE International Symposium on Multi-Valued Logic (ISMVL'2003)
Reference: pp. 361-366, Tokyo, 2003

Formal Verification of LTL Formulas for SystemC Designs
Author: Daniel Große, Rolf Drechsler
Conference: IEEE International Symposium on Circuits and Systems (ISCAS'03)
Pdf | Reference: pp. V:245-V:248, Bangkok, 2003

Synthesizing Checkers for On-line Verification of System-on-Chip Designs
Author: Rolf Drechsler
Conference: IEEE International Symposium on Circuits and Systems (ISCAS'03)
Pdf | Reference: pp. IV:748-IV:751, Bangkok, 2003

Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms
Author: Rolf Drechsler and Nicole Drechsler
Conference: 21st IASTED International Multi-Conference Applied Informatics (AI 2003)
Reference: Innsbruck, 2003

Combination of Lower Bounds in Exact BDD Minimization
Author: Rüdiger Ebendt, Wolfgang Günther and Rolf Drechsler
Conference: IEEE Design, Automation and Test in Europe (DATE'03)
Pdf | Reference: pp. 758-763, Munich, 2003

Utilizing BDDs for disjoint SOP minimization
Author: Görschwin Fey and Rolf Drechsler
Conference: IEEE The 45rd Midwest Symposium on Circuits and Systems (MWSCAS'2002)
Reference: volume II, pp. 306-309, Tulsa, 2002

Minimizing the Number of Paths in BDDs
Author: Görschwin Fey and Rolf Drechsler
Conference: 15th Symposium on Integrated Circuits and System Design
Pdf | Reference: pp. 359-364, Porto Alegre, 2002

Crossing Reduction by Windows Optimization
Author: Thomas Eschbach, Wolfgang Günther, Rolf Drechsler and Bernd Becker
Conference: 10th International Symposium on Graph Drawing (GD'2002)
Pdf | Reference: LNCS 2528, pp. 285-294, Irvine, 2002

Reachability Analysis for Formal Verification of SystemC
Author: Rolf Drechsler and Daniel Große
Conference: Euromicro Symposium on Digital System Design (DSD'2002)
Pdf | Reference: pp. 337-340, Dortmund, 2002

Decision Diagrams Optimization Using Copy Properties
Author: Dragan Jankovic, Radomir Stankovic and Rolf Drechsler
Conference: Euromicro Symposium on Digital System Design (DSD'2002)
Pdf | Reference: p. 236-243, Dortmund, 2002

Recursive Bi-Partitioning of Netlists for Large Number of Partitions
Author: Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard and Gerhard Angst
Conference: Euromicro Symposium on Digital System Design (DSD'2002)
Pdf | Reference: pp. 38-44, Dortmund, 2002

JADE: Implementation and Visualization of a BDD Package in JAVA
Author: Rolf Drechsler
Conference: IEEE Design, Automation and Test in Europe (DATE'02) - User Forum
Pdf | Reference: pp. 259, Paris, 2002

Computing Walsh, Arithmetic and Reed-Muller Spectral Decision Diagrams Using Graph Transformations
Author: Whitney Townsend, Mitch Thornton, Rolf Drechsler and Michael Miller
Conference: IEEE Great Lakes Symposium on VLSI (GLSV'02)
Pdf | Reference: pp. 178-183, New York, 2002

Switching Activity Estimation for Finite State Machines for Low Power Synthesis (Poster)
Author: Mikael Kerttu, Per Lindgren, Mitch Thornton and Rolf Drechsler
Conference: IEEE International Symposium on Circuits and Systems (ISCAS'02)
Pdf | Reference: Scottsdale, 2002

Multi-Output Timed Shannon Circuits
Author: Mitch Thorton, Rolf Drechsler and Michael Miller
Conference: IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002)
Pdf | Reference: pp. 47-52, Pittsburgh, 2002

Evaluation of Static Variable Ordering Heuristics for MDD Construction
Author: Rolf Drechsler
Conference: IEEE International Symposium on Multi-Valued Logic (ISMVL'2002)
Pdf | Reference: pp. 254-260, Boston, 2002

On the Construction of Multi-Valued Decision Diagrams
Author: Michael Miller and Rolf Drechsler
Conference: IEEE International Symposium on Multi-Valued Logic (ISMVL'2002)
Pdf | Reference: pp. 245-253, Boston, 2002

Efficient Calculation of Fixed-Polarity Polynomial Expressions for Multi-Valued Logic Functions
Author: Dragan Jankovic, Radomir Stankovic and Rolf Drechsler
Conference: IEEE International Symposium on Multi-Valued Logic (ISMVL'2002)
Pdf | Reference: pp. 76-82, Boston, 2002

On the Relation Between SAT and BDDs for Equivalence Checking
Author: Sherif Reda, Rolf Drechsler and Alex Orailoglu
Conference: International Symposium on Quality of Electronic Design (ISQED 2002)
Pdf | Reference: pp. 394-399, San Jose, 2002

RTL-Datapath Verification using Integer Linear Programming
Author: Raik Brinkmann and Rolf Drechsler
Conference: IEEE VLSI Design'02 & Asia and South Pacific Design Automation Conference
Pdf | Reference: pp. 741-746, Bangalore, 2002

Fast and Efficient Equivalence Checking based on NAND-BDDs
Author: Rolf Drechsler and Mitch Thornton
Conference: IFIP International Conference on Very Large Scale Integration (VLSI'01)
Pdf | Reference: pp. 401-405, Montpellier, 2001

Formal Verification on Register Transfer Level - Utilizing High-Level Information for Hardware Verification
Author: Peer Johannsen and Rolf Drechsler
Conference: IFIP International Conference on Very Large Scale Integration (VLSI'01)
Pdf | Reference: pp. 127-132, Montpellier, 2001

How Can Generative AI Curate the User Creativity on an Idea Crowdsourcing Platform?
Author: Sana Hassan Imam, Christopher Alexander Metz, Rolf Drechsler
Workshop: ACM CHI 24 workshop on Generative AI in User-Generated Content
Reference: Hawaii & Virtual, 2024

Enhancing Resilience against Sequential Attacks on Logic Locking using Evolutionary Strategies
Author: Marcel Merten, Mohammed E. Djeridane, Muhammad Hassan, Niladri Bhattacharjee, Jens Trommer, Thomas Mikolajick, Rolf Drechsler
Workshop: GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Darmstadt, Germany, 2024

An Evolutionary Approach to Reconfigurable Scan Network Design
Author: Payam Habiby, Fatemeh Shirinzadeh und Rolf Drechsler
Workshop: GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Darmstadt, Germany, 2024

LLM-Assisted High Quality Invariants Generation for Formal Verification
Author: Khushboo Qayyum, Sallar Ahmadi-Pour, Muhammad Hassan, Chandan Kumar Jha, Rolf Drechsler
Workshop: University Fair at Design, Automation and Test in Europe (DATE)
Reference: Valencia, Spain, 2024

Towards Completeness: Security Coverage for System Level IFT
Author: Ece Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Landau, Germany, 2024

Towards ML-based Performance Estimation of Embedded Software: A RISC-V Case Study
Author: Weiyan Zhang, Muhammad Hassan, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Landau, Germany, 2024

Workshop: „Aktuelle Entwicklungen und Perspektiven (an Hochschulen) im Bereich Data Science“
Author: Lena Steinmann, Dirk Nowotka, Lea Oberländer, Helen Pfuhl, Heiner Stuckenschmidt und Rolf Drechsler
Workshop: INFORMATIK 2023
Pdf | Reference: Berlin, Deutschland, 2023

Data Train – The Cross-disciplinary Training in Research Data Management and Data Science
Author: Tanja Hörner, Maya Dalby, Frank Oliver Glöckner, Rolf Drechsler, Iris Pigeot
Workshop: Aktuelle Entwicklungen und Perspektiven auf INFORMATIK 2023
Reference: Berlin, Deutschland, 2023

Establishing discipline-specific Data Stewardship at the Data Science Center of the University of Bremen – One Year Review
Author: Sandra Zänkert, Heike Thöricht, Lena Steinmann, Rolf Drechsler
Workshop: Data Stewardship goes Germany
Reference: Dresden, Germany, 2023

Automated Testing of Stateful Network Protocol Implementations in the IoT
Author: Sören Tempel, Rolf Drechsler
Workshop: RIOT Summit
Video | Reference: Frankfurt, Germany, 2023

Polynomial Formal Verification exploiting Constant Cutwidth
Author: Mohamed Nadeem, Jan Kleinekathöfer, Rolf Drechsler
Workshop: International Workshop on Rapid System Prototyping (RSP)
Pdf | Reference: Hamburg, Germany, 2023

Classifying Crowdsouring Platform Users’ Engagement Behaviour using Machine Learning and XAI
Author: Sana Hassan Imam, Christopher Metz, Lars Hornuf, Rolf Drechsler
Workshop: Workshop on User-Centered Artificial Intelligence (UCAI'23)
Pdf | Reference: Rapperswil, Switzerland, 2023

Automated Formal Verification Methodology for MAGIC Design Style Based In-Memory Computing
Author: Chandan Kumar Jha, Khushboo Qayyum, Kemal Çağlar Coşkun, Simranjeet Singh, Muhammad Hassan, Rainer Leupers, Farhad Merchant, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: EPFL, Lausanne, Switzerland, 2023

Expanding RISC-V Horizons: Streamlining Heterogeneous Systems Evaluation with Open Source RISC-V AMS VP Framework
Author: Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler
Workshop: RISC-V Summit Europe
Pdf | Reference: Barcelona, Spain, 2023

Scale4Edge – Scaling RISC-V for Edge Applications
Author: Wolfgang Ecker, Milos Krstic, Markus Ulbricht, Andreas Mauderer, Eyck Jentzsch, Andreas Koch, Bastian Koppelmann, Wolfgang Mueller, Babak Sadiye, Niklas Bruns, Rolf Drechsler, Daniel Mueller-Gritschneder, Jan Schlamelcher, Kim Grüttner, Jörg Bormann, Wolfgang Kunz, Reinhold Heckmann, Gerhard Angst, Ralf Wimmer, Bernd Becker, Tobias Faller, Paul Palomero Bernardo, Oliver Bringmann, Johannes Partzsch, Christian Mayr
Workshop: RISC-V Summit Europe
Pdf | Reference: Barcelona, Spain, 2023

Polynomial Formal Verification of KFDD Circuits
Author: Martha Schnieber, Rolf Drechsler
Workshop: 2023 Reed-Muller Workshop (RM2023)
Reference: Matsue, Shimane, Japan, 2023

Polynomial Formal Verification of Adder Circuits Using Answer Set Programming
Author: Mohamed Nadeem, Jan Kleinekathöfer and Rolf Drechsler
Workshop: 2023 Reed-Muller Workshop (RM2023)
Pdf | Reference: Matsue, Shimane, Japan, 2023

Fast and Accurate: Machine Learning Techniques for Performance Estimation of CNNs for GPGPUs
Author: Christopher Metz, Mehran Goli, and Rolf Drechsler
Workshop: 5th Workshop on Parallel AI and Systems for the Edge (PAISE)
Pdf | Reference: St. Petersburg, USA, 2023

Security Validation of VP-based Heterogeneous Systems: A Completeness-driven Perspective
Author: Ece Nur Demirhan Coskun, Muhammad Hassan, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Freiburg, Germany, 2023

Equivalence Checking of Majority-based Function Mapping on ReRAM Crossbars
Author: Arighna Deb, Kamalika Datta, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Freiburg, Germany, 2023

Towards Comprehensive Verification of Hardware and Software for RISC-V based Embedded Systems
Author: Niklas Bruns, Sallar Ahmadi-Pour, Sören Tempel, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Freiburg, Germany, 2023

Divider Verification Using Symbolic Computer Algebra and Delayed Don’t Care Optimization
Author: Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: Freiburg, Germany, 2023

Remote Configuration Methodology for IEEE 1687 Scan Networks
Author: Payam Habiby, Sebastian Huhn and Rolf Drechsler
Workshop: 35. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Erfurt, Germany, 2023

New Directions for Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits
Author: Kemal Çağlar Coşkun, Muhammad Hassan and Rolf Drechsler
Workshop: 35. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Erfurt, Germany, 2023

How Secure Is A Circuit Against Optical Probing? Developed Countermeasures, In Progress Countermeasures Development, and the Future Works
Author: Sajjad Parvin, Frank Sill Torres and Rolf Drechsler
Workshop: 11th International Workshop on Cryptography, Robustness, and Provably Secure Schemes for Female Young Researchers (CrossFyre)
Reference: Passau, Germany, 2022

OPTI-RISK: Design of an Optical Probing Attack Hardened RISC-V Core with an Industrially Compatible CMOS Gate Library
Author: Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, and Rolf Drechsler
Workshop: 5th RISC-V Activity Workshop
Reference: Berlin, Germany, 2022

ANN-based Performance Estimation of Embedded Software for RISC-V Processors
Author: Weiyan Zhang, Mehran Goli, Alireza Mahzoon, Rolf Drechsler
Workshop: International Workshop on Rapid System Prototyping (RSP)
Pdf | Reference: Hamburg, Germany, 2022

HLS-ing Up RISC-V: Streamlining Design and Optimization
Author: Deepak Ravibabu, Muhammad Hassan and Rolf Drechsler
Workshop: University Fair at Design, Automation and Test in Europe (DATE)
Reference: Antwerpen, Belgien, 2023

Symbolic Execution for RISC-V Embedded Software Using SystemC Peripheral Models
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Workshop: 3rd International KLEE Workshop on Symbolic Execution
Video | Reference: London, 2022

Automated Testing of RIOT modules using SymEx-VP
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Workshop: RIOT Summit
Video | Reference: Hamburg, Germany, 2022

One is not Enough: Using Hybrid Proof Engines for Polynomial Formal Verification
Author: Rolf Drechsler, Alireza Mahzoon
Workshop: 24th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)
Reference: Hirosaki, Japan, 2022

Mapping Quantum Circuits to 2-D Quantum Architectures
Author: Kamalika Datta, Abhoy Kole, Indranil Sengupta and Rolf Drechsler
Workshop: GI Quantum Computing Workshop 2022 (GI QC 22)
Pdf | Reference: Hamburg, Germany, 2022

SAT-based Key Determination Attack for Improving the Quality Assessment of Logic Locking Mechanisms
Author: Marcel Merten, Mohammed E. Djeridane, Sebastian Huhn, Rolf Drechsler
Workshop: 15th International Workshop on Boolean Problems (IWSBP)
Pdf | Reference: Bremen, Germany, 2022

Towards System-level Assertions for Heterogeneous Systems
Author: Muhammad Hassan, Thilo Voertler, Karsten Einwich, Rolf Drechsler,Daniel Grosse
Workshop: 15th International Workshop on Boolean Problems (IWSBP)
Pdf | Reference: Bremen, Germany, 2022

Feature Importance and Extensibility for Predicting Loan Defaults in Marketplace Lending using BiLSTM
Author: Sana Hassan Imam, Sebastian Huhn, Lars Hornuf, Rolf Drechsler
Workshop: Frontiers of Factor Investing Conference (FoFi)
Reference: Lancaster, UK, 2022

Polynomial Formal Verification of Approximate Adders
Author: Martha Schnieber, Saman Fröhlich, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: Virtual Conference , 2022

Polynomial Formal Verification of Complex Multipliers
Author: Alireza Mahzoon, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: Virtual, 2022

Self-Explanation in Systems of Systems
Author: Goerschwin Fey, Martin Fränzle and Rolf Drechsler
Workshop: Second International Workshop on Requirements Engineering for Explainable Systems (RE4ES)
Reference: Melbourne, Victoria, Australia (virtual event with a local hub), 2022

Simulation-based Verification of SystemC-based VPs at the ESL
Author: Mehran Goli, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Virtual, 2022

RISC-V Processor Verification with Coverage-guided Aging
Author: Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Virtual, 2022

System Level Verification of Analog/Mixed-Signal Systems using Metamorphic Relations
Author: Muhammad Hassan and Rolf Drechsler
Workshop: 34. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Bremerhaven, Germany, 2022

Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods
Author: Marcel Merten, Sebastian Huhn and Rolf Drechsler
Workshop: 34. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Bremerhaven, Germany, 2022

An ILP-based Global Optimum Test Scheduler for IEEE 1687 Multi-Power Domain Networks
Author: Payam Habiby, Sebastian Huhn and Rolf Drechsler
Workshop: 34. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Bremerhaven, Germany, 2022

Verification of RISC-V Embedded Software by Integrating Concolic Testing with SystemC-based Virtual Prototypes
Author: Sören Tempel, Vladimir Herdt, Rolf Drechsler
Workshop: 4th Workshop on RISC-V Activities
Reference: Virtual Conference, 2021

Polynomial Formal Verification of Prefix Adders
Author: Alireza Mahzoon, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: Virtual Conference, 2021

Polynomial Formal Verification of Area-efficient and Fast Adders
Author: Alireza Mahzoon, Rolf Drechsler
Workshop: 2021 Reed-Muller Workshop (RM2021)
Pdf | Video | Reference: Nursultan, Kazakhstan, 2021

MicroRV32: An Open Source RISC-V Cross-Level Platform for Education and Research
Author: Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Workshop: Design Automation for CPS and IoT (DESTION)
Pdf | Reference: Nashville, USA, 2021

GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools
Author: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: München, Germany, 2021

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion
Author: Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: München, Germany, 2021

VP-based DIFT for Embedded Binaries: A RISC-V Case Study
Author: Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: München, Germany, 2021

MicroRV32: A SpinalHDL based RISC-V Implementation for FPGAs
Author: Sallar Ahmadi-Pour, Vladimir Herdt and Rolf Drechsler
Workshop: University Booth at Design, Automation and Test in Europe (DATE)
Pdf | Reference: Grenoble, France, 2021

Efficient Techniques to Boost RISC-V Compliance Testing
Author: Vladimir Herdt and Rolf Drechsler
Workshop: Workshop on Interdependent Challenges of Reliability, Security and Quality (RESCUE)
Reference: Grenoble, France, 2021

A Memory-Upscaled Boolean Satisfiability Solver for Complex On-Chip Self-Verification Tasks
Author: Buse Ustaoglu, Sebastian Huhn and Rolf Drechsler
Workshop: Workshop on Interdependent Challenges of Reliability, Security and Quality (RESCUE)
Pdf | Reference: Grenoble, France, 2021

Pick the Right Edge Device: Towards Power and Performance Estimation of CUDA-based CNNs on GPGPUs
Author: Christopher Metz, Mehran Goli, Rolf Drechsler
Workshop: System-level Design Methods for Deep Learning on Heterogeneous Architectures (SLOHA)
Pdf | Reference: Grenoble, France, 2021

Test Scheduling Optimization Model for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability
Author: Payam Habiby, Sebastian Huhn and Rolf Drechsler
Workshop: 33. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Nordhausen, Germany, 2021

SAT-based Exact Physical Design for Field-coupled Nanocomputing Technologies
Author: Marcel Walter, Winston Haaswijk, Robert Wille, Frank Sill Torres, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: San Francisco, USA, 2020

Fuzz-Testing RISC-V Simulators
Author: Vladimir Herdt, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: Stuttgart, Germany, 2020

Coverage-Directed Stimuli Generation for Characterization of RF Amplifiers
Author: Muhammad Hassan, Daniel Große, Ahmad Asghar, Rolf Drechsler
Workshop: 32. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2020)
Pdf | Reference: Stuttgart, Germany, 2020

Power-Layout-Aware Test Pattern Re-scheduling
Author: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Workshop: 32. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2020)
Reference: Stuttgart, Germany, 2020

Integrating Hybrid Analysis with Machine Learning Techniques for Portion Resilience Evaluation in Approximating SystemC-based Designs
Author: Mehran Goli, Rolf Drechsler
Workshop: Workshop on Machine Learning for CAD (MLCAD)
Reference: Canmore (Banff Area), Alberta, Canada, 2019

GenMul: Generating architecturally complex multipliers to challenge formal verification tools
Author: Alireza Mahzoon, Daniel Große, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: Lausanne, Switzerland, 2019

fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits
Author: Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: Lausanne, Switzerland, 2019

Self-Explaining Digital Systems – Some Technical Steps
Author: Goerschwin Fey and Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Pdf | Reference: Kaiserslautern, Germany, 2019

Towards Gate-Level Design of QCA Circuits
Author: Philipp Niemann, Igor Kazhdan, Frank Sill Torres, Rolf Drechsler
Workshop: 6th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Florence, Italy, 2019

Enhanced Embedded Test Compression Technique For Processing Incompressible Test Patterns
Author: Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler
Workshop: 31. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Prien am Chiemsee, Germany, 2019

IR-drop Prediction of Test Patterns Using Parasitic Elements
Author: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler
Workshop: 31. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2019)
Reference: Prien am Chiemsee, Germany, 2019

Optimizing Ts in the Synthesis of Clifford+T Quantum Circuits
Author: Philipp Niemann, Robert Wille, Rolf Drechsler
Workshop: 2nd International Workshop on Quantum Compilation (IWQC, co-located with ICCAD)
Reference: San Diego, CA, USA, 2018

Improving SAT solving using Monte Carlo Tree Search-based Clause Learning
Author: Oliver Keszöcze, Kenneth Schmitz, Jens Schloeter, Rolf Drechsler
Workshop: 13th International Workshop on Boolean Problems (IWSBP)
Reference: Bremen, Germany, 2018

ConfidenceSat: A Parallel SAT Solver with Conflict Clause Handling
Author: Kenneth Schmitz, Oliver Keszöcze, Jil Tietjen and Rolf Drechsler
Workshop: 13th International Workshop on Boolean Problems (IWSBP)
Reference: Bremen, Germany, 2018

A Document-oriented, Heterogeneous Database Model for Large Experimental Data Sets
Author: Timo Kohorst and Sebastian Huhn and Rolf Drechsler
Workshop: MAPEX Symposium
Pdf | Reference: Bremen, Germany, 2018

Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation
Author: Rolf Drechsler, Christoph Lüth, Goerschwin Fey, Tim Güneysu
Workshop: 3nd International Verification and Security Workshop (IVSW)
Pdf | Reference: Costa Brava, Spain, 2018

Evaluation of Power State Cross Coverage in Firmware-Based Power Management
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: Embedded Software for Industrial IoTs (ESIIT)
Reference: Dresden, Germany, 2018

Time-stamps for Hardware Simulation Models Accurate Time-back Annotation
Author: Rehab Massoud, Jannis Stoppe, Karthik Maddikunta, Rolf Drechsler
Workshop: 5th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Dresden, Germany, 2018

Execution Environment for Dynamic Software Runtime Examination
Author: Kenneth Schmitz, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Workshop: 5th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Dresden, Germany, 2018

A Codeword-based Compaction Technique for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks
Author: Sebastian Huhn, Marcel Merten, Stephan Eggersglüß and Rolf Drechsler
Workshop: 30. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Freiburg (Breisgau), Germany, 2018

ATPG Constraint Analysis for Reducing Regional Power Activity
Author: Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen
Workshop: 30. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ 2018)
Reference: Freiburg (Breisgau), Germany, 2018

Towards Automated Refinement of TLM Properties to RTL
Author: Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: Tübingen, Germany, 2018

Revisiting Symbolic Software-implemented Fault Injection
Author: Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler
Workshop: 2nd International Workshop on Resiliency in Embedded Electronic Systems (REES)
Reference: Lausanne, Switzerland, 2017

Making Waveforms Great Again
Author: Jannis Stoppe and Rolf Drechsler
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Lausanne, Switzerland, 2017

A Human-Centered Approach to Routing for Digital Microfluidic Biochips
Author: Oliver Keszöcze, Andre Pols and Rolf Drechsler
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Lausanne, Switzerland, 2017

Verilog2GEXF - Dynamic Large Scale Circuit Visualization
Author: Kenneth Schmitz, Jannis Stoppe, Rolf Drechsler
Workshop: 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Lausanne, Switzerland, 2017

Der Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips
Author: Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: Bremen, Germany, 2017

Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing
Author: Saman Fröhlich, Daniel Große, Rolf Drechsler
Workshop: Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: pp. 27-38, Bremen, Germany, 2017

Using Lightweight Containers in Hardware/Software Co-Design for Security
Author: Daniel Große, Kenneth Schmitz, Rolf Drechsler
Workshop: Workshop on Computer-Aided Design and Implementation for Cryptography and Security (CADICS)
Reference: Austin, USA, 2016

Integrating an SMT-based Model Finder into USE
Author: Nils Przigoda, Frank Hilken, Judith Peters, Robert Wille, Martin Gogolla, Rolf Drechsler
Workshop: Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Reference: Saint-Malo, France, 2016

On the computational complexity of error metrics in approximate computing
Author: Oliver Keszöcze, Mathias Soeken, Rolf Drechsler
Workshop: International Workshop on Boolean Problems
Reference: Freiberg, Germany, 2016

SystemCDG - AI Based Coverage Driven Stimuli Generation for SystemC
Author: Jannis Stoppe, Arved Friedemann, Rolf Drechsler
Workshop: International Workshop on Logic & Synthesis (IWLS)
Reference: Austin, TX, USA, 2016

Synthesis of Optical Circuits with Contradictory Optimization Objectives
Author: Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler
Workshop: The 2nd International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS Workshop)
Reference: Dresden, Germany, 2016

Change Management for Hardware Designers
Author: Martin Ring, Jannis Stoppe, Christoph Lüth, Rolf Drechsler
Workshop: Workshop on Design Automation for Understanding Hardware Designs (DUHDE)
Reference: Dresden, Germany, 2016

Visualizing Microfluidic Biochips Interactively
Author: Jannis Stoppe, Oliver Keszöcze, Robert Wille, Rolf Drechsler
Workshop: Workshop on Design Automation for Understanding Hardware Designs (DUHDE)
Reference: Dresden, Germany, 2016

Leichtgewichtige Datenkompressions-Architektur für IEEE 1149.1-kompatible Testschnittstellen
Author: Sebastian Huhn, Stephan Eggersglüß and Rolf Drechsler
Workshop: 28. GI/GMM/ITG Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Pdf | Reference: Siegen, Germany, 2016

Symbolic Error Metric Determination for Approximate Computing
Author: Arun Chandrasekharan, Daniel Große, Mathias Soeken, Rolf Drechsler
Workshop: 19. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'16)
Reference: Freiburg, Germany, 2016

Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses
Author: Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop: Workshop on Model-Driven Engineering, Verification, and Validation (MoDeVVa)
Reference: Ottawa, Canada, 2015

Towards Generating Test Suites with High Functional Coverage for Error Effect Simulation
Author: Aljoscha Windhorst, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 1st International ESWEEK Workshop on Resiliency in Embedded Electronic Systems
Reference: Amsterdam, The Netherlands, 2015

Simulation Graphs for Reverse Engineering
Author: Baruch Sterin, Mathias Soeken, Rolf Drechsler, Robert K. Brayton
Workshop: International Workshop on Logic Synthesis (IWLS)
Reference: Mountain View, CA, USA, 2015

Quo Vadis, Reversible Circuit Design? Towards Scaling Design and Synthesis of Reversible Circuits
Author: Eleonora Schönborn, Robert Wille, Rolf Drechsler
Workshop: Reed-Muller Workshop
Reference: Waterloo, Canada, 2015

Fehlereffektsimulation mittels virtueller Prototypen
Author: Sebastian Reiter, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Rolf Drechsler, Wolfgang Ecker, Thomas Kruse, Christoph Kuznik, Jo Laufenberg, Hoang M. Le, Petra Maier, Daniel Müller-Gritschneder, Hendrik Post, Jan-Hendrik Oetjens, Wolfgang Rosenstiel, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl
Workshop: GI/GMM/ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference: Bad Urach, 2015

Verbesserung der Fehlersuche in inkonsistenten formalen Modellen
Author: Nils Przigoda, Robert Wille, Rolf Drechsler
Workshop: 18. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'15)
Reference: Chemnitz, Germany, 2015

Ecore Model Generation from SystemC/C++ Implementations
Author: Jannis Stoppe, Rolf Drechsler
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs (DUHDe)
Reference: Grenoble, France, 2015

Coverage at the Formal Specification Level
Author: Rolf Drechsler, Julia Seiter, Mathias Soeken
Workshop: International Workshop on Design and Implementation of Formal Tools and Systems (DIFTS)
Reference: Lausanne, Switzerland, 2014

A framework for reversible circuit complexity
Author: Mathias Soeken, Nabila Abdessaied, Rolf Drechsler
Workshop: 10th International Workshop on Boolean Problems
Pdf | Reference: Freiberg, Germany, post-print available at arXiv:1407.5878, 2014

Towards a Multi-dimensional and Dynamic Visualization for ESL Designs
Author: Jannis Stoppe, Marc Michael, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop: DATE Friday Workshop: Design Automation for Understanding Hardware Designs
Reference: Dresden, Germany, 2014

Formale Methoden für Alle
Author: Mathias Soeken, Max Nitze, Rolf Drechsler
Workshop: 17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Reference: Böblingen, Germany, 2014

Funktionale Abdeckungsanalyse von C-Programmen
Author: Aljoscha Windhorst, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Reference: pp. 201-204, Böblingen, Germany, 2014

A Logic for Cardinality Constraints
Author: Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey
Workshop: 17. ITG/GMM/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV'14)
Reference: Böblingen, Germany, 2014

Hohe Testmengenkompaktierung durch formale Optimierungstechniken
Author: Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Workshop: Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ)
Reference: Bad Staffelstein, 2014

Using Optimization Techniques to Increase Test Compaction
Author: Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler
Workshop: IEEE 14th Workshop on RTL and High Level Testing (WRTLT'13)
Reference: Yilan, Taiwan, 2013

Law-based Verification for Complex Swarm Systems
Author: Rolf Drechsler, Hoang M. Le, Mathias Soeken, Robert Wille
Workshop: International Workshop on the Swarm at the Edge of the Cloud
Reference: Montreal, Canada, 2013

lips: An IDE for Model Driven Engineering Based on Natural Language Processing
Author: Oliver Keszöcze, Mathias Soeken, Eugen Kuksa, Rolf Drechsler
Workshop: Workshop on Natural Language Analysis in Software Engineering (NaturaLiSE)
Pdf | Reference: pp. 31-38, San Francisco, 2013

Towards Automatic Scenario Generation from Coverage Information
Author: Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
Workshop: 8th International Workshop on Automation of Software Test (AST)
Pdf | Reference: pp. 82-88, San Francisco, 2013

SystemC Verifikation mittels symbolischer Simulation einer Zwischensprache
Author: Hoang M. Le, Daniel Große, Vladimir Herdt, Rolf Drechsler
Workshop: edaWorkshop
Pdf | Reference: pp. 53-58, Dresden, Germany, 2013

Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen
Author: Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler
Workshop: 16. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: Rostock, Germany, 2013

Verification of Embedded Systems Using Modeling and Implementation Languages
Author: Mathias Soeken, Heinz Riener, Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop: International Workshop on Metamodelling and Code Generation for Embedded Systems (MeCoEs'12)
Pdf | Reference: pp. 67-72, Tampere, Finland, 2012

Towards Increasing Test Compaction Abilities of SAT-based ATPG through Fault Detection Constraints
Author: Stephan Eggersglüß, Melanie Diepenbeck, Robert Wille, Rolf Drechsler
Workshop: IEEE 13th Workshop on RTL and High Level Testing (WRTLT'12)
Pdf | Reference: Niigata, Japan, 2012

Behavior Driven Development for Circuit Design and Verification
Author: Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler
Workshop: IEEE International Workshop on High-Level Design Validation and Test (HLDVT)
Pdf | Reference: pp. 9-16, Huntington Beach, USA, 2012

Towards Embedding of Large Functions for Reversible Logic
Author: Mathias Soeken, Robert Wille, Laura Tague, D. Michael Miller, Rolf Drechsler
Workshop: International Workshop on Boolean Problems
Reference: Freiberg, 2012

Using πDDs in the Design for Reversible Circuits
Author: Mathias Soeken, Robert Wille, Shin-Ichi Minato, Rolf Drechsler
Workshop: Workshop on Reversible Computation
Reference: Kopenhagen, 2012

Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams
Author: Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop: Workshop on Reversible Computation
Reference: Kopenhagen, 2012

Design Understanding by Feature Localization on ESL
Author: Marc Michael, Daniel Große, Rolf Drechsler
Workshop: 9. GMM/ITG/GI-Workshop Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS)
Reference: pp. 19-24, Dresden, 2012

Compilation of Methodologies to Speed up the Verification Process at System Level
Author: Stephan Radke, Steffen Rülke, Marcio F. S. Oliveira, Christoph Kuznik, Wolfgang Müller, Wolfgang Ecker, Volkan Esen, Simon Hufnagel, Nico Bannow, Helmut Brazdrum, Peter Janssen, Hoang M. Le, Daniel Große, Rolf Drechsler, Erhard Fehlauer, Gernot Koch, Andreas Burger, Oliver Bringmann, Wolfgang Rosenstiel, Finn Haedicke, Ralph Görgen, Jan-Hendrik Oetjens
Workshop: edaWorkshop
Reference: pp. 57-62, Hannover, 2012

SystemC-based ESL Verification Flow Integrating Property Checking and Automatic Debugging
Author: Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: DATE Friday Workshop: OSCI and Accellera Core Technologies for the Next Generation of System-Level Design
Reference: Dresden, 2012

CRAVE: An Advanced Constrained Random Verification Environment for SystemC
Author: Finn Haedicke, Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 15. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
Reference: pp. 37-48, Kaiserslautern
Software and benchmarks available at www.systemc-verification.org, 2012

Towards Proving TLM Properties with Local Variables
Author: Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 7th International Workshop on Constraints in Formal Verification (CFV)
Pdf | Reference: San Jose, 2011

Towards Automatic Determination of Problem Bounds for Object Instantiation in Static Model Verification
Author: Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop: Model-Driven Engineering, Verification, And Validation (MoDeVVa)
Reference: Wellington, 2011

metaSMT: Focus on Your Application not on Solver Integration
Author: Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler
Workshop: DIFTS'11: 1st International workshop on design and implementation of formal tools and systems
Pdf | Reference: pp. 22-29, Austin, USA, 2011

Synthesis of Reversible Circuits with Minimal Lines for Large Functions
Author: Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler
Workshop: Workshop on Reversible Computation
Reference: pp. 59-70, Gent, 2011

Customized Design Flows for Reversible Circuits Using RevKit
Author: Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Workshop: Workshop on Reversible Computation
Reference: pp. 91-96, Gent, 2011

Formal Analysis Techniques: A Basis for High-Quality Designs
Author: Stephan Eggersglüß, Rolf Drechsler
Workshop: IEEE International Workshop on Processor Verification, Test and Debug
Pdf | Reference: Invited Talk, Trondheim, 2011

On Timing-Aware ATPG using Pseudo-Boolean Optimization
Author: Stephan Eggersglüß, Rolf Drechsler
Workshop: IEEE European Test Symposium (ETS), Informal Digest of Papers
Pdf | Reference: Trondheim, 2011

Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines
Author: Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler
Workshop: SORT 2011: 2nd IEEE Workshop on Self-Organizing Real-Time Systems
Reference: pp. 181-188, Newport Beach, 2011

Improving ESOP-based Synthesis of Reversible Logic Using Evolutionary Algorithms
Author: Rolf Drechsler, Alexander Finder, Robert Wille
Workshop: 6th European Workshop on Hardware Optimization Techniques (EvoHOT)
Pdf | Reference: Applications of Evolutionary Computation, LNCS 6625, pp. 151-161, Turin, 2011

Protocol Compliance Checking of SystemC TLM Models
Author: Mohamed Bawadekji, Daniel Große, Rolf Drechsler
Workshop: 8. GMM/ITG/GI-Workshop Cyber-Physical Systems – Enabling Multi-Nature Systems (CPMNS)
Reference: pp. 27-32, Bremen, 2011

Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction
Author: Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler
Workshop: 14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: pp. 269-278, Oldenburg, 2011

Designing a RISC CPU in Reversible Logic
Author: Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler
Workshop: 14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: pp. 249-258, Oldenburg, 2011

Towards Automatic Property Generation for the Formal Verification of Bus Bridges
Author: Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler
Workshop: 14. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: Oldenburg, 2011

As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization
Author: Stephan Eggersglüß, Rolf Drechsler
Workshop: 23. GI/GMM/ITG Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2011
Pdf | Reference: Passau, 2011

SAT-based ATPG for Reversible Circuits
Author: Hongyan Zhang, Robert Wille, Rolf Drechsler
Workshop: 5th International Design & Test Workshop (IDT)
Reference: pp. 149-154, Abu Dhabi, 2010

Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition
Author: Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop: 5th International Design & Test Workshop (IDT)
Pdf | Reference: pp. 143-148, Abu Dhabi, 2010

Automatic Fault Localization for SystemC TLM Designs
Author: Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: 11th International Workshop on Microprocessor Test and Verification (MTV)
Pdf | Reference: pp. 35-40, Austin, Texas, 2010

Towards Unifying Localization and Explanation for Automated Debugging
Author: Görschwin Fey, André Sülflow, Rolf Drechsler
Workshop: 11th International Workshop on Microprocessor Test and Verification (MTV)
Pdf | Reference: pp. 3-8, Austin, Texas, 2010

RevKit: A Toolkit for Reversible Circuit Design
Author: Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
Workshop: Workshop on Reversible Computation
Pdf | Reference: pp. 69-72, Bremen, 2010

Hierarchical Synthesis of Reversible Circuits Using Positive and Negative Davio Decomposition
Author: Mathias Soeken, Robert Wille, Rolf Drechsler
Workshop: Workshop on Reversible Computation
Reference: pp. 55-58, Bremen, 2010

Towards Analyzing Functional Coverage in SystemC TLM Property Checking
Author: Hoang M. Le, Daniel Große, Rolf Drechsler
Workshop: IEEE International Workshop on High-Level Design Validation and Test (HLDVT)
Pdf | Reference: pp. 67-74, Anaheim, 2010

SyReC: A Programming Language for Synthesis of Reversible Circuits
Author: Robert Wille, Sebastian Offermann, Rolf Drechsler
Workshop: International Workshop on Logic Synthesis (IWLS)
Reference: Irvine, 2010

Technische Dokumentation im V-Modell XT
Author: Beate Kapturek, Rolf Drechsler
Workshop: 17. Workshop der Fachgruppe WI-VM der Gesellschaft für Informatik e.V.
Pdf | Reference: Stuttgart, 2010

RobuCheck: A Robustness Checker for Digital Circuits
Author: Stefan Frehse, Görschwin Fey, Andre Sülflow and Rolf Drechsler
Workshop: The First International Workshop on Dynamic Aspects in Dependability Models for Fault-Tolerant Systems (DYADEM-FTS)
Reference: Valencia, 2010

VisSAT: Visualization of SAT Solver Internals
Author: Robert Wille, Andre Sülflow, Christian Genz, Rolf Drechsler
Workshop: University Booth at Design, Automation and Test in Europe (DATE10)
Pdf | Reference: Dresden, 2010

A Better-Than-Worst-Case Robustness Measure
Author: Stefan Frehse, Görschwin Fey, Rolf Drechsler
Workshop: 22. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2010
Pdf | Reference: Paderborn, 2010

SyReC: A Programming Language for Synthesis of Reversible Circuits
Author: Robert Wille, Sebastian Offermann, Rolf Drechsler
Workshop: 13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: Dresden, 2010

Verifying UML/OCL Models Using Boolean Satisfiability
Author: Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler
Workshop: 13. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: pp. 57-66, Dresden, 2010

Induction-based Formal Verification of SystemC TLM Designs
Author: Daniel Große, Hoang M. Le, Rolf Drechsler
Workshop: 10th International Workshop on Microprocessor Test and Verification (MTV)
Reference: pp. 101-106, Austin, Texas, 2009

Using QBF to Increase the Accuracy of SAT-Based Debugging
Author: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: International Workshop on Constraints in Formal Verification (CFV)
Pdf | Reference: Grenoble, France, 2009

Reducing Reversible Circuit Cost by Adding Lines
Author: D. Michael Miller, Robert Wille, Rolf Drechsler
Workshop: International Workshop on Logic Synthesis (IWLS)
Reference: Berkeley, 2009

Synthesis of Reversible Functions Beyond Gate Count and Quantum Cost
Author: Robert Wille, Mehdi Saeedi, Rolf Drechsler
Workshop: International Workshop on Logic Synthesis (IWLS)
Pdf | Reference: Berkeley, 2009

Model-Based Diagnosis for Programmable Logic Controllers
Author: Andre Sülflow, Rolf Drechsler
Workshop: Gemeinsamer Workshop der Informatik-Graduiertenkollegs und Forschungskollegs
Reference: Dagstuhl, 2009

A Two-Stage SAT-based ATPG Approach with Reduced Switching Activity
Author: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Workshop: Second International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR) 2009
Pdf | Reference: Sevilla, Spain, 2009

Robustness Check for Multiple Faults using Formal Techniques
Author: Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler
Workshop: Constraints in Formal Verification (CFV)
Pdf | Reference: Grenoble, France, 2009

Synthesizing Reversible Logic: An Overview
Author: Robert Wille, Rolf Drechsler
Workshop: Reed-Muller Workshop
Reference: Naha, Okinawa, 2009

FormED: A Formal Environment for Debugging
Author: Andre Sülflow, Robert Wille, Christian Genz, Görschwin Fey, Rolf Drechsler
Workshop: University Booth at Design, Automation and Test in Europe (DATE09)
Pdf | Reference: Nizza, 2009

Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
Author: Robert Wille, Rolf Drechsler
Workshop: Reversible Computation
Reference: York, 2009

A Fast Untestability Proof for SAT-based ATPG
Author: Daniel Tille, Rolf Drechsler
Workshop: 21. Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen - TuZ 2009
Pdf | Reference: Bremen, 2009

Using a Two-Dimensional Fault List for Compact Automatic Test Pattern Generation
Author: Marc Messing, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler
Workshop: 10th IEEE Latin-American TestWorkshop (LATW)
Reference: Búzios, Rio de Janeiro, 2009

Increasing the Accuracy of SAT-based Debugging
Author: Andre Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler
Workshop: 12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Pdf | Reference: pp. 47-56, Berlin, 2009

Equivalence Checking of Reversible Circuits
Author: Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler
Workshop: 12. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: Berlin, 2009

Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow
Author: Ulrich Kühne, Daniel Große, Rolf Drechsler
Workshop: 9th International Workshop on Microprocessor Test and Verification (MTV)
Pdf | Reference: pp. 88-93, Austin, Texas, 2008

Computing Bounds for Fault Tolerance using Formal Techniques
Author: Andre Sülflow, Görschwin Fey, Stefan Frehse, Ulrich Kühne, Rolf Drechsler
Workshop: IEEE Workshop on Design for Reliability and Variability (DRV)
Pdf | Reference: Santa Clara, USA, 2008

Experimental Studies on SMT-based Debugging
Author: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: IEEE 9th Workshop on RTL and High Level Testing (WRTLT'08)
Pdf | Reference: pp. 93-98, Japan, 2008

Reversible Logic Synthesis with Output Permutation
Author: Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler
Workshop: International Workshop on Boolean Problems
Reference: Freiberg, 2008

Effiziente automatische Generierung von Assertions für industrielle Hardware-Designs
Author: Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke
Workshop: Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
Reference: Dresden, 2008

Contradiction Analysis for Constraint-based Random Simulation
Author: Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler
Workshop: Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS)
Reference: pp. 25-30, Dresden, 2008

Robust Tests for Transition Faults with Long Propagation Paths Using Boolean Satisfiability
Author: Stephan Eggersglüß, Daniel Tille, Rolf Drechsler
Workshop: IEEE European Test Symposium (ETS), Informal Digest of Papers
Pdf | Reference: Lago Maggiore, 2008

Formale Modellextraktion von SystemC Entwürfen
Author: Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard
Workshop: edaWorkshop
Pdf | Reference: pp. 7-12, Hannover, 2008

Incremental SAT Instance Generation for SAT-based ATPG
Author: Daniel Tille, Rolf Drechsler
Workshop: 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Pdf | Reference: pp. 68-73, Bratislava, 2008

Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking
Author: Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler
Workshop: 11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Reference: pp. 169-178, Freiburg, 2008

Debugging Design Errors by Using Unsatisfiable Cores
Author: Andre Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler
Workshop: 11. ITG/GMM/GI-Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen"
Pdf | Reference: pp. 159-168, Freiburg, 2008

False Noise Analysis Using Branch & Bound and SAT
Author: Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
Workshop: ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU 2008)
Reference: Monterey, 2008

Improved Circuit-to-CNF Transformation for SAT-based ATPG
Author: Daniel Tille, René Krenz-Bååth, Jürgen Schlöffel, Rolf Drechsler
Workshop: 20. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
Pdf | Reference: Wien, 2008

Evaluation of SAT like Proof Techniques for Formal Verification of Word Level Circuits
Author: Andre Sülflow, Ulrich Kühne, Robert Wille, Daniel Große, Rolf Drechsler
Workshop: IEEE 8th Workshop on RTL and High Level Testing (WRTLT'07)
Pdf | Reference: pp. 31-36, Beijing, P.R.China, 2007

Formal Robustness Checking
Author: Görschwin Fey, Rolf Drechsler
Workshop: Workshop on Constraints in Formal Verification, 2007
Pdf | Reference: Bremen, 2007

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
Author: Rolf Drechsler, Görschwin Fey, Jürgen Schlöffel
Workshop: edaWorkshop 2007
Reference: Hannover, 2007

Parallelisierung von SAT-basierter Testmustergenerierung
Author: Daniel Tille, Robert Wille, Rolf Drechsler
Workshop: 21. Workshop der GI/ITG-Fachgruppe Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS 2007)
Reference: pp. 213-217, Hamburg, 2007

Building Free Binary Decision Diagrams Using SAT Solvers
Author: Robert Wille, Görschwin Fey, Rolf Drechsler
Workshop: 8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007)
Reference: Oslo, 2007

SAT-based ATPG for Path Delay Fault in Industrial Circuits
Author: Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Juergen Schloeffel
Workshop: IEEE European Test Symposium (ETS), Informal Digest of Papers
Reference: Freiburg, 2007

Estimating the Quality of AND-EXOR Optimization Results
Author: Sebastian Kinder, Görschwin Fey and Rolf Drechsler
Workshop: 8th Workshop on Applications of the Reed-Muller Expansion in Circuit Design and Representations and Methodology of Future Computing Technology (RM2007)
Reference: Oslo, 2007

Documentation Driven Software Development for Embedded Systems
Author: Beate Muranko, Rolf Drechsler
Workshop: 14. Workshop der Fachgruppe WI-VM der Gesellschaft für Informatik e.V. Vorgehensmodelle und Projektmanagement - Assessment, Zertifizierung, Akkreditierung -
Pdf | Reference: München, 2007

Studies on Integrating SAT-based ATPG in an Industrial Environment
Author: Daniel Tille, Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Workshop: 19. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
Pdf | Reference: Erlangen, 2007

Instance Generation for SAT-based ATPG
Author: Daniel Tille, Görschwin Fey, Rolf Drechsler
Workshop: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems
Pdf | Reference: Krakau, 2007

Visualized SystemC Debugging
Author: Christian Genz, Frank Rogin, Rolf Drechsler, Steffen Rülke
Workshop: University Booth at Design, Automation and Test in Europe (DATE07)
Pdf | Reference: Nizza, 2007

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
Author: Rolf Drechsler
Workshop: Treffen der ASIM/GI-Fachgruppen "Simulation technischer Systeme" und "Grundlagen und Methoden in Modellbildung und Simulation"
Reference: Bremen, 2007

Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse
Author: Andre Sülflow, Görschwin Fey, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: pp. 101-110, Erlangen, 2007

Formal Verification on the Word Level using SAT-like Proof Techniques
Author: Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference: pp. 165-173, Erlangen, 2007

Efficient Design-Flow for Counting Heads
Author: Sebastian Kinder und Rolf Drechsler
Workshop: 8. Bieleschweig Workshop „Systems Engineering”: Modellbasierte Entwicklung & Human-Centered Engineering
Pdf | Reference: Braunschweig, 2006

Exact Toffoli Network Synthesis of Reversible Logic using Boolean Satisfiability
Author: Daniel Große, Xiaobo Chen, Rolf Drechsler
Workshop: Fifth IEEE Dallas Circuits and Systems Workshop
Reference: pp. 51-54, Dallas, 2006

Complete Formal Verification of Multi Core Embedded Systems using Bounded Model Checking
Author: Ulrich Kühne, Daniel Große, Rolf Drechsler
Workshop: Fifth IEEE Dallas Circuits and Systems Workshop
Reference: pp. 147-150, Dallas, 2006

Efficiency of Multi-Valued Encoding in SAT-based ATPG
Author: Görschwin Fey, Junhao Shi , Rolf Drechsler
Workshop: 18. Workshop „Testmethoden und Zuverlässigkeit von Schaltungen und Systemen“
Reference: Titisee, 2006

Technische Dokumentation von Soft- und Hardware-Systemen: Die vergessene Welt
Author: Beate Muranko, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: Dresden, 2006

SAT-Based Calculation of Source Code Coverage for BMC
Author: Görschwin Fey, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: Dresden, 2006

Efficient Evolutionary Approaches for the Data Ordering Problem with Inversion
Author: Doina Logofatu, Rolf Drechsler
Workshop: 3rd European Workshop on Hardware Optimisation Techniques (EvoHOT)
Reference: LNCS 3907, pp. 320-331, Budapest, 2006

HW/SW Co-Verification of a RISC CPU using Bounded Model Checking
Author: Daniel Große, Ulrich Kühne, Rolf Drechsler
Workshop: 6th International Workshop on Microprocessor Test and Verification (MTV'05)
Pdf | Reference: pp. 133-137, Austin, 2005

Bounded Model Checking mit SystemC
Author: Sebastian Kinder, Rolf Drechsler, Jan Peleska
Workshop: Bieleschweig 6 - Workshop "Systems Engineering"
Reference: Braunschweig, 2005

Bounded Model Checking of Tram Control Systems
Author: Sebastian Kinder, Daniel Große, Jan Peleska, Rolf Drechsler
Workshop: TRain Workshop @ SEFM2005
Reference: Koblenz, 2005

Formale Verifikation des Befehlssatzes eines in SystemC modellierten Mikroprozessors
Author: Daniel Große, Ulrich Kühne, Rolf Drechsler
Workshop: Entwurfsmethoden für Nanometer VLSI Design
Pdf | Reference: pp. 308-312, Bonn, 2005

On the Exact Minimization of Path-Related Objective Functions for BDDs
Author: Rüdiger Ebendt, Rolf Drechsler
Workshop: International Workshop on Logic and Synthesis (IWLS'05)
Pdf | Reference: pp. 333-400, Lake Arrowhead, California, 2005

Acceleration of SAT-based Iterative Property Checking
Author: Daniel Große, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: München, 2005

Modellierung eines Mikroprozessors in SystemC
Author: Daniel Große, Ulrich Kühne, Christian Genz, Frank Schmiedle, Bernd Becker, Rolf Drechsler, Paul Molitor
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: München, 2005

SyCE: An Integrated Environment for System Design in SystemC
Author: Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große
Workshop: 16th IEEE International Workshop on Rapid System Prototyping (RSP)
Pdf | Reference: pp. 258-260, Montreal, 2005

PASSAT: Efficient SAT-based Test Pattern Generation
Author: Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
Workshop: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Reference: Sopron, 2005

Efficient Hierarchical System Debugging for Property Checking
Author: Görschwin Fey, Rolf Drechsler
Workshop: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)
Pdf | Reference: Sopron, 2005

ParSyC: An Efficient SystemC Parser
Author: Görschwin Fey, Daniel Große, Tim Cassens, Christian Genz, Tim Warode, Rolf Drechsler
Workshop: 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004)
Pdf | Reference: pp. 148-154, Kanazawa, 2004

Design Understanding by Automatic Property Generation
Author: Rolf Drechsler, Görschwin Fey
Workshop: 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2004)
Pdf | Reference: pp.274-281, Kanazawa, 2004

Debugging Sequential Circuits Using Boolean Satisfiability
Author: Moayad Ali, Andreas Veneris, Sean Safarpour, Magdy Abadir, Rolf Drechsler, Alexander Smith
Workshop: 5th International Workshop on Microprocessor Test and Verification (MTV'04)
Reference: Austin, 2004

Experimental Studies on Test Pattern Generation for BDD Circuits
Author: Junhao Shi, Görschwin Fey, Rolf Drechsler
Workshop: International Workshop on Boolean Problems (IWSBP)
Pdf | Reference: pp. 71-76, Freiberg, 2004

Towards Formal Verification on the System Level
Author: Rolf Drechsler
Workshop: 15th IEEE International Workshop on Rapid System Prototyping
Pdf | Reference: Invited Talk, pp. 2-5, Geneva, 2004

Visualization of Diagnosis Results for Design Debugging
Author: Görschwin Fey, Rolf Drechsler
Workshop: 13th International Workshop on Post-Binary ULSI Systems
Reference: pp. 1-2, Toronto, 2004

Disjoint Sum of Product Minimization by Evolutionary Algorithms
Author: Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler
Workshop: 1st European Workshop on Hardware Optimisation Techniques (EvoHOT)
Pdf | Reference: Applications of Evolutionary Computing: EvoWorkshops 2004, LNCS 3005, p. 198-207, Coimbra, 2004

Efficient (Non-)Reachability Analysis of Counterexamples
Author: Rolf Drechsler, Wolfgang Günther, Burkhard Stubert
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: pp. 250-259, Kaiserslautern, 2004

Using Synthesis Techniques in SAT Solvers
Author: Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: pp. 165-173, Kaiserslautern, 2004

A Tight Lower Bound for Dynamic BDD Minimization
Author: Rüdiger Ebendt, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Reference: pp. 233-242, Kaiserslautern, 2004

An Approach to Formal Verification of Reconfigurable Systems
Author: Görschwin Fey, Rolf Drechsler, Muazzam Ali
Workshop: 1st IFIP WG 10.5 Workshop on "Frontiers in Automotive Electronics"
Reference: Darmstadt, 2003

BDD-Based Verification of Scalable Designs
Author: Daniel Große, Rolf Drechsler
Workshop: IEEE International High Level Design Validation and Test Workshop (HLDVT'2003)
Pdf | Reference: pp. 123-128, San Francisco, 2003

Random Pattern Testability of Circuits Derived from BDDs
Author: Junhao Shi, Göschwin Fey and Rolf Drechsler
Workshop: 4th Workshop on RTL and High Level Testing(WRTLT'03)
Pdf | Reference: p.70-78, Xi'an, 2003

Synthesizing Checkers for On-line Verification of System-on-Chip Designs
Author: Rolf Drechsler
Workshop: GI/GMM/ITG Fachtagung Entwurf Integrierter Schaltungen (11. E.I.S.-Workshop)
Reference: Erlangen, 2003, page 69, 2003

BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability
Author: Junhao Shi, Görschwin Fey and Rolf Drechsler
Workshop: IEEE European Test Workshop (ETW'03)
Pdf | Reference: pp. 109-110, Maastricht, 2003, 2003

MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits
Author: Rolf Drechsler
Workshop: 15th ITG/GMM/GI Workshop Test methods and Reliability of Circuits and Systems
Reference: Timmendorfer Strand, 2003

BDD Circuit Optimization for Path Delay Fault-Testability
Author: Görschwin Fey, Junhao Shi, Rolf Drechsler
Workshop: 15th ITG/GMM/GI Workshop Test methods and Reliability of Circuits and Systems
Reference: Timmendorfer Strand, 2003 , 2003

A Hybrid Approach Combining Symbolic and Structural Techniques for Disjoint SOP Minimization
Author: Görschwin Fey, Rolf Drechsler
Workshop: 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI'2003)
Reference: pp. 54-60, Hiroshima , 2003

GAME-HDL: Implementation of Evolutionary Algorithms using Hardware Description Languages
Author: Rolf Drechsler, Nicole Drechsler
Workshop: 5th European Workshop on Evolutionary Computation in Image Analysis and Signal Processing (EvoIASP2003)
Pdf | Reference: LNCS 2611, pp. 378-387, Colchester, 2003

Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen
Author: Daniel Große, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: pp. 229-238, Bremen, 2003

Complete BDDs for Fast and Efficient Equivalence Checking, In Workshop on Computational Intelligence and Information Technologies
Author: Rolf Drechsler
Workshop: XXXVII International Scientific Conference on Information Communication and Energy Systems and Technologies (ICEST 2002)
Reference: pp. 741-744, Nis, 2002

Gatecomp: Equivalence Checking of Digital Circuits in an Industrial Environment
Author: Rolf Drechsler, Stefan Höreth
Workshop: International Workshop on Boolean Problems
Pdf | Reference: pp. 195-200, Freiberg, 2002

Low Power Optimization Technique for BDD Mapped Finite State Machines
Author: M. Kerttu, P. Lindgren, Rolf Drechsler, M. Thornton
Workshop: International Workshop on Logic Synthesis (IWLS'2002)
Reference: New Orleans, 2002

Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation
Author: Rolf Drechsler, M. Kerttu, P. Lindgren, M. Thornton
Workshop: International Workshop on System-on-Chip for Real-Time Applications 2002
Reference: Banff, 2002

Symbolic Simulation of Algorithms Specified in HDL
Author: Klaus-Jürgen Englert, Bernd Becker, Rolf Drechsler
Workshop: GI/ITG/GMM-Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: pp. 113 - 122, Tübingen, 2002

Implementation and Visualization of a BDD Package in JAVA
Author: Rolf Drechsler, Jochen Römmler
Workshop: GI/ITG/GMM-Workshop 2002, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Pdf | Reference: pp. 219 - 228, Tübingen, 2002

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