I am the head of the group of computer architecture. The main focus of the group is the development and application of CAD tools in circuit design. The research areas range from system descriptions in SystemC over test and verification down to synthesis. For further information see www.rolfdrechsler.de
Erweiterte virtuelle Prototypen für heterogene Systeme
Formal and Practical Techniques for the Complex System Design Process using Virtual Prototypes
Design für Testbarkeit, Fehlersuche und Zuverlässigkeit
Noerdman Comicbuch
Automatisierte Analyse von virtuellen Prototypen auf der Ebene elektronischer Systeme | Design, Verständnis und Anwendungen
Advanced Boolean Techniques
In-Memory-Computing
Formal Verification of Structurally Complex Multipliers
Verbessertes virtuelles Prototyping
Design Automation for Field-coupled Nanotechnologies
Design for Testability, Debug and Reliability: Next Generation Measures Using Formal Techniques
Recent Findings in Boolean Techniques
Natural Language Processing for Electronic Design Automation
Noch analog oder lebst Du schon?
Enhanced Virtual Prototyping: Featuring RISC-V Case Studies
Automated Analysis of Virtual Prototypes at the Electronic System Level – Design Understanding and Applications
Advanced Boolean Techniques
In-Memory Computing -
Synthesis and Optimization
Information Storage - A Multidisciplinary Perspective
Design Automation Techniques for Approximation Circuits
Exact Design of Digital Microfluidic Biochips
Advanced Logic Synthesis
Formal System Verification
State-of the-Art and Future Trends
Computer: Wie funktionieren Smartphone, Tablet & Co.?
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Automatic Methods for the Refinement of System Models
Reversible and Quantum Circuits
Languages, Design Methods, and Tools for Electronic System Design
Synthese- und Optimierungsverfahren für zukünftige Computerparadigmen
Formal Modeling and Verification of Cyber-Physical Systems
Formal Specification Level
Aspekte der Technischen Informatik
Auf dem Weg zum Quantencomputer - Entwurf reversibler Logik
High Quality Test Pattern Generation and Boolean Satisfiability
Applications of Evolutionary Computation
Towards a Design Flow for Reversible Logic
Debugging at the Electronic System Level
Quality-Driven SystemC Design
Test Pattern Generation using Boolean Proof Engines
Robustness and Usability in Modern Design Flows 
Applications of Evolutionary Computing
Applications of Evolutionary Computing
SATRIX - Algorithmen für Boolesche Erfüllbarkeit
Applications of Evolutionary Computing
Advanced BDD Optimization
Technische Informatik - Eine Einführung
Applications of Evolutionary Computing
FunTaskIC - Eine integrierte Entwurfsumgebung für SystemC
Applications of Evolutionary Computing
Advanced Formal Verification
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Evolutionary Algorithms for Embedded System Design
Software-Engineering und Hardware-Design
Towards One-Pass Synthesis
Spectral Techniques in VLSI CAD
Formal Verification of Circuits
Evolutionary Algorithms for VLSI CAD
Binary Decision Diagrams: Theory and Implementations
Graphenbasierte Funktionsdarstellung
Functional Decision Diagrams und ihre Anwendung
Modulares und rekonfigurierbares Systemdesign für Unterwasserfahrzeuge
Verifizierung für autonome Unterwassersysteme
AQuCiDe: Architecture Aware Decomposition of Quantum Circuits
Polynomial Formal Verification of Carry Look-Ahead Adders
Start Small But Dream Big: On Choosing a Static Variable Order for Multiplier BDDs
SAT-Based Key Determination Attack for Improving the Quality Assessment of Logic Locking Mechanisms
Toward System-Level Assertions for Heterogeneous Systems
Empowering the Design of Reversible and Quantum Logic with Decision Diagrams
Das Bremen Ambient Assisted Living Lab und darüber hinaus – Intelligente Umgebungen, smarte Services und Künstliche Intelligenz in der Medizin für den Menschen
Intelligent Umgeben: Ausgewählte Einblicke in 10 Jahre Bremen Ambient Assisted Living Lab
Automatic Design of Microfluidic
Devices: An Overview of Platforms
and Corresponding Design Tasks
Extensible and Configurable RISC-V Based Virtual Prototype
Approximate Memory: Data Storage in the Context of Approximate Computing
Modular and Reconfigurable System Design for Underwater Vehicles
Verification for Autonomous Underwater Systems
An Efficient Nearest Neighbor Design for 2D Quantum Circuits
Assistenzsysteme der Zukunft – Nutzen und Potenzial künstlicher Intelligenz
In-Memory Computing:
The Integration of Storage and Processing
Approximate Hardware Generation Using Formal Techniques
Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach
Computational Complexity of Error Metrics in Approximate Computing
On the Application of Formal Fault Localization to Automated RTL-to-TLM Fault Correspondence Analysis for Fast and Accurate VP-Based Error Effect Simulation: A Case Study
Logic Synthesis for Majority based In-Memory Computing
Formal Verification of SystemC-based Cyber Components
A framework for reversible circuit complexity
Formal Specification Level
SyReC: A Programming Language for Synthesis of Reversible Circuits
Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis
SMT-based Stimuli Generation in the SystemC Verification Library
Synthesis of Boolean Functions in Reversible Logic
Non-Clausal SAT and ATPG
Debugging Contradictory Constraints in Constraint-based Random Simulation
SWORD: A SAT like Prover Using Word Level Information
An Integrated SystemC Debugging Environment
Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques
Exact BDD Minimization for Path-Related Objective Functions
Stuck-At-Fault Testability of SPP Three-Level Logic Forms
Exploration of Sequential Depth by Evolutionary Algorithms
Processor Verification
Automatic Test Pattern Generation
System-level validation using formal techniques
Exploration of Design Alternatives for Reducing Idle Time in Shor’s Algorithm: A Study on Monolithic and Distributed Quantum Systems
Advanced And-Inverter Graph Decomposition Technique for Reducing Circuit Complexity
Polynomial formal verification parameterized by cutwidth properties of a circuit using Boolean satisfiability
LLM-assisted Bug Identification and Correction for Verilog HDL
Efficient Evolution of Variable Ordering for Binary Decision Diagram Optimization
veriSiM: Formal Verification of Spice Netlists for MAGIC-Based Logic-in-Memory
LLM-assisted Bug Identification and Correction for Verilog HDL
FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits
Why less is sometimes more: Using Boolean literals to solve 2048
Lower bound proof for the size of BDDs representing a shifted addition
Polynomial Formal Verification of a RISC-V Processor
MESSI: Task Mapping and Scheduling Strategy for FPGA-based Heterogeneous Real-Time Systems
Polynomial Formal Verification of Multi-Valued Approximate Circuits within Constant Cutwidth
Automated polynomial formal verification using generalized binary decision diagram patterns
Linear Formal Verification of Multi-Valued Logic Circuits within Constant Cutwidth Architectures
Auto-OPS: A Framework For Automated Optical Probing Simulation on GDS-II
qSAT: Design of an Efficient Quantum Satisfiability Solver for Hardware Equivalence Checking
Correct and Verify - CAV: Exploiting Binary Decision Diagrams to Enable Formal Verification of Approximate Adders with Correct Carry Bits
EnR: Extend and Reduce Methodology to Enable Formal Verification of Truncated Adders
Determining the Effect of Feedback Quality on User Engagement on Online Idea Crowdsourcing Platforms Using an AI model | Proceedings of the ACM on Human-Computer Interaction
Lower the RISC: Designing optical-probing-attack-resistant cores
Exploiting the Extended Neighborhood of Hexagonal Qubit Architecture for Mapping Quantum Circuits
OPTI-Sim: Performing Optical Probing Simulation on Layout Design Files
Determining the Effect of Feedback Quality on User Engagement on Idea Crowdsourcing Platforms using an AI model
veriSIMPLER : An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing
cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits
Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices
Special issue on in-memory computing: Circuits, system, architecture and verification
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style
Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation
ReSG: A Data Structure for Verification of Majority based In-Memory Computing on ReRAM Crossbars
KI-gestützte Optimierung repetitiver Prozesse - Eine Kodierungstechnik für repetitive Prozesse in der evolutionären Optimierung
AI-Driven and Automated MRI Sequence Optimization in Scanner-Independent MRI Sequences Formulated by a Domain-Specific Language
Impact of Sneak Paths on In-Memory Logic Design in Memristive Crossbars Information Technology
A Novel Default Risk Prediction and Feature Importance
Analysis Technique for Marketplace Lending using
Machine Learning
MARADIV: Library of MAGIC based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors
Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT
IMAGIN: Library of IMPLY and MAGIC NOR Based Approximate Adders for In-Memory Computing
The MicroRV32 framework: An Accessible and Configurable Open Source RISC-V Cross-Level Platform for Education and Research
Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype
Feed-Forward learning algorithm for resistive memories
FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications
Early SoCs Information Flow Policies Validation using SystemC-based Virtual Prototypes at the ESL
Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits
Power-aware Test Scheduling Framework for IEEE 1687 Multi-Power Domain Networks using Formal Techniques
Towards Quantification and Visualization of the Effects of Concretization during Concolic Testing
CoMIC: Complementary Memristor based in-memory computing in 3D architecture
Template-based mapping of reversible circuits to IBM quantum computers
SymEx-VP: An Open Source Virtual Prototype for OS-Agnostic Concolic Testing of IoT Firmware
Unlocking Approximation for In-Memory Computing with Cartesian Genetic Programming and Computer Algebra for Arithmetic Circuits
Verzahnung von Data Stewardship und Data Science – Wege und Perspektiven
Disziplinübergreifendes Modell zur Ausbildung von Forschungsdatenmanagement und Data Science Kompetenzen: „Data Train – Training in Research Data Management and Data Science“
Advanced Virtual Prototyping for Cyber-Physical Systems using RISC-V: Implementation, Verification and Challenges
RevSCA-2.0: SCA-based Formal Verification of Non-trivial Multipliers using Reverse Engineering and Local Vanishing Removal
Towards RISC-V CSR Compliance Testing
Parallel Computing of Graph-Based functions in ReRAM
An ant colony based mapping of quantum circuits to nearest neighbor architectures
Adaptive Simulation with Virtual Prototypes in an Open-Source RISC-V Evaluation Platform
Through the Looking Glass: Automated Design Understanding of SystemC-based VPs at the ESL
On the Difficulty of Inserting Trojans in Reversible Computing Architectures
An Improved Heuristic Technique for Nearest Neighbor Realization of Quantum Circuits in 2D Architecture
Improving the Designs of Nearest Neighbor Quantum Circuits for 1D and 2D Architectures
ReCoFused partial reconfiguration for secure moving-target countermeasures on FPGAs
Advanced Exact Synthesis of Clifford+T Circuits
Overcoming the Trade-off Between Accuracy and Compactness in Decision Diagrams for Quantum Computation
On the Impact of the Synchronization Constraint and Interconnections in Quantum-dot Cellular Automata
PREASC: Automatic Portion Resilience Evaluation for Approximating SystemC-based Designs using Regression Analysis Techniques
RISC-V based Virtual Prototype: An Extensible and Configurable Platform for the System-level
Reversible Circuits: IC/IP Piracy Attacksand Countermeasures
Near Zero-Energy Computation Using Quantum-dot Cellular Automata
Placement & Routing for Tile-based Field-coupled Nanocomputing Circuits is NP-complete
Combining Sequentialization-based Verification of Multi-Threaded C Programs with Symbolic Partial Order Reduction
Security Validation of VP-based SoCs Using Dynamic Information Flow Tracking
Automated Non-intrusive Analysis of Electronic System Level Designs
Determining Application-specific Knowledge for Improving Robustness of Sequential Circuits
The complexity of error metrics
On the complexity of design tasks for Digital Microfluidic Biochips
Evaluation of (power) side-channels
in cryptographic implementations
Arduinos in der Schule -
Lernen mit Mikrocontrollern
Verifying SystemC using Intermediate Verification Language and Stateful Symbolic Simulation
Logic synthesis for RRAM-based in-memory computing
Behaviour Driven Development for Hardware Design
An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs
An Energy-aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata
Frame Conditions in the Automatic Validation and Verification of UML/OCL Models: A Symbolic Formulation of modifies only Statements
Synthesis of optical circuits using binary decision diagrams
A PLiM computer for the IoT
Towards a Verification Flow Across Abstraction Levels:
metaSMT: Focus On Your Application And Not On Solver Integration
Verifying the Structure and Behavior in UML/OCL Models Using Satisfiability Solvers
Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits
Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability
On Optimization-based ATPG and its Application for Highly Compacted Test Sets
Time-resolved detection of diffusion limited temperature gradients inside single isolated burning droplets using Rainbow Refractometry
Complexity of Reversible Circuits and their Quantum Implementations
Analyzing Inconsistencies in UML/OCL Models
KI-Unterstützung im Systementwurf –
Wenn Computer lernen, wie Computer
arbeiten
Atomic distributions in crystal structures solved by Boolean satisfiability techniques
SyReC: A Hardware Description Language for the Specification and Synthesis of Reversible Circuits
Analyzing SystemC Designs: SystemC Analysis Approaches for Varying Applications
Scalable One-Pass Synthesis for Digital Microfluidic Biochips
QMDDs: Efficient Quantum Function Representation and Manipulation
Embedding of Large Boolean Functions for Reversible Logic
Ancilla-free synthesis of large reversible functions using binary decision diagrams
Benefits of illustrations and videos for technical documentations
Incorporating User Preferences in Many-Objective Optimization using Relation epsilon-Preferred
Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures
Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic
An Approach to Reversible Logic Synthesis Using Input and Output Permutations
Special Issue on Reversible Computation
An effective fault ordering heuristic for SAT-based dynamic test compaction techniques
Testing integrated circuits
Upper bounds for reversible circuits based on Young subgroups
Formale Verifikation von UML-basierten Spezifikationen, Prüfung der Korrektheit von Systementwürfen vor deren Implementierung
Considering Nearest Neighbor Constraints of Quantum Circuits at the Reversible Circuit Level
Quantum circuits employing roots of the Pauli matrices
Trading Off Circuit Lines and Gate Costs in the Synthesis of Reversible Logic
A Formal Model for Embedded Brain Reading
Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits
RevKit: An Open Source Toolkit for the Design of Reversible Circuits
Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis
Automatic TLM Fault Localization for SystemC
Special Issue on Reversible Computation
RevKit: A Toolkit for Reversible Circuit Design
A Highly Fault-Efficient SAT-Based ATPG Flow
Efficient Data Structures and Methodologies for SAT-based ATPG providing High Fault Coverage in Industrial Application
Effective Robustness Analysis using Bounded Model Checking Techniques
Synthesis of Quantum Circuits for Linear Nearest Neighbor Architectures
Debugging Reversible Circuits
BDD-Based Synthesis of Reversible Logic 
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen
Towards Fully Automatic Synthesis of Embedded Software
Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic
Incremental Solving Techniques for SAT-based ATPG
Synthese reversibler Logik
MONSOON: SAT-based ATPG for Path Delay Faults Using Multiple-Valued Logics
Overcoming the limitations of data introspection for SystemC
Formale Verifikation von logistischen Prozessmodellen
Weighted A* search - unifying view and application
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern
Exact Synthesis of Elementary Quantum Gate Circuits
Advanced Verification by Automatic Property Generation
Exact Multiple Control Toffoli Network Synthesis with SAT Techniques
Modeling and Proving Completeness in Formal Verification of Counting Heads
On Acceleration of SAT-based ATPG for Industrial Designs
Improved SAT-based Reachability Analysis with Observability Don’t Cares
On the Construction of Small Fully Testable Circuits with Low Depth
Logic Minimization and Testability of 2-SPP Networks
Analyzing Functional Coverage in Bounded Model Checking
Automatic Fault Localization for Property Checking
BDD-based Verification of Scalable Designs
Building Free Binary Decision Diagrams Using SAT Solvers
An Integrated Approach for Combining BDDs and SAT Provers
Technische Dokumentation von Soft- und Hardware in
eingebetteten Systemen
Exact minimisation of path-related objective functions for binary decision diagrams
Testability of SPP Three-Level Logic Networks in Static Fault Models
The Effect of Improved Lower Bounds in Dynamic BDD Reordering
Minimizing the Number of Paths in BDDs
- Theory and Algorithm
Combining Ordered Best-First Search with Branch and Bound for Exact BDD Minimization
System Level Validation Using Formal Techniques
Generic Implementation of Multi-Valued Decision Diagram Packages
Project-Based Learning in Student Teams in Computer Science Education
Synthesis of Fully Testable Circuits from BDDs
Methods for Construction of Recursive Algorithms for Reed-Mulle-Fourier Polarity Matrices Calculation
Using Word-Level Information in Formal Hardware Verification
An Improved Branch and Bound Algorithm for Exact BDD Minimization
Recursive Bi-Partitioning of Netlists for Large Number of Partitions
Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams
Exact Routing with Search Space Reduction
Computer Architecture Core of Knowledge for Computer Science Studies
Polynomial Formal Verification of Multipliers
Low Power Optimization Techniques for BDD Mapped Circuits Using Temporal Correlation
Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts
Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs
Minimization of Word-level Decision Diagrams
Minimization of Free BDDs
Verifying Integrity of Decision Diagrams
Heuristic Learning based on Genetic Programming
Dynamic Re-Encoding During MDD Minimization
History-based Dynamic BDD Minimization
Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld
Fault Simulation in Multi-Valued Logic Networks
Binary Decision Diagrams in Theory and Practice
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits
Decision Diagram Method for Calculation of Pruned Walsh Transform
Using Lower Bounds during Dynamic BDD Minimization
ACTion: Combining Logic Synthesis and Technology Mapping for MUX based FPGAs
EXOR transform of inputs to design efficient two-level AND/EXOR adders
Boolean Function Representation and Spectral Characterization Using AND/OR Graphs
Genetic Algorithm for Minimization of fixed polarity Reed-Muller expressions
On the Computational Power of Linearly Transformed BDDs
Fast Exact Minimization of BDDs
Pseudo Kronecker Expressions for Symmetric Functions
ETDD-based synthesis of two-dimensional cellular arrays for multi-output incompletely specified Boolean functions
OKFDD minimization by genetic algorithms with application to circuit design
Testability of 2-Level AND/EXOR Circuits
BDD Minimization Using Symmetries
On Variable Ordering and Decomposition Type Choice in OKFDDs